CN100386964C - Amplifier of power supply by AC power supply in switch condenser circuit - Google Patents

Abstract

The present invention relates to an amplifier which uses an AC power source for supplying electricity, is used in a switched capacitor circuit and belongs to the technical field of the switched capacitor circuit. The present invention is characterized in that the input end of the traditional switched capacitor amplifier which is supplied with electricity a DC power source is connected in parallel with a switch which is closed at the time of sampling and is opened at the time of magnification, and the output end of the amplifier is connected in series with the other switch which is opened at the time of sampling and is closed at the time of amplification; simultaneously, the amplifier uses an AC power source signal which is synchronous with an amplification clock signal when phases are amplified and has the same pulse width as the amplification clock signal as a power source input, the state conversion times of the AC power source when the AC power source is in the state of low level and energy saving in a sampling phase and in the state of normal operation in an amplification phase are as small as possible and are equal. Because when the circuit is in a sampling stage, the present invention closes a circuit element with the maximum energy consumption, namely the amplifier, compared with the amplifier which uses the DC power source for supplying the electricity in the switched-capacitor circuit, the present invention has the advantage of low power consumption.

Description

Use the amplifier of ac power supply in the switched-capacitor circuit

Technical field

Be to adopt the low-power consumption analog circuit and the mixed signal circuit design of switched-capacitor circuit technology with the direct applied technical field of the amplifier of ac power supply in the switched-capacitor circuit.The circuit that proposes is a kind of basic switch capacitor circuit unit that is used to design low-power consumption simulation and mixed signal circuit.

Background technology

Along with the progress of integrated circuit fabrication process, the scale and the design complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem also more and more obtain paying attention to.Particularly under present integrated circuit SOC (System-On-a-Chip) mentality of designing and in based on reusable IP kernel (Reusable Intellectual Property Cores) design style, increasing analog module and digital circuit blocks are integrated in the same system, and the ratio that the power consumption of analog module accounts for whole SOC system power dissipation constantly increases (sees document Akira Matsuzawa, " Low-Voltage and Low-Power Circuit Design for MixedAnalog/Digital Systems in Portable Equipment ", IEEE Journal of Solid-State Circuits, Vol29, pp.470-480,1994.).For digital circuit blocks, the working power voltage that reduces circuit is the method for very effective reduction circuit power consumption, but this method can make the signal to noise ratio circuit performances such as (SNR:Signal-to-NoiseRatio) of analog circuit worsen for analog module on the contrary.At present, the power consumption for reducing digital circuit blocks and analog module does not also have a kind of unified low power consumption design method; For analog module, make full use of the work characteristics of various analog circuit units, can reduce the power consumption of circuit equally to a great extent.

Switched-capacitor circuit (SC:Switched-Capacitor Circuit) is a kind of digital/analog converter that is widely used in, the circuit unit of analog/digital converter and Design of Filter.The power consumption that reduces switched-capacitor circuit can reduce the power consumption of whole SOC system greatly.Traditional method for designing is conceived to optimize simultaneously the power consumption of the operation transconductance amplifier (OTA:Operational Tansconductance Amplifier) in the switched-capacitor circuit and the characteristic of setting up of closed loop (is seen document Silveira, F.andFlandre, D, " Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time " in Proc.15th Symposium on Integrated Circuits and Systems Design, Pages.247-253Sept.9-142002.).Adopt two Sampling techniques to set up the sampling clock frequency of the following switched-capacitor circuit of prerequisite of characteristic and double and (see document PaulJ.Hurst not influencing circuit, " Double Sampling In Switched-CapacitorDelta-Sigma A/D Converters " in Proc.IEEE International Symposium on Circuits and Systems, New Orleans, LA USA, pp.902-905, May.1-3,1990.).Document (P.S.Cusinato, F.Baschirotto, A., " Reducing the power consumption in high-speed/spl Sigma//spl Delta/bandpass modulators ", IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing, Vol.48, pp.952-960,2001.) according to the clock phase of switched-capacitor circuit work, the combining adaptive biasing technique reduces circuit power consumption.The switched-OPAMP technology adopts the amplifier with two states of ON/OFF to replace the switch mosfet circuit, be fit to very much low supply voltage work, and then have less circuit power consumption and (see document A.Baschirotto and R.Castello, " A 1V CMOSfully-differential switched-opamp bandpass simga-delta modulator " in Proc.23 ^RdEuropeanSolid-State Circuits Conference, Southampton, UK, Sept.16-18,1997.).

Basic switched-capacitor circuit unit comprises that switched capacitor amplifier (Switched-Capacitor Amplifier) and switched-capacitor integrator (Switched-Capacitor Integrator) (see document Behzad Razavi, Design of Analog CMOSIntegrated Circuits.NY:McGraw-Hill Inc., 2001.).Following circuit analysis will be mainly to adopting DC power supply (DCP:Direct-Current Power) powered switch dielectric amplifier circuit (DCPSC amplifier) to describe, as shown in Figure 1.The switch mosfet S in the circuit wherein ₁, S ₂And S ₃By two-phase clock signal C K1 and the CK2 control that do not overlap, as shown in Figure 2, the clock signal C K that this two-way clock signal that do not overlap is T by the circuit external cycles produces through the two-phase clock signal generating circuit that do not overlap.

The DCPSC amplifier directly adopts traditional DCP power supply power supply, sees Fig. 1, and its operation principle can simply be described as: at circuit sampling phase place (CK1), switch mosfet S ₁And S ₂Closure, switch S ₃Open circuit node X _DCAnd Y _DCVoltage is connected to " virtual earth " by the negative input end point of OTA amplifier; At the amplification phase place (CK2) of circuit, switch mosfet S ₃Closure, switch S ₁And S ₂Open, be stored in capacitor C in the circuit sampling stage ₁On electric charge all transfer to capacitor C ₂Therefore, input signal V _InOutput at circuit is amplified to original

Doubly.

Summary of the invention

Employing AC power (ACP:Alternative-Current Power) the powered switch condenser network technology that patent of the present invention proposes, characteristics when having made full use of switched-capacitor circuit work, directly adopt the ACP power supply to give switched capacitor amplifier (ACPSC amplifier) power supply, on circuit structure and circuit optimization method, be different from traditional DCPSC amplifier.As shown in Figure 2, ACP power supply signal and CK2 signal Synchronization are in sampling phase (CK1) at switched-capacitor circuit, and OTA external capacitive offered load is less with respect to amplifying phase place (CK2), so the ACP power supply signal is in low level power save mode (power OFF); When circuit enters the amplification phase place, the ACP power supply signal is in operate as normal level state (powerON) accordingly.Wherein, in order to guarantee to obtain the set up characteristic identical with the DCPSC amplifier, the ACP power supply is in the duration (t of operate as normal power supply _ON) be set at identical with the pulse duration of CK2 clock signal, to guarantee enough circuit (t settling time _s); Simultaneously, ACP power supply existence change-over time when the conversion of low level power save mode and operate as normal level state, TR and TF in our analysis, suppose TR=TF.

If directly adopt the ACP power supply, then when the ACP power supply is in the low level power save mode, because OTA circuit cisco unity malfunction causes nodes X to the power supply of DCPSC amplifier _DCVoltage can not be connected to " virtual earth " by the negative input pin of OTA, cause circuit working unusual.The ACPSC amplifier circuit that the present invention proposes shown in Fig. 3 (a), relatively with Fig. 1 in the DCPSC amplifier circuit, keep apart for capacitance network and employing ACP are powered and be in power save mode OTA, circuit has increased by two switch mosfet S _I1And S _I2At sampling phase (CK1), the ACP power supply signal is in low level power save mode, switch S ₁And S ₂Closure, switch S ₃Open.The while switch S _I1Closure, nodes X _ACBe directly connected to the ground terminal of circuit; Switch S _I2Open, guarantee the output voltage V of amplifier _OutCan not be subjected to being in the influence of the OTA exit point of power save mode.The ACPSC amplifier is in the equivalent electric circuit of sampling phase shown in Fig. 3 (b), is stored in capacitor C in this stage ₁On electric charge be,

$Q_{\mathrm{sampling}}=(V_{\mathrm{in}}-V_{X_{\mathrm{AC}}})\·C_1---\left(1\right)$

The ACPSC amplifier is in the equivalent electric circuit of amplification phase place (CK2) shown in Fig. 3 (c), and this is identical with the equivalent electric circuit that the DCPSC amplifier is in the amplification phase place.At this moment, switch S _I2Closure, switch S simultaneously _I1Open, the ACP power supply signal is in the operate as normal level state, circuit node X _ACVoltage be connected to " virtual earth " of circuit by the OTA negative input end point that is in normal operating conditions.In this process, from capacitor C ₁Transfer to capacitor C ₂On electric charge be,

$Q_{\mathrm{amplifying}}=(V_{\mathrm{out}}-{V_X}_{\mathrm{AC}})\·C_2---\left(2\right)$

Therefore can obtain the voltage gain identical with the DCPSC amplifier,

$A_{\mathrm{ACPSC}}=\frac{C_1}{C_2}---\left(3\right)$

The invention is characterized in: it contains:

First switch S ₁, its end and input signal end V _InLink to each other this input signal end V _InEnd is sampling or amplifying signal input;

The 3rd switch S ₃, its end and above-mentioned first switch S ₁The other end link to each other above-mentioned the 3rd switch S ₃Other end ground connection;

First capacitor C ₁, its end and above-mentioned first switch S ₁The other end link to each other;

Amplifier OTA, its negative input end X _ACWith above-mentioned first capacitor C ₁The other end link to each other, the positive input terminal ground connection of above-mentioned amplifier OTA, the power input of above-mentioned amplifier OTA meets ac supply signal ACP, this ac supply signal ACP and pulse duration synchronous with amplification clock signal C K2 equates; Ac supply signal ACP is in the low level power save mode from sampling phase, and to be converted to the time of amplifying the phase place normal operating conditions be the first state exchange time T R, to be in the time that normal operating conditions is converted to sampling phase low level power save mode be the second state exchange time T F to ac supply signal ACP from amplifying phase place, and the first state exchange time T R equates with the second state exchange time T F;

The 5th switch S _I2, the output of its above-mentioned amplifier OTA of a termination, above-mentioned the 5th switch S _I2Other end Y _ACThe amplifying signal output V that connects switched capacitor amplifier _Out

Second capacitor C ₂, its two ends respectively with the negative input end X of above-mentioned amplifier OTA _ACWith above-mentioned the 5th switch S _I2Other end Y _ACLink to each other;

Second switch S ₂, it and above-mentioned second capacitor C ₂In parallel;

The 4th switch S _I1, the negative input end X of its above-mentioned amplifier OTA of a termination _AC, the 4th switch S _I1Other end ground connection;

When sampling phase, first switch S ₁, second switch S ₂, the 4th switch S _I1Closure, the 3rd switch S ₃, the 5th switch S _I2Open;

When amplifying phase place, first switch S ₁, second switch S ₂, the 4th switch S _I1Open the 3rd switch S ₃, the 5th switch S _I2Closed.

By above circuit analysis, can find that the ACPSC amplifier can realize the circuit function identical with the DCPSC amplifier, because the ACPSC amplifier is in sample phase the power-off of the circuit element OTA of energy consumption maximum at circuit, make the ACPSC amplifier very big power consumption advantages be arranged simultaneously with respect to the DCPSC amplifier.If the state exchange time T R of ACP power supply is enough short, adopt the energy-saving efficiency of the maximum that can obtain behind the ACPSC circuit engineering to be expressed as so,

${\mathrm{\η}}_{\max }=(1-\frac{t_{\mathrm{ON}}}{T})\·100\%=(1-\frac{t_s}{T})\·100\%---\left(4\right)$

The invention has the beneficial effects as follows: with existing DCPSC amplifier circuit technology relatively, the present invention can obtain under the identical prerequisite of setting up characteristic, the reduction of ACPSC amplifier circuit power consumption is up to 40%.Circuit is realized fairly simple simultaneously.Compare with other low-power consumption switched-capacitor circuit methods for designing, the ACPSC circuit engineering that the present invention proposes exists to be coordinated mutually with the digital circuit low power consumption design method, forms the potentiality of unified SOC low consumption circuit method for designing.

Description of drawings

Fig. 1. adopt DC power supply (DCP) powered switch dielectric amplifier circuit diagram;

Fig. 2. the two-phase clock signal C K1 that do not overlap, CK2 and ACP power supply sequential chart:

A clock signal C K1,

B clock signal C K2,

C ac supply signal ACP;

Fig. 3 .ACPSC amplifier circuit structure chart:

A circuit diagram and isolating switch S _I1And S _I2,

B sampling phase equivalent electric circuit,

C amplifies the phase place equivalent electric circuit;

Fig. 4 .ACPSC amplifier circuit transient state input and output oscillogram:

A V _InAnd V _OutWaveform,

The conversion of signals waveform that b is once complete;

Fig. 5 .ACPSC amplifier and DCPSC amplifier transient state source current I _DdThe comparison diagram of waveform;

Fig. 6. difference is set up under the precision conditions ACPSC amplifier normalization settling time

With ACP signal normalization TR/T change-over time graph of a relation.

Embodiment

The ACPSC circuit engineering adopts AC power ACP power supply, ACP power supply and the two-phase clock signal C K1 that do not overlap, CK2 cooperation.When the ACPSC circuit working at sampling phase (CK1), the ACP power supply enters the low level power save mode, makes energy dissipation device OTA enter low power consumpting state, reaches the target that reduces energy consumption; When the ACPSC circuit working at signal processing phase place (CK2, amplify phase place), the ACP power supply enters the operate as normal level state, OTA begins operate as normal, carries out signal processing.The ACP power supply carries out state exchange, and to need the time be TR.Adopt ACPSC circuit engineering design switched-capacitor circuit, on circuit structure, need to increase isolating switch.The effect of these switches is to guarantee when circuit working during at sampling phase, can be circuit node X _ACVoltage determine at " virtual earth ", guarantee that simultaneously the OTA output be in low power consumpting state does not influence output circuit node Y _ACLevel.Thereby guaranteed that the ACPSC circuit engineering satisfies law of conservation of charge, can realize the circuit function identical with the DCPSC circuit engineering.

For relatively the ACPSC circuit engineering is with respect to the energy-saving effect of DCPSC circuit engineering, we adopt CSMC 5-V0.6 μ m technology, use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the emulation comparative analysis.We are example with ACPSC amplifier and DCPSC amplifier mainly still, have also provided the simulation result to the power consumption of ACPSC integrator and DCPSC integrator at last.In circuit simulation, the OTA circuit adopts folding cascode (folded cascode) structure, input signal V _InBe that peak-to-peak value is 1V, frequency is the sinusoidal signal of 20KHz.External reference clock signal is that duty ratio is 50%, and frequency is the square-wave signal of 200KHz, the two-phase that is used to produce same frequency do not overlap clock signal C K1 and CK2.The ACP power supply signal is that frequency is the 200KHz trapezoidal wave signal, and wherein state exchange time T R is 0.25 μ s.The output load capacitance of all artificial circuits is 10pF.

The transient state emulation output waveform of ACPSC amplifier is shown in Fig. 4 (a).It shown in Fig. 4 (b) the once complete conversion of signals waveform of ACPSC amplifier.Can see clearly that from the circuit simulation waveform ACPSC amplifier can well satisfy the requirement of switched-capacitor circuit amplifier sequential.

Figure 5 shows that ACPSC amplifier and DCPSC amplifier transient state source current I _DdThe comparison of waveform.When the ACP power supply was in the low level power save mode, the source current i (ACP) of ACPSC amplifier was much smaller than DCPSC amplifier power supply current i (DCP).When the ACP power supply begins when high level state is changed from low level state, i (ACP) begins to increase, and is established to and the quite approaching numerical value of i (DCP) before the rising edge that amplifies phase clock signal CK2 arrives.Guaranteed that the ACPSC amplifier sets up and have the power consumption less with respect to the DCPSC amplifier under the prerequisite of characteristic satisfying circuit.

ACPSC amplifier and DCPSC amplifier transient state emulation average power consumption result are as shown in table 1, and the simulation result of corresponding integrator circuit compares in table 1 equally.

Table 1ACPSC amplifier circuit and DCPSC amplifier circuit transient state emulation average power consumption are relatively

	DCPSC(mW)	ACPSC(mW)	Power Cutback ratio (%)
				Simulation result	12.26	7.74	36.9

In formula (4), we suppose that TR is enough little.But the value of TR has very big influence to the characteristic of setting up of circuit.Because TR is more little,, need the more time allowance to guarantee that the OTA circuit satisfies the specific required precision of setting up though can save more energy.So when adopting ACPSC circuit engineering design low-power consumption switched-capacitor circuit unit, existence is to the circuit energy-saving effect and set up the problem that the characteristic compromise is considered, as shown in Figure 6.Among Fig. 6, set up settling times all under the precision conditions all by the result after DCPSC amplifier normalization settling time under the same terms in difference, the abscissa in the diagram is ACP power supply signal normalization TR/T change-over time.

Claims (1)

1. use the amplifier of ac power supply in the switched-capacitor circuit, it is characterized in that it contains:

First switch (the S ₁), its end and input signal end (V _In) link to each other this input signal end (V _In) hold to sampling or the amplifying signal input;

The 3rd switch (S ₃), its end and the above-mentioned first switch (S ₁) the other end link to each other above-mentioned the 3rd switch (S ₃) other end ground connection;

First electric capacity (the C ₁), its end and the above-mentioned first switch (S ₁) the other end link to each other;

Amplifier (OTA), its negative input end (X _AC) and the above-mentioned first electric capacity (C ₁) the other end link to each other, the positive input terminal ground connection of above-mentioned amplifier (OTA), the power input of above-mentioned amplifier (OTA) connects ac supply signal (ACP), this ac supply signal (ACP) with amplify the synchronous and pulse duration of clock signal (CK2) and equate; Ac supply signal (ACP) is in the low level power save mode from sampling phase, and to be converted to the time of amplifying the phase place normal operating conditions be the first state exchange time (TR), to be in the time that normal operating conditions is converted to sampling phase low level power save mode be the second state exchange time (TF) to ac supply signal (ACP) from amplifying phase place, and the first state exchange time (TR) equated with the second state exchange time (TF);

The 5th switch (S _I2), the output of its above-mentioned amplifier of a termination (OTA), above-mentioned the 5th switch (S _I2) the other end (Y _AC) connect the amplifying signal output (V of switched capacitor amplifier _Out);

Second electric capacity (the C ₂), its two ends respectively with the negative input end (X of above-mentioned amplifier (OTA) _AC) and above-mentioned the 5th switch (S _I2) the other end (YA _C) link to each other;

Second switch (S ₂), it and the above-mentioned second electric capacity (C ₂) parallel connection;

The 4th switch (S _I1), the negative input end (X of its above-mentioned amplifier of a termination (OTA) _AC), the 4th switch (S _I1) other end ground connection;

When sampling phase, the first switch (S ₁), second switch (S ₂), the 4th switch (S _I1) closure, the 3rd switch (S ₃), the 5th switch (S _I2) open;

When amplifying phase place, the first switch (S ₁), second switch (S ₂), the 4th switch (S _I1) open the 3rd switch (S ₃), the 5th switch (S _I2) closure.

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