CN100385633C - Method for fabricating MOSFET element - Google Patents
Method for fabricating MOSFET element Download PDFInfo
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- CN100385633C CN100385633C CNB2004100315281A CN200410031528A CN100385633C CN 100385633 C CN100385633 C CN 100385633C CN B2004100315281 A CNB2004100315281 A CN B2004100315281A CN 200410031528 A CN200410031528 A CN 200410031528A CN 100385633 C CN100385633 C CN 100385633C
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Abstract
The present invention relates to a method for manufacturing elements of metal oxide semiconductor transistors. In the method, firstly, ions are injected by using a gate and a lining layer as masks so that source electrodes / drain electrodes are formed in a substrate at both sides of the gate; afterwards, the lining layer is etched so as to reduce the thickness of the lining layer; ions are injected for another time so that an annular doping area is formed in the periphery of the contours of the source electrodes / the drain electrodes. The annular doping area surrounding the source electrodes / the drain electrodes is close to a channel area, and is little overlapped with the source electrodes / the drain electrodes so as to simultaneously keep stable starting voltage of the elements and achieve the purpose of reducing junction leakage currents.
Description
Technical field
The present invention relates to the manufacture method of integrated circuit, particularly relate to a kind of manufacture method of metal-oxide semiconductor transistor component.
Background technology
When the integrated level of element constantly increases, metal oxide semiconductor transistor (metal-oxide-semiconductor field effect transistor; MOSFET) size of component also must constantly be dwindled.When component size littler, the channel length of metal oxide semiconductor transistor (channellcngth), grid length just also shortens thereupon.But, after channel length shortens to a certain degree, many problems of can deriving.This phenomenon is called as short-channel effect (short channel effect).
When metal oxide semiconductor transistor in when operation, source electrode and drain electrode overlap with raceway groove because of understanding with substrate (substrate) depletion region that reverse bias produced (depletion region), make length of effective channel shorter than former the design's length.Under short-channel effect, it is very high that raceway groove and depletion region produce the ratio that overlaps.Shared by the depletion region of source electrode and drain electrode owing to the part raceway groove this moment, thereby cause cut-in voltage (the threshold voltage of metal oxide semiconductor transistor, Vt) dwindle with channel length and descend rapidly (Vt roll-off), thereby produce and time open beginning electric leakage (sub-threshold leakage).Another problem is, because of electrical breakdown (punch through) leakage current path via the raceway groove below that effect caused.This is because when channel length is dwindled, the mutual short circuit of depletion region that source electrode and draining is produced and taking place.
In order to improve the problem that the above short-channel effect is derived, in the conventional semiconductor manufacturing process when making metal oxide semiconductor transistor, identical through the formation of the below of the source/drain extension area of being everlasting with the doping type (can be P type or N type) of substrate, but the higher zone of doping content.This zone generally abbreviates ring doped region (halo) or bag shape (pocket) zone as.The manufacturing process that forms the ring doped region is called the ring doped region and injects (halo implantation).Encircle the mode of wherein a kind of mode that doped region injects for injecting with rake angle.This ring doped region has the effect of covering to the electric field of source/drain, can effectively improve short-channel effect.
Yet the mode of encircling the doped region injection in the conventional semiconductor manufacturing process has shortcoming.Fig. 1 has source/drain and the transistorized section of structure of N type metal oxide semiconductor that encircles doped region.Please refer to Fig. 1, in a P type substrate 100, a grid 110 is arranged in this structure.This grid 110 comprises a gate dielectric layer (gate dielectric layer) 120, one conductor layer 130 and a cap layer (caplayer) 136.This conductor layer 130 has a polysilicon layer 132 and a metal silicide layer 134.This grid 110 utilizes a photoetching corrosion manufacturing process and defines.
After forming this grid 110, a lining (liner) 140 is formed at the sidewall of this conductor layer 130.Then with this grid 110 therewith lining 140 be that mask carries out a P type ion and injects, with formation one P type ring doped region 160 in this substrate 100 in these grid 110 outsides.And then with this grid 110 therewith lining 140 be that mask carries out a N type ion and injects, in this substrate 100 in these grid 110 outsides, to form a N type source/drain 150.
Fig. 2 is for carrying out the section of structure after the lining etching to N type metal oxide semiconductor transistor arrangement among Fig. 1.Please refer to Fig. 2, after this lining 140 of etching, the thickness of this lining 140 reduces.Then, form clearance walls (spacer does not illustrate) afterwards in lining 140 both sides therewith at this grid 110, will dielectric layer (not illustrating, for example silica) on said structure.So the purpose of this lining 140 of etching is to reduce the depth-to-width ratio (aspect ratio) between neighboring gates, insert ability and the etched manufacturing process window of follow-up contact hole (contact window) (process window) to increase dielectric layer.
By Fig. 1,2 as can be known, because the mask when this lining 140 injects as two secondary ions, and this lining 140 of etching just carries out after ion injects manufacturing process, so that N type source/drain 150 is not defined by etched this lining 140 as yet with the boundary of P type ring doped region 160 in substrate 100 by script.So less and can't surround N type source/drain 150 ideally near the P type ring doped region 162 of raceway groove, as shown in Figure 2.This shortcoming makes the problem of short-channel effect, comprises too high inferior beginning electric leakage and the low excessively cut-in voltage of opening, and can not effectively improve.Better improved and the doping content of P type ring doped region 160 can be improved, but so way can make the junction leakage (junction leakage) between N type source/drain 150 and P type ring doped region 160 or the P type substrate 100 increase again, so neither good solution.
According to the above, the manufacture method that needs development new is arranged, improving the problem of short-channel effect, and then promote the operation usefulness of metal oxide semiconductor transistor.
Summary of the invention
Therefore purpose of the present invention is exactly that a kind of manufacture method of metal-oxide semiconductor transistor component is being provided, with the problem of improving short-channel effect so that the ring doped region more desirably surrounds source/drain.
According to above-mentioned purpose of the present invention, a kind of manufacture method of metal-oxide semiconductor transistor component is proposed.The step of the method is as described below.In a substrate, form a gate dielectric layer earlier.On this gate dielectric layer, form a conductor layer again.Then to this gate dielectric layer therewith conductor layer carry out a photoetching corrosion manufacturing process to form a grid.Then on the sidewall of this grid, form a lining.Again with this grid therewith lining be that mask carries out one first conductive type ion and injects, in this substrate in this grid outside, to form source.Next this lining of etching is so that the thickness of this lining reduces.Carry out one second conductive type ion at last and inject, to form a ring doped region around this source/drain in the one-sided or substrate on two sides outside this grid.
Because this lining of etching carried out before ring doped region ion injects manufacturing process, the boundary of ring doped region in substrate is by defined by etched this lining.Therefore the ring doped region near raceway groove can surround source/drain greatly ideally.So can make and time open that electric leakage that the beginning electric leakage reduces, caused because of the electrical breakdown effect also can reduce and cut-in voltage can be kept stable.In addition, the ring doped region can use lower doping content just can reach the cut-in voltage that prior art reaches, and the junction leakage between source/drain and ring doped region or the substrate is reduced.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate institute's accompanying drawing to elaborate.In the accompanying drawing:
Fig. 1 has source/drain and the transistorized section of structure of N type metal oxide semiconductor that encircles doped region.
Fig. 2 is for carrying out the section of structure after the lining etching to N type metal oxide semiconductor transistor arrangement among Fig. 1.
Fig. 3 is the transistorized section of structure of N type metal oxide semiconductor with source/drain according to the preferred embodiment of the present invention.
Fig. 4 A is for carrying out the section of structure after both sides lining etching is injected with the ring doped region to N type metal oxide semiconductor transistor arrangement among Fig. 3.
Fig. 4 B is for carrying out the section of structure after one-sided lining etching is injected with the ring doped region to N type metal oxide semiconductor transistor arrangement among Fig. 3.
The simple symbol explanation
100,300: substrate 110,310: grid
120,320: gate dielectric layer 130,330: conductor layer
132,332: polysilicon layer 134,334: metal silicide layer
136,336: cap layer 140,340: lining
150,350: source/drain 160,360: the ring doped region
162,362: near the ring doped region of raceway groove
Embodiment
The manufacture method of metal-oxide semiconductor transistor component of the present invention is applicable to the metal oxide semiconductor transistor of making in the various different products application.
Below narrate the first embodiment of the present invention.Fig. 3 is the transistorized section of structure of N type metal oxide semiconductor with source/drain according to the preferred embodiment of the present invention.Fig. 4 A is for carrying out the section of structure after both sides lining etching is injected with the ring doped region to N type metal oxide semiconductor transistor arrangement among the 3rd figure.In the following description, for purpose clearly, same numeral is used to element same or approximate in fact among sign picture 3, the 4A.Yet need be understood that through after the various different manufacturing technology steps, same or approximate element may be similar to no longer in fact or remain unchanged.
The manufacturing process mode that forms structure among Fig. 3 is as described below.Go up in a substrate 300 (for example being the P type semiconductor substrate) earlier and form a gate dielectric layer 320 with for example thermal oxidation method, the material of this gate dielectric layer 320 for example is a silica.Then on this gate dielectric layer 320, form a conductor layer 330, for example with chemical vapour deposition (CVD) (Chemical Vapor Deposition, mode CVD) deposits a polysilicon layer 332; Can select also again that the mode with for example chemical vapour deposition (CVD) deposits a metal silicide layer 334 on the surface of this polysilicon layer 332.In this embodiment, the material of this metal silicide layer 334 is a tungsten silicide.This polysilicon layer 332 metal silicide layer 334 therewith can be collectively referred to as conductor layer 330, and this conductor layer 330 is called multi-crystal silicification metal (polycide) layer again.When other is applied to the manufacturing process of different elements, also can select to form a cap layer 336 on conductor layer 330, this cap layer 336 for example is a silicon nitride or silicon oxynitride layer.Afterwards, gate dielectric layer 320 and conductor layer 330 (and cap layer 336) are carried out a photoetching corrosion manufacturing process to form a grid 310 stack architectures.
Form a lining 340 then in the sidewall of this grid 310.The mode that forms this lining 340 for example is with rapid thermal oxidation method (rapid thermal oxidation).The material of this lining 340 for example is a silica.
After forming this lining 340, then with this grid 310 therewith lining 340 be that mask carries out one first conductive type ion (for example being N type phosphorus or arsenic ion) and injects, with formation source 350 in this substrate 300 in these grid 310 outsides.
Please refer to Fig. 4 A, this lining 340 of etching next is so that the thickness of this lining 340 reduces.Then, this lining 340 that reduces with this grid 310 and thickness is that mask carries out one second conductive type ion (for example being P type boron ion) injection again, to form a ring doped region 360 in this substrate 300 of both sides outside this grid 310.So far formed the structure among Fig. 4 A.In this embodiment, this ring doped region 360 coats this source/drain 350 fully in this substrate 300.By the invention described above preferred embodiment as can be known, use the present invention and have following advantage.Shown in Fig. 4 A, because injecting manufacturing process in ring doped region 360 ions, this lining 340 of etching carries out before, so the boundary line of ring doped region 360 in substrate 300 is by defined by etched this lining 340.Therefore the ring doped region 362 near raceway groove can surround source/drain 350 greatly ideally.Because ring doped region 360 can surround source/drain 350 ideally, time open that electric leakage that the beginning electric leakage reduces, caused because of the electrical breakdown effect also can reduce and cut-in voltage can be kept stable so can make.In addition, ring doped region 360 can use lower doping content just can reach the cut-in voltage that prior art reaches, and the junction leakage between source/drain 350 and ring doped region 360 or the substrate 300 is reduced.
Finish after the above-mentioned manufacturing process, also be included in this grid 310 and form clearance wall (spacer) in lining 340 both sides therewith, carrying out another first conductive type ion injects, dielectric layer (for example being silica) and forms the manufacturing process such as contact hole that metal oxide semiconductor transistor therewith electrically connects on said structure.
Below narrate the second embodiment of the present invention.Fig. 4 B is for carrying out the section of structure after one-sided lining etching is injected with the ring doped region to N type metal oxide semiconductor transistor arrangement among Fig. 3.
Please refer to Fig. 4 B, after finishing the structure of Fig. 3, form a mask layer (not illustrating) and for example be the photoresist layer, cover a side of position grid 310.Next the lining 340 of these grid 310 opposite sides of etching is so that the thickness of the lining 340 of this side reduces.Then, this lining 340 that reduces with this grid 310 and thickness is that mask carries out one second conductive type ion (for example being P type boron ion) injection again, to form a ring doped region 360 in this one-sided outside this grid 310 substrate 300.So far formed the structure among Fig. 4 B.In this embodiment, this ring doped region 360 in this substrate 300, coat fully this source/drain 350 one of them.By the invention described above preferred embodiment as can be known, use the present invention and have following advantage.Shown in Fig. 4 B, because injecting manufacturing process in ring doped region 360 ions, this lining 340 of etching carries out before, so the boundary line of ring doped region 360 in substrate 300 is by defined by etched this lining 340.Therefore near the ring doped region 362 of raceway groove big and can surround ideally source/drain 350 one of them.So can make and time open that electric leakage that the beginning electric leakage reduces, caused because of the electrical breakdown effect also can reduce and cut-in voltage can be kept stable.In addition, ring doped region 360 can use lower doping content just can reach the cut-in voltage that prior art reaches, and also makes simultaneously source/drain 350 one of them and the junction leakage reduction that encircles between doped region 360 or the substrate 300.
Finish after the above-mentioned manufacturing process, also be included in this grid 310 and form clearance wall (spacer in lining 340 both sides therewith, do not illustrate), carrying out another first conductive type ion injects, dielectric layer (does not illustrate, silica for example) on said structure, and forms the manufacturing process such as contact hole that metal oxide semiconductor transistor therewith electrically connects.
The metal oxide semiconductor transistor of this second embodiment manufacturing can be applied to memory such as dynamic random access memory (Dynamic Random Access Memory especially, DRAM) memory cell in (memory cell) is with as access transistor (access transistor).The grid 310 of this access transistor is connected to word line (word line), and the source electrode 350 that tool ring doped region 360 surrounds is connected to bit line (bit line).350 of the drain electrodes of this access transistor are connected to an end of storage (storage) capacitor.
Owing to have above advantage, manufacture method of the present invention can be promoted the operation usefulness of metal oxide semiconductor transistor.
Need be understood that as long as use the substrate of N type, P type source/drain and N type ring doped region, the manufacture method of metal-oxide semiconductor transistor component of the present invention can be used for making the P-type mos transistor equally.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (17)
1. the manufacture method of a metal-oxide semiconductor transistor component, this method comprises at least:
Form a grid in a substrate, wherein this grid comprises a gate dielectric layer and a conductor layer;
On the sidewall of this grid, form a lining;
With this grid and this lining is that mask carries out the injection of one first conductive type ion, to form source/drain in this substrate in this grid outside;
This lining of etching is so that the thickness of this lining reduces; And
With this lining after this grid and the etching is mask, carries out one second conductive type ion and injects, to form a ring doped region around this source/drain.
2. manufacture method as claimed in claim 1, wherein this conductor layer is a polysilicon layer.
3. manufacture method as claimed in claim 2, wherein this conductor layer also comprises a metal silicide layer on this polysilicon layer.
4. manufacture method as claimed in claim 1, the method that wherein forms this lining on the sidewall of this grid comprises the rapid thermal oxidation method.
5. manufacture method as claimed in claim 1, wherein this first conductive type ion is a N type ion, and this second conductive type ion is a P type ion.
6. manufacture method as claimed in claim 1, wherein this first conductive type ion is a P type ion, and this second conductive type ion is a N type ion.
7. manufacture method as claimed in claim 1 wherein is formed with a cap layer on this grid.
8. the manufacture method of a metal-oxide semiconductor transistor component, this method comprises at least:
Form a grid in a substrate, wherein this grid comprises a gate dielectric layer and a conductor layer;
On the sidewall of this grid, form a lining;
With this grid and this lining is that mask carries out the injection of one first conductive type ion, to form source/drain in this substrate in this grid outside;
This lining of this grid one side of etching is so that the thickness of this side lining reduces; And
With this lining after this grid and the etching is mask, carry out one second conductive type ion and inject, with this source/drain of etched this side one of them around form a ring doped region.
9. manufacture method as claimed in claim 8, wherein this conductor layer is a polysilicon layer.
10. manufacture method as claimed in claim 9, wherein this conductor layer also comprises a metal silicide layer on this polysilicon layer.
11. manufacture method as claimed in claim 8, the method that wherein forms this lining comprises the rapid thermal oxidation method.
12. manufacture method as claimed in claim 8, wherein this first conductive type ion is a N type ion, and this second conductive type ion is a P type ion.
13. manufacture method as claimed in claim 8, wherein this first conductive type ion is a P type ion, and this second conductive type ion is a N type ion.
14. manufacture method as claimed in claim 8 wherein is formed with a cap layer on this grid.
15. manufacture method as claimed in claim 8, wherein this metal-oxide semiconductor transistor component is applied to the memory cell in the memory, and with as an access transistor, and this source/drain that contains this ring doped region is connected to a bit line.
16. manufacture method as claimed in claim 8 wherein before this lining of this grid one side of etching, also comprises forming the opposite side that a mask layer covers this grid.
17. manufacture method as claimed in claim 16, wherein this mask layer is a photoresist layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100315281A CN100385633C (en) | 2004-03-19 | 2004-03-19 | Method for fabricating MOSFET element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100315281A CN100385633C (en) | 2004-03-19 | 2004-03-19 | Method for fabricating MOSFET element |
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| Publication Number | Publication Date |
|---|---|
| CN1670928A CN1670928A (en) | 2005-09-21 |
| CN100385633C true CN100385633C (en) | 2008-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100315281A Expired - Fee Related CN100385633C (en) | 2004-03-19 | 2004-03-19 | Method for fabricating MOSFET element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1964164B1 (en) * | 2005-12-13 | 2012-02-15 | Nxp B.V. | Field effect transistor structure with an insulating layer at the junction |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5972762A (en) * | 1998-01-05 | 1999-10-26 | Texas Instruments--Acer Incorporated | Method of forming mosfets with recessed self-aligned silicide gradual S/D junction |
| CN1088914C (en) * | 1995-03-08 | 2002-08-07 | 现代电子产业株式会社 | Method for fabricating metal oxide semiconductor field effect transistor |
| US6472284B2 (en) * | 2000-08-31 | 2002-10-29 | Hynix Semiconductor, Inc. | Method for fabricating a MOSFET having a thick and thin pad oxide at the gate sides |
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2004
- 2004-03-19 CN CNB2004100315281A patent/CN100385633C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1088914C (en) * | 1995-03-08 | 2002-08-07 | 现代电子产业株式会社 | Method for fabricating metal oxide semiconductor field effect transistor |
| US5972762A (en) * | 1998-01-05 | 1999-10-26 | Texas Instruments--Acer Incorporated | Method of forming mosfets with recessed self-aligned silicide gradual S/D junction |
| US6472284B2 (en) * | 2000-08-31 | 2002-10-29 | Hynix Semiconductor, Inc. | Method for fabricating a MOSFET having a thick and thin pad oxide at the gate sides |
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| Publication number | Publication date |
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| CN1670928A (en) | 2005-09-21 |
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Granted publication date: 20080430 |