CN100379321C

CN100379321C - Array base plate and its manufacturing method

Info

Publication number: CN100379321C
Application number: CNB2005101341998A
Authority: CN
Inventors: 陈慧昌; 陈建良
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2005-12-27
Filing date: 2005-12-27
Publication date: 2008-04-02
Anticipated expiration: 2025-12-27
Also published as: CN1805655A

Abstract

The present invention relates to an array base plate and a manufacturing method thereof. The array base plate comprises a base plate, a first circuit, a second circuit, a patternized protective layer, a pad and a protective pad; the front circuit is arranged on the base plate; the second circuit which is generally parallel to the front circuit is arranged on the base plate; the patternized protective layer is arranged on the base board, covers the first circuit and the second circuit, and is provided with an opening which exposes a part of the first circuit; the pad is arranged in the opening and is in contact with the first circuit; the protective pad is arranged on the second circuit and is overlapped with the pad in the direction which is perpendicular to the second circuit in general.

Description

Array base palte and manufacture method thereof

Technical field

The present invention relates to a kind of array base palte and manufacture method thereof, particularly relate to a kind of array base palte that prevents that the circuit on it from being destroyed when chip (IC) pressing.

Background technology

As glass flip chip (chip on glass, when COG) the past more areolar (fine pitch) of technology develops, because accuracy of machines reaches in order to increase technology permission (process window), in the IC pressing, have very big probability and can be pressed onto adjacent lines, describe in detail below with reference to Fig. 1 a, 1b, 1c.

As shown in Figure 1a, on array basal plate 100, be typically provided with many circuits 110, and on each circuit 110, be equipped with a pad 120, when IC piece (bump) 200 and pad 120 contrapositions just often, shown in Fig. 1 b as; Yet, when contraposition is offset, will be shown in Fig. 1 c as, IC piece 200 is pressed onto adjacent lines 110 because circuit 110 top layers matcoveredn (passivation) only, IC piece 200 might be pressed and be worn protective layer and cause circuit 110 and pad 120 to produce the phenomenon of short circuits.

Summary of the invention

In view of this, the object of the present invention is to provide a kind of array base palte and manufacture method thereof, it can prevent that the circuit on it from being destroyed when chip pressing.

According to the present invention; a kind of array base palte is provided; comprise a substrate; one first circuit; one second circuit; one patterning protective layer; one first pad; and one first neonychium; wherein first circuit is arranged on the substrate; second circuit is to be arranged on the substrate with the parallel substantially mode of first circuit; the patterning protective layer is arranged on the substrate and covers first circuit and second circuit; and have one first opening and expose partly first circuit; first pad is arranged in first opening and with first circuit and contacts; first neonychium is arranged on second circuit, and with the vertical substantially direction of second circuit on overlapping with first pad.

In a preferred embodiment, first neonychium is made by indium tin oxide, and the length of comparable first pad of its length is long or equate with it, and the width of comparable second circuit of width is wide or equate with it.

In another preferred embodiment; the patterning protective layer also has one second opening and exposes partly second circuit; and above-mentioned array base palte also comprises one second pad and one second neonychium; wherein second pad is arranged in second opening and with second circuit and contacts; and second neonychium is arranged on first circuit, and with the vertical substantially direction of first circuit on overlapping with second pad.

Again, second neonychium is made by indium tin oxide, and the length of comparable second pad of its length is long or equate with it, and the width of comparable first circuit of width is wide or equate with it.

Again in the present invention, provide a kind of manufacture method of array base palte, comprise the following steps: at first, a substrate is provided; Then, form one first circuit parallel to each other substantially and one second circuit on substrate; Afterwards, form a patterning protective layer on substrate and cover first circuit and second circuit, wherein the patterning protective layer has one first opening and exposes partly first circuit; At last; form a patterned conductive layer; form one first neonychium in first opening, to form one first pad and the patterning protective layer on second circuit top, wherein be formed on second circuit first neonychium be formed at first circuit on first pad with the vertical substantially direction of second circuit on overlapping.

In a preferred embodiment, in forming a patterning protective layer on substrate and cover in the step of first circuit and second circuit, the patterning protective layer also has one second opening and exposes partly second circuit; Again; in the step that forms a patterned conductive layer; in second opening, form one second pad and the patterning protective layer on first circuit top and form one second neonychium, and be formed on first circuit second neonychium be formed at second circuit on second pad with the vertical substantially direction of first circuit on overlapping.

For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.

Description of drawings

Fig. 1 a is the schematic diagram of existing array base palte;

Fig. 1 b is pad and the IC piece contraposition schematic diagram just often among Fig. 1 a;

Schematic diagram when Fig. 1 c is pad among Fig. 1 a and IC piece contraposition skew;

Fig. 2 is the schematic diagram of first embodiment of array base palte of the present invention;

Fig. 3 a is the profile along the line a-a of Fig. 2;

Fig. 3 b is the profile along the line b-b of Fig. 2;

Fig. 3 c is the profile along the line c-c of Fig. 2;

Fig. 3 d is the profile along the line d-d of Fig. 2;

Fig. 3 e is the profile along the line e-e of Fig. 2;

Fig. 4 a, 4b are the schematic diagram of the process of the array base palte in the shop drawings 2;

Schematic diagram when Fig. 5 is pad among Fig. 2 and IC piece contraposition skew;

Fig. 6 a is the schematic diagram of second embodiment of array base palte of the present invention;

Schematic diagram when Fig. 6 b is pad among Fig. 6 a and IC piece contraposition skew; And

Fig. 7 is the schematic diagram of the 3rd embodiment of array base palte of the present invention.

The simple symbol explanation

10,10 ', 10 ", 100～array base palte; 11～substrate;

12～the first circuits; 13～the second circuits;

110～circuit; 14～the first pads;

15～the first neonychiums; 15a, 15b, 19a, 19b, 19 '～neonychium;

16～the second pads; 17～the second neonychiums;

18～patterning protective layer; 18a～first opening;

18b～second opening; 120～pad;

200～IC piece.

Embodiment

First embodiment

With reference to figure 2,3a, 3b, 3c; first embodiment of array base palte 10 of the present invention comprises a substrate 11, many circuits (comprising one first circuit 12 and one second circuit 13), a patterning protective layer 18, a plurality of pad (comprising one first pad 14 and one second pad 16) and a plurality of neonychium (comprising one first neonychium 15 and one second neonychium 17), and wherein each

circuit

12,13 is arranged on the substrate 11 in the mode that is parallel to each other substantially.

As shown in Fig. 3 b, 3d, patterning protective layer 18 is arranged on the substrate 11, and cover first circuit 12 and second circuit 13, and have one first opening 18a and one second opening 18b (with reference to figure 4b), to expose partly first circuit 12 and part second circuit 13 respectively; Each pad is arranged in the opening of patterning protective layer 18 and with circuit and contacts; for example, in Fig. 3 b, first pad 14 is arranged in the first opening 18a and with first circuit 12 and contacts; and in Fig. 3 d, second pad 16 is arranged in the second opening 18b and with second circuit 13 and contacts.

In present embodiment, each neonychium is set on each circuit, for example via the patterned conductive layer identical with forming first pad 14 and second pad 16, in Fig. 3 c, first neonychium 15 is arranged on second circuit 13, and in Fig. 3 e, second neonychium 17 is arranged on first circuit 12; Again; it should be noted each neonychium with the vertical substantially direction of circuit on adjacent lines on pad overlapping; for example; with reference to figure 2; first neonychium 15 with the vertical substantially direction of second circuit 13 on first circuit 12 on first pad 14 overlapping, and second neonychium 17 with the vertical substantially direction of first circuit 12 on second circuit 13 on second pad 16 overlapping.

Each neonychium is identical with gasket material, makes by indium tin oxide; Again, though will be appreciated that in graphic, the length of each neonychium is longer than the pad length on the adjacent lines, is not limited to this, also can equate with it or less; Similarly, though in graphic, though the width of each neonychium equates that with the width of circuit be not limited to this, also comparable circuit is wide or narrow.

The formation of present embodiment below illustrates the manufacture method of the array base palte of present embodiment as mentioned above.

The manufacture method of the array base palte of present embodiment comprises the following steps: at first, and a substrate 11 is provided; Then,

form circuit

12,13 parallel to each other substantially on substrate 11, shown in Fig. 4 a; Afterwards, formation patterning protective layer 18 is on substrate 11 and

cover circuit

12,13, and wherein patterning protective layer 18 has opening 18a, 18b, to expose partly

circuit

12,13, shown in Fig. 4 b; At last, form a patterned conductive layer, and in opening 18a, 18b,

form pad

14,16, shown in Fig. 3 b, 3d, and the top of the patterning protective layer on

circuit

12,13

formation neonychium

15,17, shown in Fig. 3 c, 3e.

As above-mentioned, owing on the position corresponding to pad neonychium is being set on the adjacent lines, and the material of this neonychium is the same with pad, made by indium tin oxide, the situation of IC piece 200 contrapositions skew even take place in its hard and scratch resistance, as shown in Figure 5, also be unlikely to cause for circuit to weigh and cause short circuit wounded, can increase the technology permission, making more, the IC product of areolar (fine pitch) is entered the volume production stage; Because neonychium and pad are made by same patterned conductive layer, can't increase any cost again.

Second embodiment

Fig. 6 a is the schematic diagram of second embodiment of array base palte 10 ' of the present invention, the difference of the array base palte 10 of the array base palte 10 ' of present embodiment and first embodiment is: in first embodiment, pad on each circuit is that one group mode is provided with per two circuits, and in the present embodiment, the pad on each circuit is that one group mode is provided with every three-line then.

Know clearly it; in first embodiment; the pad that only need set up on each circuit on the adjacent lines of the corresponding side of a neonychium gets final product; and in the present embodiment, then need the pad (for example, the 15a among Fig. 6 a and 15b, 19a and 19b) on the adjacent lines of setting up the corresponding both sides of two neonychiums on each circuit; by this; even the situation of IC piece 200 contrapositions skew takes place, shown in Fig. 6 b, also be unlikely to circuit caused to weigh wounded.

Again, though will be appreciated that in first and second embodiment, be that one group mode describes with per two and every three-line respectively, be not limited to this, also can per circuit more than three be that one group mode is provided with pad.

The 3rd embodiment

Fig. 7 is an array base palte 10 of the present invention " the schematic diagram of the 3rd embodiment; the array base palte 10 of present embodiment " be with the difference of the array base palte 10 ' of second embodiment: for two neonychium 19a, the 19b that separates is connected to single neonychium 19 ' in the present embodiment, technology is more simplified in a second embodiment.

Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.

Claims

1. array base palte comprises:

Substrate;

First circuit is arranged on this substrate;

Second circuit is arranged on this substrate in the mode parallel with this first circuit;

The patterning protective layer is arranged on this substrate and covers this first circuit and this second circuit, and has first opening and expose partly this first circuit;

First pad is arranged in this first opening and contacts with this first circuit;

First neonychium is arranged on this second circuit, and overlapping with this first pad on the direction vertical with this second circuit.

2. array base palte as claimed in claim 1, wherein this first neonychium is made by indium tin oxide.

3. array base palte as claimed in claim 1, wherein the length of this first neonychium is longer than the length of this first pad.

4. array base palte as claimed in claim 1, wherein the width of this first neonychium is wideer than the width of this second circuit.

5. array base palte as claimed in claim 1, wherein this patterning protective layer also has second opening and exposes partly this second circuit, and above-mentioned array base palte also comprises:

Second pad is arranged in this second opening and contacts with this second circuit; And

Second neonychium is arranged on this first circuit, and overlapping with this second pad on the direction vertical with this first circuit.

6. array base palte as claimed in claim 5, wherein this second neonychium is made by indium tin oxide.

7. array base palte as claimed in claim 5, wherein the length of this second neonychium is longer than the length of this second pad.

8. array base palte as claimed in claim 5, wherein the width of this second neonychium is wideer than the width of this first circuit.

9. the manufacture method of an array base palte comprises:

Substrate is provided;

Form first circuit parallel to each other and second circuit on this substrate;

Form the patterning protective layer on this substrate and cover this first circuit and this second circuit, wherein this patterning protective layer has first opening and exposes partly this first circuit; And

Form patterned conductive layer, in this first opening, to form first pad and the top of the patterning protective layer on this second circuit formation first neonychium;

This first neonychium that wherein is formed on this second circuit is overlapping on the direction vertical with this second circuit with this first pad on being formed at this first circuit.

10. the manufacture method of array base palte as claimed in claim 9, wherein this first neonychium is formed in the length mode longer than this first pad.

11. the manufacture method of array base palte as claimed in claim 9, wherein this first neonychium is formed in the width mode wideer than this second circuit.

12. the manufacture method of array base palte as claimed in claim 9; wherein in forming the patterning protective layer on this substrate and cover in the step of this first circuit and this second circuit; this patterning protective layer also has second opening and exposes partly this second circuit; and in the step that forms patterned conductive layer; in this second opening, form second pad and the top of the patterning protective layer on this first circuit formation second neonychium, and this second neonychium that is formed on this first circuit is overlapping on the direction vertical with this first circuit with this second pad on being formed at this second circuit.