CN100378736C - Sequential depth computing method of synchronous sequential circuit - Google Patents

Sequential depth computing method of synchronous sequential circuit Download PDF

Info

Publication number
CN100378736C
CN100378736C CNB200510027607XA CN200510027607A CN100378736C CN 100378736 C CN100378736 C CN 100378736C CN B200510027607X A CNB200510027607X A CN B200510027607XA CN 200510027607 A CN200510027607 A CN 200510027607A CN 100378736 C CN100378736 C CN 100378736C
Authority
CN
China
Prior art keywords
state
succeeding
overbar
formula
algorithm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB200510027607XA
Other languages
Chinese (zh)
Other versions
CN1710568A (en
Inventor
张忠林
唐璞山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to CNB200510027607XA priority Critical patent/CN100378736C/en
Publication of CN1710568A publication Critical patent/CN1710568A/en
Application granted granted Critical
Publication of CN100378736C publication Critical patent/CN100378736C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

The present invention belongs to the technical field of a very large-scale integrated circuit, particularly, a method for calculating the time sequence depth of a synchronous time sequence circuit. The method is based on a satiable algorithm engine. A data structure adopts an explicit memory mode of a reachable state so as to reduce the burden of the satiable algorithm. The method for calculating the time sequence depth of a synchronous time sequence circuit comprises the following procedures: initializing a state, calculating subsequent states, traversing previous states, storing a novel state, rejecting a redundant state, resetting the algorithm engine, etc. The operating efficiency of the method of the present invention is greatly enhanced.

Description

Sequential depth computing method of synchronous sequential circuit
Technical field
The invention belongs to the very large scale integration technology field, be specifically related to calculate synchronizing sequential circuit sequential degree of depth way to solve the problem for the completeness that guarantees checking in a kind of modelling verification of VLSI (very large scale integrated circuit).
Background technology
At present, the electronic hardware system has been widely used in various key areas, e-commerce field for example, telephone-switching network, control system of highway and air traffic or the like.In these fields, system's loss that is brought that makes a mistake is normally unacceptable, but still some incidents of makeing mistakes and causing system to make a mistake owing to hardware system often takes place.Therefore hardware system is vital reliably.Although have 70-80% people to be engaged in checking work in current hardware design group, vicious chip still can be produced, and just can be found after the user runs into, thereby causes great commerce loss.
In the checking field of VLSI (very large scale integrated circuit), the verification method of normal use is based on the method for signal imitation.But owing to improving constantly of design complexities, this authentication policy becomes and more and more lacks efficient.For example, according to Intel Company, in the proof procedure of Pentium four microprocessors, common mode has intended surpassing 2,000 hundred million clock period, if still operate in the following time of dominant frequency of 1GHz when microprocessor, this is equivalent to microprocessor and has moved two minutes.In addition, authentication policy based on simulation can not guarantee the completeness verified: under best state, the possibility that also design can only be made mistakes based on the verification method of simulation is reduced to an acceptable level, and can not guarantee the hundred-percent correctness of design function.
Method as an alternative, formal verification method are suggested and obtain in many engineering projects to use.For can be in the mistake in the design early detection design, the method for model checking be used widely.Method based on the bounded model checking still can obtain extraordinary result when design reaches 100,000 orders of magnitude.
But there is the problem that algorithm itself is intrinsic in bounded model checking method, promptly in given boundary, can not provide the proof of completeness.In order to address this problem, the algorithm that is used for the counting circuit sequential degree of depth is suggested.After obtaining the sequential degree of depth of circuit, just can provide the depth capacity of the required calculating of bounded model checking, explain thereby provide completeness.
At present, sequential degree of depth algorithm mainly is based on the satisfiability engine.In other algorithms, at first the computational problem with the sequential degree of depth is converted into a quantitative Boolean Equation QBF (Quantified Boolean Formula).But the calculating of QBF has two main obstacles.At first, measure word and inversion operation can not simply be used for the satisfiability algorithm engine.Secondly, the inquiry computing in path has traversing operation, and is too time-consuming.Therefore people have carried out abbreviation to QBF, and step QBF computing is become two step satisfiability computings [1].Though step has increased, because computing becomes simpler, from experimental result, speed still is acceptable.But this algorithm also has a very big shortcoming, and when the sequential degree of depth was very dark, the computing scale tended to surpass the processing power of satisfiability algorithm engine.Therefore on the actual treatment ability, the algorithm application scope that simple use can be satisfied engine is very restricted.
Summary of the invention
The objective of the invention is to propose a kind of method of the fireballing calculating synchronizing sequential circuit sequential degree of depth based on the satisfiability algorithm engine.
The computing method of the sequential degree of depth of the sequential circuit that the present invention proposes, based on the satisfiability algorithm engine, data structure adopts state explicit storage mode, reduces the burden of satisfiability algorithm engine.Because the explicit storage of state space has reduced the computing scale of satisfiability engine in the algorithm.Though the call number of satisfiability algorithm engine has increased and since at every turn when calling the scale of problem all little, so speed is still faster than the algorithm of independent use satisfiability engine.
According to the present invention, the method that solves the sequential depth calculation of Sequential Circuit Design comprises the steps: the initialization of state, the calculating of succeeding state, the traversal of historic state, storage, the rejecting of redundant state and the resetting of algorithm engine of new state.Particular content is as follows:
1, the initialization of state: read the practical design circuit, therefrom extract finite state machine model, this model comprises state exchange equation and system initial state set at least, finishes initialization task then, as the initialization of built-in variable;
2, the calculating of succeeding state: set up the CNF formula of an expression system state transfer equation, calculate the succeeding state of a certain current state with this CNF formula;
3, the rejecting of the traversal of historic state and redundant state: traversal historic state space, determine whether succeeding state is emerging state, if then in historic state, store this state; If not, then this state is added the CNF formula that is used for the calculated for subsequent state, be used to reject redundant state;
4, the storage of new state: whether record has new state to occur, if having, empties the set of current state and the new state that occurs is become the current state of next degree of depth; If there is not new state to occur, then current circuit depth is exactly the sequential degree of depth of this finite state machine, returns this value;
5, resetting of algorithm engine: the satisfiability engine is resetted, comprising with state variable and input variable set; Continue repeating step 3,4, until there not being new state to occur.
Above-mentioned implementation step is specifically seen shown in Figure 1.
Further introduce two algorithm points in this method below, i.e. the implementation method that succeeding state calculates and historic state travels through.
Succeeding state calculates:
At first obtain the state transition function of each state variable.And then, state transition function is become the CNF formula according to the transformational relation of listed elementary gate logic in designing to common factor general equation formula (CNF) expression formula.In algorithm of the present invention, among the assignment adding CNF with current state, call the satisfiability algorithm engine then.Each CNF formula is resulting to satisfy the assignment that assigned result all provides one group of succeeding state.The clause that this succeeding state assignment is become a CNF formula is added in the original CNF formula, to avoid repetition.Judge then whether this succeeding state is new state, if new state then joins this state in the historic state set, otherwise then do not do any operation.When no longer including new state and occur, the finishing iteration arithmetic operation.In side circuit, state transition function generally can be not complicated especially, so the engine of satisfiability algorithm generally can reach very high speed.
Because this algorithm need not significantly be revised the CNF formula in the computing of calculated for subsequent state each time, the time of therefore seeking new state probably remains on the magnitude of a constant.Even very big of the sequential degree of depth like this, the scale of CNF formula can not surpass the computing power of all satisfiability algorithm engine at present.
The storage of historic state:
For the historic state of system of storage efficiently, the data structure of storage of the present invention adopts the binary search tree form.Owing to be difficult to predict the important informations such as quantity of historic state in advance, therefore the binary tree of adopting storage of linked list to represent.And because the coding of each state is all different, and we only need locating function fast, so the initial data structure that realizes of the present invention is binary search tree (Binary Search Tree), and it is defined as follows:
Binary search tree or an empty tree, or binary tree with following character:
1. each node all has a key (key) as the search foundation, and the key of all nodes is different;
Left subtree (if exist) go up all nodes key all less than the key of root node;
Right subtree (if exist) go up all nodes key all greater than the key of root node;
4. left subtree and right subtree also are binary search trees.
In order to improve the efficient of binary search tree, reduce the average search length of tree.We have adopted the algorithm of height balance binary search tree in improved enforcement.This algorithm is adjusted the structure of tree when inserting a new node, make binary search tree keep balance, thereby reduces the height of tree as far as possible, reduces the average search length of tree.Height balance binary search tree is defined as follows:
A height balance binary search tree or an empty tree, or the binary search tree with following character: its left subtree and right subtree all are height balance binary search trees, and the absolute value of the difference of the height of left subtree and right subtree is no more than 1.
If being located at the height of the preceding height of new node insertion balance binary search tree is h, the node number is n, and the time of then inserting a new node is O (h).This is identical with general binary search tree.Under worst case, inserting a required time of new node in general binary search tree is O (n).And for height balance binary search tree, the worst search highly is
Figure C20051002760700061
Can satisfy the requirement of the inventive method fully.
Checking for sequential circuit has provided many examples for test in the world.The standard of estimating is the working time of seeing under the different test cases, for guaranteeing fairness, generally selects identical platform.
The method that can be satisfied problem by the solution of the present invention's proposition is designated as FDSDC (being compiled into the respective algorithms program), with the method comparison SDC03 (2003) of foreign latest.C Plus Plus is adopted in the realization of algorithm, and utilizes Zchaff to come the succeeding state of counting circuit as SAT-Solver.Program is to move on the P4PC of 2GHz in dominant frequency, and physical memory 1GBytes, test case are 10 examples of ISCAS ' 89.This test environment is identical with SDC03, and concrete operation result sees the following form.
The circuit name The sequential degree of depth FDSDC(s) SDC03(s)
s298 18 0.047 19.3
s386 7 0.015 0.18
s499 21 0 1.07
s510 46 0.015 144.81
s641 6 2.578 97.03
s713 6 4.094 126.94
s820 10 0.063 2.51
s953 10 0.891 102.23
s1196 2 9.937 232.84
s1488 21 0.125 96.87
To sum up, algorithm model of the present invention uses the core of ripe satisfiability engine as computing, aids in the storage of historic state, has reduced the pressure that can satisfy algorithm engine.Because the explicit storage of state space has reduced the computing scale of satisfiability engine in the algorithm.Though the call number of satisfiability algorithm engine has increased and since at every turn when calling the scale of problem all little, therefore the operational efficiency of algorithm is improved greatly.
Description of drawings
Fig. 1 is the FB(flow block) of the inventive method.
Fig. 2 is a synchronizing sequential circuit.
Fig. 3 is the idiographic flow of state computation.
Embodiment
Fig. 1 provides a little example and illustrates how to change state transition function into Boolean equation.
Described according to last joint, at first obtain the state transition function of each state variable, promptly
Figure C20051002760700071
Figure C20051002760700072
According to the transformational relation of listed elementary gate logic, state transition function is launched into following CNF formula then to the CNF expression formula:
T ( y + , y , x ) = ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 ) ( y 2 + + x ‾ 2 )
( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) · · · · · · ( 1 )
After obtaining the CNF formula of system state transfer function, just can be very easily calculate all succeeding states in given current state by calling the satisfiability algorithm engine.
In the algorithm that the present invention mentioned, at first the assignment with current state adds among the CNF, calls the satisfiability algorithm engine then.Each CNF formula is resulting to satisfy the assignment that assigned result all provides one group of succeeding state.At first the clause that this succeeding state assignment is become a CNF formula is added in the original CNF formula to avoid repetition.Judge then whether this succeeding state is new state, if new state then joins this state in the historic state set, otherwise then do not do any operation.When no longer including new state and occur, the finishing iteration arithmetic operation.In side circuit, state transition function generally can be not complicated especially, so the engine of satisfiability algorithm generally can reach very high speed.
For clearer explanation the inventive method, be that example provides the state computation idiographic flow with Fig. 2 circuit below, see shown in Figure 3.
At first the original state of circuit, be made as y1=0, y2=0 is changed to 0 with circuit depth then.With the clause
Figure C20051002760700075
With
Figure C20051002760700076
Be added in the formula (1), obtain following formula:
T ( y + , y , x ) = y ‾ 1 y ‾ 2 ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 )
( y 2 + + x ‾ 2 ) ( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) · · · · · · ( 2 )
Call the succeeding state under the satisfiability algorithm engine calculating original state, obtain new succeeding state y 1 + = 0 , y 2 + = 1 . For fear of state y 1 + = 0 , y 2 + = 1 Repeat, we are with the clause
Figure C200510027607000713
In the adding formula (1).This moment, state transition function became following formula:
T ( y + , y , x ) = y ‾ 1 y ‾ 2 ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 )
( y 2 + + x ‾ 2 ) ( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) ( y 1 + + y ‾ 2 + ) · · · · · · ( 3 )
Continue to call the satisfiability algorithm engine, obtain this formula for can not satisfy formula, original state y1=0 is described, y2=0 does not have follow-up state again, finishes the calculating of the succeeding state of this state.Owing to there is new state to occur, therefore need descend the computing of one deck, circuit depth is increased 1, replacement satisfiability algorithm engine.Current state is changed to new state y1=0, and y2=1 is with the clause
Figure C200510027607000716
And y 2Be added in the formula (3), obtain following formula:
T ( y + , y , x ) = y ‾ 1 y 2 ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 )
( y 2 + + x ‾ 2 ) ( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) ( y 1 + + y ‾ 2 + ) · · · · · · ( 4 )
Call satisfiability algorithm engine calculated for subsequent state and can get new state y 1 + = 1 , y 2 + = 0 . In like manner for fear of the repeating of state, we are with the clause In the adding formula (4).This moment, state transition function became following formula:
T ( y + , y , x ) = y ‾ 1 y 2 ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 )
( y 2 + + x ‾ 2 ) ( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) ( y 1 + + y ‾ 2 + )
( y ‾ 1 + + y 2 + ) · · · · · · ( 5 )
Continue to call satisfiability algorithm engine calculated for subsequent state and can get new state again y 1 + = 1 , y 2 + = 1 . In like manner repeat us with the clause for fear of state
Figure C200510027607000810
In the adding formula (5).This moment, state transition function became following formula:
T ( y + , y , x ) = y ‾ 1 y 2 ( y ‾ 1 + + y 2 ) ( y ‾ 1 + + x 1 ) ( y 1 + + x ‾ 1 + y ‾ 2 )
( y 2 + + x ‾ 2 ) ( y 2 + + y ‾ 1 ) ( y ‾ 2 + + x 2 + y 1 ) ( y 1 + + y ‾ 2 + )
( y ‾ 1 + + y 2 + ) ( y ‾ 1 + + y ‾ 2 + ) · · · · · · ( 6 )
Continue to call the satisfiability algorithm engine, obtain this formula for can not satisfy formula, original state y1=0 is described, y2=1 does not have follow-up state again, finishes the calculating of the succeeding state of this state.Owing to there is new state to occur again, therefore proceed down the computing of one deck, circuit depth is increased 1, replacement satisfiability algorithm engine.Current state is changed to y1=1 successively, y2=0 and y1=1, y2=1 continues to carry out respectively as stated above the calculating of succeeding state, owing to do not have the appearance of new state, so the computing termination, the sequential degree of depth of this circuit should be 2.
Because algorithm of the present invention need not significantly be revised the CNF formula in the computing of calculated for subsequent state each time, the time of therefore seeking new state probably remains on the magnitude of a constant.And the algorithm of SDC03 (2003) has used delta algorithm, and in order to calculate the sequential degree of depth, this article is pressed time frame to circuit and launched, and when causing the calculating for each succeeding state, all can increase the scale of CNF with the speed of linear growth.If the sequential degree of depth is dark excessively, the scale of CNF formula will soon surpass the computing power of all satisfiability algorithm engine at present.

Claims (4)

1. a sequential depth computing method of synchronous sequential circuit is characterized in that based on the satisfiability algorithm engine, and data structure adopts the explicit storage mode of accessible state, reduces the burden of satisfiability algorithm engine, and concrete steps are as follows:
(1) initialization of state: read the practical design circuit, therefrom extract finite state machine model, this model comprises state exchange equation and system initial state set at least, finishes initialization task then;
(2) calculating of succeeding state: set up the CNF formula of an expression system state transfer equation, calculate the succeeding state of a certain current state with this CNF formula; Here the CNF formula is the general equation formula of elementary gate logic to common factor:
(3) rejecting of the traversal of historic state and redundant state: traversal historic state space, determine whether succeeding state is emerging state, if then in historic state, store this state; If not, then this state is added the CNF formula that is used for the calculated for subsequent state, be used to reject redundant state;
(4) storage of new state: whether record has new state to occur, if having, empties the set of current state and the new state that occurs is become the current state of next degree of depth; If there is not new state to occur, then current circuit depth is exactly the sequential degree of depth of this finite state machine, returns this value;
(5) resetting of algorithm engine: the satisfiability engine is resetted, and comprising with state variable and input variable set, promptly level puts 1; Continue repeating step 3,4, until there not being new state to occur.
2. method according to claim 1, it is characterized in that the described succeeding state that calculates a certain current state with the CNF formula, the steps include: the assignment of current state variable is joined among the CNF, call the satisfiability algorithm engine then, each CNF formula is resulting to satisfy the assignment that assigned result all provides one group of succeeding state; The clause that this succeeding state assignment is become a CNF formula is added in the original CNF formula, to avoid repetition; Judge then whether this succeeding state is new state, if new state then joins this state in the historic state set, otherwise then do not do any operation.
3. method according to claim 1 is characterized in that the storage of described historic state, and its data structure adopts the binary search tree form:
(1) each node all has a key as the search foundation, and the key of all nodes is different;
(2) on the left subtree key of all nodes all less than the key of root node;
(3) on the right subtree key of all nodes all greater than the key of root node;
(4) left subtree and right subtree also are binary search trees.
4. method according to claim 3, it is characterized in that height balance binary search tree algorithm is adopted in the inquiry of historic state, this height balance binary search tree or an empty tree, or the binary search tree with following character: its left subtree and right subtree all are height balance binary search trees, and the absolute value of the difference of the height of left subtree and right subtree is no more than 1.
CNB200510027607XA 2005-07-07 2005-07-07 Sequential depth computing method of synchronous sequential circuit Expired - Fee Related CN100378736C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB200510027607XA CN100378736C (en) 2005-07-07 2005-07-07 Sequential depth computing method of synchronous sequential circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB200510027607XA CN100378736C (en) 2005-07-07 2005-07-07 Sequential depth computing method of synchronous sequential circuit

Publications (2)

Publication Number Publication Date
CN1710568A CN1710568A (en) 2005-12-21
CN100378736C true CN100378736C (en) 2008-04-02

Family

ID=35706810

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200510027607XA Expired - Fee Related CN100378736C (en) 2005-07-07 2005-07-07 Sequential depth computing method of synchronous sequential circuit

Country Status (1)

Country Link
CN (1) CN100378736C (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11225136A (en) * 1998-02-06 1999-08-17 Matsushita Electric Ind Co Ltd Clock recovery system
JP2000040363A (en) * 1998-05-21 2000-02-08 Nec Corp Semiconductor memory
CN1525550A (en) * 2003-09-18 2004-09-01 复旦大学 Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification
CN1604093A (en) * 2004-11-04 2005-04-06 复旦大学 Scanning chain construction method based on overall situation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11225136A (en) * 1998-02-06 1999-08-17 Matsushita Electric Ind Co Ltd Clock recovery system
JP2000040363A (en) * 1998-05-21 2000-02-08 Nec Corp Semiconductor memory
CN1525550A (en) * 2003-09-18 2004-09-01 复旦大学 Method for resolving satisfiability problem of very large scale integrated circuit (VLSIC) verification
CN1604093A (en) * 2004-11-04 2005-04-06 复旦大学 Scanning chain construction method based on overall situation

Also Published As

Publication number Publication date
CN1710568A (en) 2005-12-21

Similar Documents

Publication Publication Date Title
Chavira et al. Compiling Bayesian Networks Using Variable Elimination.
Manthey et al. Automated reencoding of boolean formulas
Murakami et al. Efficient algorithms for dualizing large-scale hypergraphs
Kwiatkowska et al. Probabilistic symbolic model checking with PRISM: A hybrid approach
Yeh et al. OBDD-based evaluation of k-terminal network reliability
Björklund et al. A discrete subexponential algorithm for parity games
Maire et al. Transient analysis of acyclic Markov chains
Khomenko et al. Towards an efficient algorithm for unfolding Petri nets
CN109408521A (en) A kind of method and device thereof for more new block chain global data state
van Hee et al. Resource-constrained workflow nets
Vasicek Relaxed equivalence checking: a new challenge in logic synthesis
CN105069290A (en) Parallelization critical node discovery method for postal delivery data
US7047510B1 (en) Method and system for partitioning an integrated circuit design
CN109102303A (en) Risk checking method and relevant apparatus
CN100378736C (en) Sequential depth computing method of synchronous sequential circuit
Piazza et al. Ackermann encoding, bisimulations and OBDDs
Liu et al. Binary decision diagram with minimum expected path length
Drechsler Verification of multi-valued logic networks
Baier et al. Norm functions for probabilistic bisimulations with delays
Minato VSOP (valued-sum-of-products) calculator for knowledge processing based on zero-suppressed BDDs
Kozura et al. Verification of distributed systems modelled by high-level Petri nets
CN112800242A (en) Pedigree mining method and device, electronic equipment and computer-readable storage medium
Lampka A symbolic approach to the state graph based analysis of high-level Markov reward models
Dsouza et al. Generating BDD models for process algebra terms
Shen et al. Synthesizing complementary circuits automatically

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080402

Termination date: 20120707