CN100373585C - Hardening method for improving MOS device field total dose - Google Patents
Hardening method for improving MOS device field total dose Download PDFInfo
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- CN100373585C CN100373585C CNB2006100248464A CN200610024846A CN100373585C CN 100373585 C CN100373585 C CN 100373585C CN B2006100248464 A CNB2006100248464 A CN B2006100248464A CN 200610024846 A CN200610024846 A CN 200610024846A CN 100373585 C CN100373585 C CN 100373585C
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Abstract
The present invention relates to a reinforcing method of increasing dosages for resisting the total radiation of an MOS transistor field region, which belongs to the technical field of processing semiconductor integrated circuits in microelectronics and solid electronics. The present invention is characterized in that after the technological processes of silicon island etching, field injection, degumming and cleaning and field oxidation for preparing a metal oxide semiconductor device and before pre-grid oxidation, one or the mixture of nitrogen, fluorine, silicon, and germanium ions is injected in the oxide layer of a field region at a room temperature and is annealed for 30 to 60 min at the temperature of 800 to 1000 DEG C in the protection of an inert atmosphere; subsequent technologies are normally performed. Injected energy and dosages are determined by the thickness of the oxide layer in field region. The present invention introduces a deep electron trap in the oxide layer to avoid edge current leakage and reduce the influence of positive charges generated by radiation on the device so as to improve the level of the device for resisting the total radiation of the dosages. Moreover, the present invention does not use a special method for preparing oxidation buried layers and is suitable for commercial production.
Description
Technical field
The present invention relates to the reinforcement means of the place anti-integral dose radiation of a kind of raising metal-oxide semiconductor (MOS) (MOS) device, or rather, be to adopt method that ion injects that dopant ion is incorporated into the place oxide layer of device, to improve anti-integral dose radiation performance based on device and circuit.The research fields such as manufacturing that belong to Microelectronics and Solid State Electronics, silicon integrated-optic device material.
Background technology
At complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) in the manufacturing technology, generally obtaining oxide layer by local oxidation silicon (LOCOS) or shallow trench isolation (STI) technology isolates to realize the electricity between device, and be exactly oxide layer to the most responsive zone of integral dose radiation in the MOS device, the effect that integral dose radiation causes in the MOS device mainly is to produce electric charge and at Si/SiO in oxide
2The interface produces interface state.Ionising radiation in inner electronics one hole that produces of semiconductor to can be very fast compound, but at the SiO of MOS device
2Middle electronics-the hole that produces is right, and just part is compound, as can be seen from Figure 1, and outside under the effect of electric field, because electron mobility (2 * 10
-3m
2/ Vs (T=300K)) bigger, can be very fast leave insulating barrier, staying the hole will be under electric field action, with slower migration velocity (2 * 10
-9m
2/ Vs (T=300K)), at SiO
2Middle migration.At last, arrive Si/SiO when the hole
2Near interface is near SiO
2Side is captured by trap and is become positive space charge, and simultaneously at Si/SiO
2The radiation interfacial state of inducting is introduced at the interface.Therefore, the device that adopts field oxide to isolate, when standing ionising radiation, the positive charge that field oxide is captured is far longer than the positive charge that grid oxide layer is captured.For body silicon N pipe, therefore the threshold voltage of the P type substrate below the field oxide can reduce greatly, even can drop to about 0V, and this moment, an insulating oxide did not just have the effect of isolation, and leakage current increases thereupon, as shown in Figure 2.For SOI MOS device, as shown in Figure 3, the edge, silicon island just is equivalent to and is parallel to the parallel parasitic transistor of SOI MOS device, the oxide layer at edge, silicon island is more responsive to radiation, the also very possible conducting (ovfl electric current) when main transistor is OFF state of these parasitic transistors this moment causes the beyond thought increase of device creepage.But these leakage currents can just one " step " can occur, as the electric current of Sidewall current indication among Fig. 4 by gate voltage control on transfer characteristic (I-V) curve.For cmos device, these are the problems that presses for solution by the leakage current that isolating oxide layer causes.
Reinforcing for field oxygen, people design a lot of ways, mainly contain two kinds of methods at present, the one, adopt the non-flanged device to avoid the place, as encircle grid, it is bigger that but this non-flanged device takies chip area, do not fit into the requirement that the development of present very lagre scale integrated circuit (VLSIC) reduces device size.Another kind itself is started with from place technology exactly, the transoid that suppresses P type place, eliminate edge, place ionising radiation parasitic leakage, adopt the P type to inject on the one hand, improve P type silicon surface dopant concentration under the field oxide, can increase the ability of the anti-ionizing radiation of circuit, but directly influence the puncture voltage of nmos device owing to P type doping content under the field oxide, doping content is high more, the puncture voltage of device is low more, because guarantee the work of circuit normal reliable ground, the raising of P type doping content is restricted, simultaneously since p type impurity at Si/SiO
2The effect of segregation at interface, p type impurity is difficult to increase substantially thick oxygen lower surface concentration, adopts the capability of resistance to radiation of this method raising circuit not obvious; Change the preparation technology of an oxygen on the other hand, as the process conditions of attenuate oxidated layer thickness, change heat growth field oxide, but this still can not satisfy the requirement of the anti-irradiation of circuit.
Summary of the invention
The object of the present invention is to provide the reinforcement means of a kind of MOS of raising device place radiation resistance, described reinforcement means can avoid the ovfl electric current that ionising radiation causes in the isolation camp oxide layer in the MOS device, prolonged the useful life of MOS device under abominable radiation environment simultaneously; Thereby, the device size of both having avoided adopting the non-flanged device to bring increases, also avoided adopting the circuit puncture voltage that P type silicon surface dopant concentration method causes under the raising field oxide to reduce, and described reinforcement process is simple and with the CMOS process compatible, and reinforcement process is suitable for commercially producing.
The feature of method provided by the invention is, in the isolation camp oxide layer of MOS device, inject one or more of doses nitrogen, fluorine, silicon, germanium plasma, so that dark electron trap and complex centre to be provided, this dark electron trap and complex centre in field oxide, be positioned at field oxide/silicon island near interface, neither on the interface, also not in the silicon of silicon island.
Implementation of the present invention is
The present invention, by in the oxide layer of place, producing dark electron trap/complex centre, suppress electronics from oxide layer to external migration.Thereby make oxide layer remain electric neutrality, the serviceability of device is also kept.The dopant ion that injects oxide layer should be able to firmly combine with any free electron that radiation damage causes, says that therefrom the nitrogen of injection, fluorine, silicon and germanium ion can well reach requirement.
The technical scheme that the present invention realizes:
1) after the etching silicon island of MOS device preparation technology flow process, injections, cleanings of removing photoresist, field oxidation, and in advance before the grid oxygen, in the oxide layer of place, injects a kind of of nitrogen, fluorine, silicon and germanium ion or their combination under the room temperature, at N
2Perhaps Ar atmosphere or Ar+3vol%O
2Protection under, the 30～60min that anneals under 800～1000 ℃ temperature normally carries out subsequent technique then.Energy that injects and dosage are according to the thickness decision of field oxide.
2) for the different device of isolated area field oxide parameter, it is different with dosage to inject energy of ions, but the peak value of the injection ion that finally obtains after the annealing all be arranged in the place oxide layer, be 800～1600 apart from Si and oxide layer interface
The place;
3) annealing and the standard CMOS process compatibility after the injection: temperature is for to carry out in 700～1000 ℃ of scopes, under inert atmosphere protection; Related MSO transistor can be silicon (SOI) MOS transistor on body silicon MOS transistor or the insulating barrier;
4) adopting local thermal oxidation (LOCOS) or shallow channel (STI) technology to obtain the place oxide layer isolates with the electricity of realizing device.
The used ion implantation technology of the present invention is very ripe technology, but characteristics of the present invention are the technology that adopts ion to inject the isolation camp oxide layer of MOS device are injected other foreign ions, thereby the MOS device is reinforced, reduce the edge leakage current of MOS device, improved the anti-integral dose radiation level of MOS device.The invention is characterized in that technological parameters such as dosage that ion injects, energy have significant effect to the anti-integral dose radiation performance that improves the MOS device.If the dosage that ion injects is too high, can the insulation property of isolating oxide layer be exerted an influence, be unfavorable for that the insulation between the device is isolated.If dosage is too low, then reinforcing is not had corresponding effect.To annotating the Si ion, dosage must reach and form Si nanocluster (Si Nanoclusters) in oxide layer, and the least possible to the damage of the insulation property of isolating oxide layer, and this dosage range probably is 1 * 10
15～l * 10
17Ions/cm
2Dosage is lower than 1 * 1O
15Ions/cm
2Time annealing back only can form the SiOx structure in field oxide, can not form the Si nanocluster, does not have the effect of reinforcing; Dosage too high (〉 5 * 1O
17Ions/cm
2) time, can in field oxide, can form the Silicon-rich structure, this has a negative impact to device performance.For the injection of F ion, dosage is l * 10
12～1 * 10
16Ions/cm
2In the scope; For the injection of N ion, dosage is 1 * 10
14M～1 * 10
17Ions/cm
2In the scope, dosage low excessively (＜1 * 10
14Ions/cm
2) not reaching the effect of reinforcing, the too high meeting of dosage forms one deck silicon nitride (Si in oxidation layer by layer
3N
4), even forming bubble, the lattice structure of this nitride and Si difference are bigger, thereby cause the fluctuating at interface, cause the insulation property of field oxide, finally influence the electric property of device.The dosage range that the Ge ion is injected is l * 10
11～5 * 10
15Ions/cm
2
Description of drawings
In Fig. 1 .MOS structure, the generation of irradiation induced charge, transmit and capture schematic diagram
The radiation that field oxide may exist among Fig. 2 .NMOSFET causes the leakage current passage
The radiation that field oxide may exist among Fig. 3 .SOI NMOSFET causes edge lateral sulcus leakage current passage
Fig. 4 .NMOSFET/SOI has shown the leakage current of side wall at the I-V curve of radiation front and back
Fig. 5. adopt SOI device that method provided by the invention reinforces under different radiation doses, the Ids-Vgs curve of device: (a) reinforce device, (b) comparative device
Fig. 6. the SOI device that adopts method reinforcing provided by the invention is under different radiation doses, and the Ids-Vgs curve (a) of device is reinforced device, (b) comparative device
Embodiment
The following example will help understands the present invention, but content of the present invention never limits embodiment.
With SOI MOSFET is example.The CMOS technology of employing standard is made in the process of MOS device on standard SIM OX disk, and after the oxidation step on the scene, the acquisition thickness of oxide layer is 300nm, adopts the mask plate protection then, and the injection energy is that 120keV, dosage are 1 * 10
16Cm
-2Silicon ion, at N
230min anneals under the protection of atmosphere, 1000 ℃ the temperature; Carry out subsequent technique then, until the manufacture craft of finishing whole MOS device.The SOI MOS device that obtain this moment does not have edge leakage current, has superior radiation resistance, as shown in Figure 5.
Inject ion and be respectively Si, or N, or F, technologies such as the implantation dosage degree of depth and annealing are listed in the table, after reinforcing, make the SOI insulating buried layer have superior radiation resistance.(shown in Figure 6) by in Fig. 5 and Fig. 6 curve as can be seen, through behind the irradiation, the leakage current of comparative sample increases suddenly, and the leakage current of reinforcing sample does not have obvious variation, and threshold voltage shift is significantly smaller than non-reinforcing sample; Behind 1.5Mrad (Si) irradiation, reinforce sample and still have good Ids-Vgs characteristic curve.
| No. | Inject ion | Dosage (ions/cm 2) | Annealing temperature (℃) | Time (h) | Protective atmosphere | The radiation resistance index |
| 2 | |
1×10 14 | 900～ 1000 | 1 | Ar | ～3×10 5rad(Si) |
| 3 | |
1×10 15 | 1 | N 2 | ||
| 4 | |
1×10 14 | ～1000 | 1 | |
3×10 5～5× 10 5rad(Si) |
| 5 | |
1×10 16 | 1 | Ar | ||
| 6 | |
1×10 17 | 1 | |
||
| 7 | |
5×10 15 | ～800 | 0.5 | Ar+3％O 2 | >5×10 5rad(Si) |
| 8 | |
4×10 16 | ～1000 | 1 | Ar+3％ |
|
| 9 | |
1×10 17 | ～900 | 0.8 | Ar |
Claims (7)
1. reinforcement means that improves metal oxide semiconductor device place anti-integral dose radiation; it is characterized in that after the etching silicon island, injections, the cleaning of removing photoresist, field oxidation in metal oxide semiconductor device preparation technology flow process; and before the pre-grid oxygen; in the oxide layer of place, inject a kind of of nitrogen, fluorine, silicon or germanium ion or their combination under the room temperature; under the protection of inert atmosphere; annealing temperature 30～60min in 800～1000 ℃; normally carry out subsequent technique then, the energy of injection and dosage are according to the thickness decision of field oxide.
2. by the reinforcement means of the described raising metal oxide semiconductor device of claim 1 place anti-integral dose radiation, it is characterized in that the dosage range that the Si ion injects is 1 * 10
15～1 * 10
17Cm
-2
3. by the reinforcement means of the described raising metal oxide semiconductor device of claim 1 place anti-integral dose radiation, it is characterized in that the dosage range that the nitrogen ion injects is 1 * 10
14～1 * 10
17Cm
-2
4. by the reinforcement means of the described raising metal oxide semiconductor device of claim 1 place anti-integral dose radiation, it is characterized in that the dosage range that fluorine ion injects is 1 * 10
12～1 * 10
16Cm
-2
5. by the reinforcement means of the described raising metal oxide semiconductor device of claim 1 place anti-integral dose radiation, it is characterized in that the dosage range that germanium ion injects is 1 * 10
11～5 * 10
15Cm
-2
6. press the reinforcement means of any described raising metal oxide semiconductor device place anti-integral dose radiation in the claim 1,2,3,4 or 5, the peak value of the injection ion that finally obtains after it is characterized in that annealing is arranged in the place oxide layer, is 800～1600 places apart from silicon and oxide layer interface.
7. by the reinforcement means of the described raising metal oxide semiconductor device of claim 1 place anti-integral dose radiation, it is characterized in that described inert atmosphere is Ar, nitrogen or Ar+3vol%0
2
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100248464A CN100373585C (en) | 2006-03-17 | 2006-03-17 | Hardening method for improving MOS device field total dose |
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|---|---|---|---|
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| CN1845308A CN1845308A (en) | 2006-10-11 |
| CN100373585C true CN100373585C (en) | 2008-03-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217925B (en) * | 2013-06-05 | 2017-07-18 | 中国科学院微电子研究所 | Method for reducing positive charge density in silicon-on-insulator (SOI) buried oxide layer |
| CN104269376B (en) * | 2014-09-24 | 2017-03-15 | 上海华力微电子有限公司 | The manufacture method of shallow trench isolation |
| CN108598168A (en) * | 2018-05-03 | 2018-09-28 | 深圳吉华微特电子有限公司 | The power field effect transistor and its manufacturing method of anti-integral dose radiation |
| CN111739838B (en) * | 2020-06-23 | 2023-10-31 | 中国科学院上海微***与信息技术研究所 | Preparation method of anti-radiation SOI material |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152798A (en) * | 1995-09-08 | 1997-06-25 | 日本电气株式会社 | Method for making radiation-resistance semiconductor integrated circuit |
| JPH1065156A (en) * | 1996-08-20 | 1998-03-06 | Nittetsu Semiconductor Kk | Manufacturing method for semiconductor device |
| CN1393935A (en) * | 2001-06-29 | 2003-01-29 | 富士通株式会社 | Semiconductor device with small bag and its mfg. |
| US6569781B1 (en) * | 2002-01-22 | 2003-05-27 | International Business Machines Corporation | Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation |
| US6825133B2 (en) * | 2003-01-22 | 2004-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer |
-
2006
- 2006-03-17 CN CNB2006100248464A patent/CN100373585C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152798A (en) * | 1995-09-08 | 1997-06-25 | 日本电气株式会社 | Method for making radiation-resistance semiconductor integrated circuit |
| JPH1065156A (en) * | 1996-08-20 | 1998-03-06 | Nittetsu Semiconductor Kk | Manufacturing method for semiconductor device |
| CN1393935A (en) * | 2001-06-29 | 2003-01-29 | 富士通株式会社 | Semiconductor device with small bag and its mfg. |
| US6569781B1 (en) * | 2002-01-22 | 2003-05-27 | International Business Machines Corporation | Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation |
| US6825133B2 (en) * | 2003-01-22 | 2004-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer |
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