CN100367477C - Technique for fabricating bipolar device under improved two-layer wiring - Google Patents
Technique for fabricating bipolar device under improved two-layer wiring Download PDFInfo
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- CN100367477C CN100367477C CNB2004100182612A CN200410018261A CN100367477C CN 100367477 C CN100367477 C CN 100367477C CN B2004100182612 A CNB2004100182612 A CN B2004100182612A CN 200410018261 A CN200410018261 A CN 200410018261A CN 100367477 C CN100367477 C CN 100367477C
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- Prior art keywords
- base
- propelling
- emitter region
- trap
- injection
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 53
- 238000002347 injection Methods 0.000 claims description 22
- 239000007924 injection Substances 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- 239000004411 aluminium Substances 0.000 claims description 13
- -1 phosphonium ion Chemical class 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 238000005530 etching Methods 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 238000005755 formation reaction Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The present invention discloses a manufacture process for a bipolar device of double-layer wire laying. The temperature during base-region propulsion is 950 DEG C to 1000 DEG C, and the time for the base-region propulsion is 100 minutes; the temperature during transmission-region propulsion is 950 DEG C to 1000 DEG C, and the time for the transmission-region propulsion is 30 to 60 minutes; injected arsenic (As) ions of large dosage are used as a transmission region, the injected dosage is not below E<15>, and the energy of the injected ions is 20 to 80 KeV. The size of a minimum opening of the device manufactured by the manufacture process of the present invention is 1.5 multiplied by 1.5 mum, and in such a way, the size of a chip is largely reduced; the depth of a base-region knot is 0.7 mum, the depth of a transmission-region knot is 0.4 mum, and thus, the manufactured high-frequency device is used in high-frequency occasions.
Description
Technical field
The present invention relates to the manufacturing process of bipolar device, relate in particular to a kind of manufacturing process of two-layer wiring bipolar device.
Background technology
Existing ambipolar Bipolar manufacturing process, no matter be two-layer wiring or the individual layer wiring, its smallest cell dimension is generally 3 * 4 μ m, junction depth is about 2 μ m.Not only chip area is big for the integrated circuit made from it, and can only be applied in the low frequency occasion.Along with development of integrated circuits, the client often needs the very little high performance integrated circuit of a kind of low pressure, hyperfrequency and chip area.So the manufacturing process of the bipolar device that just a kind of hole that has than minor diameter of needs, and junction depth is more shallow is its occasion that can be applicable to high frequency, low pressure.
The manufacturing process of traditional bipolar device comprises (is example to make two-layer wiring): make that substrate → making N trap → make P trap → formations extension → isolations on the substrate inject on substrate → dark phosphorus injects and propellings → base advances → dense boron injects and propellings → emitter region propellings → ground floor connects up (perforate → aluminium connects up) → second layer connects up (perforate → aluminium connects up) → formation protective layer.
Because the degree of depth of base and emitter region has directly determined the frequency and the voltage of this device, if therefore wish to obtain the bipolar device of low pressure, high frequency, how to control that the base advances and to advance these two processing steps be very crucial in the emitter region, in addition, adopt which kind of technology directly to determine the size of perforate in the opening step.Therefore, the improvement at above-mentioned processing step is the key that obtains high performance device.
Summary of the invention
The purpose of this invention is to provide a kind of two-layer wiring bipolar fabrication technology, it can make base, the more shallow device of the emitter region degree of depth, to satisfy the needs of low pressure, high frequency.
Another purpose of this kind manufacturing process provided by the invention is to have the littler perforate of size, can dwindle area of chip.
In order to achieve the above object, the present invention adopts following technical scheme:
A kind of two-layer wiring bipolar fabrication technology, wherein:
Temperature is 950 ℃～1000 ℃ when carrying out the base propelling, and the time that the base advances is 100 minutes;
Temperature is 950 ℃～1000 ℃ when carrying out the emitter region propelling, and the time that the emitter region advances is 30～60 minutes;
Adopt heavy dose of arsenic (As) ion that injects as the emitter region, the dosage of injection is not less than 1E15, and the injection energy of ions is 20～80KeV.
In the processing step of perforate, adopt dry etching and wet etching process combined.
The processing step that also comprises zero layer structure growth after epitaxially grown processing step, described zero layer structure growth is specifically designed to exposure on described extension.
After the ground floor wiring is finished, before the second layer wiring beginning, also has the flatening process step.
According to a preferred embodiment of the present invention; it specifically comprises following processing step: making N trap → on substrate, make step → growth zero layer structure → isolation injection DP trap → injection phosphonium ion of P trap → growth N type extension on the substrate and carrying out dark phosphorus propelling → base propelling → injection boron ion and advance → emitter region propelling → ground floor connects up; comprise perforate and aluminium wiring → planarisation step → second layer wiring, comprise perforate and aluminium wiring → formation protective layer.
Owing to adopted above-mentioned technical scheme, the smallest cell dimension of worker artistic skill of the present invention manufacturing is 1.5 * 1.5 μ m, has dwindled chip size so greatly.And its base junction depth is 0.7 μ m, and the emitter region junction depth is 0.4 μ m, and the high-frequency element that can be made into like this is used for the high frequency occasion.
Description of drawings
Fig. 1 is the manufacturing process flow diagram according to one embodiment of the present of invention;
Fig. 2 carries out the sectional view that the N trap advances in the foregoing description;
Fig. 3 carries out the sectional view that the P trap advances in the foregoing description;
Fig. 4 is an epitaxially grown sectional view in the foregoing description;
Fig. 5 isolates the sectional view that injects in the foregoing description;
Fig. 6 is the sectional view that dark phosphorus injects and advances in the foregoing description;
Fig. 7 is the sectional view that the base advances in the foregoing description;
Fig. 8 is the sectional view that dense boron injects and advances in the foregoing description;
Fig. 9 is the sectional view that the emitter region advances in the foregoing description;
Figure 10 is the sectional view of perforate in the foregoing description;
Figure 11 is the sectional view of aluminium wiring in the foregoing description;
Figure 12 is the cross section structure figure according to the NPN pipe of manufacturing process manufacturing of the present invention;
Figure 13 is the cross section structure figure according to the lateral PNP pipe of manufacturing process manufacturing of the present invention;
Figure 14 is the cross section structure figure according to the longitudinal P NP pipe of manufacturing process manufacturing of the present invention;
Figure 15 is according to the SP of manufacturing process manufacturing of the present invention and the cross section structure figure of IR resistance;
Figure 16 is the cross section structure figure according to the mos capacitance of manufacturing process manufacturing of the present invention.
Embodiment
Feature of the present invention, essence and advantage will be below become more obvious in conjunction with the embodiments with after the description of accompanying drawing.
The front said that the main improvement of the present invention was on base propelling, emitter region propelling and these three steps of perforate.The present invention advances by the control base and time of the temperature of emitter region propelling and propelling is controlled the junction depth of base and emitter region, adopts dry etching and wet etching process combined to realize perforate than minor diameter simultaneously.When shown in Figure 1 according to the concrete processing step of one embodiment of the present of invention, this embodiment is the technological process of two-layer wiring, need to prove, embodiment shown in Figure 1 is an exemplarily explanation, be not that manufacturing process of the present invention must accurately meet each step in the flow chart shown in Figure 1, as long as within the scope of thought of the present invention, carrying out suitable modification for step shown in Figure 1 all is that those skilled in the art expect easily.
As shown in Figure 1, the processing step among this embodiment specifically comprises:
Making N trap → on substrate, make step → growth zero layer structure → isolation injection DP trap → injection phosphonium ion of P trap → growth N type extension on the substrate and carrying out dark phosphorus propelling → base propelling → injection boron ion and advance → emitter region propelling → ground floor connects up; comprise perforate and aluminium wiring → planarisation step → second layer wiring, comprise perforate and aluminium wiring → formation protective layer.
Above-mentioned flow process is compared with traditional technological process, can find, on step, this embodiment has increased by two steps.The first is isolated and is injected the step that the DP trap has increased growth zero layer structure before after the step of growth N type extension.This is owing to adopt the full technology of injecting in the technical scheme of the present invention, can have problems for the exposure of the later level of extension, therefore increases by one zero layer structure, and this layer is specifically designed to exposure.It two is the steps that increased planarization between twice wiring, so-called planarization re-lays one deck such as BPSG (B+P+silicon Glass exactly, the silex glass that promptly contains B+ and P+ ion) material because it has flowability, can make smooth surface after covering this layer.Be the step that increases newly in two tangible flow processs of step above, some improvement for existing step of the present invention once be described below in conjunction with the sectional view that is in the device of different phase in each step.
Below description be to be that example describes with the process of making the NPN pipe, those of ordinary skill in the art should be appreciated that, following process is to have certain change making different components, but this change is predictable, should not be regarded as a departure from scope of the present invention.
Fig. 2 is a sectional view of making the N trap in the foregoing description on substrate.This step specifically comprises with the lower part: at first be that window → injection antimony ion → BN of oxidation → be then etching BN advances and forms N trap → removal oxide layer.Just form form as shown in Figure 2 afterwards, on substrate P-Substrate, form N trap BN.
Fig. 3 carries out the sectional view that the P trap advances in the foregoing description.This step specifically comprises with the lower part: at first be that window → injection boron ion → BP of oxidation → be then etching BP advances and forms P trap → removal oxide layer.Just form form as shown in Figure 3 afterwards, on substrate P-Substrate, form P trap BP.
Fig. 4 is an epitaxially grown sectional view in the foregoing description.In this embodiment, the extension of growth is the extension N-EPI of N type.
After this step, the present invention has also increased a step, is exactly the step of growth zero layer structure, is described above.Zero layer structure is specifically designed to exposure, and therefore just no longer special the picture represented.
Fig. 5 isolates the sectional view that injects the DP trap in the foregoing description.This step specifically comprises with the lower part: at first be to form oxide layer 501 → coat photoresist 502 → etching photoresist 502 to form DP windows → injections boron ions formation DP trap → DP trap propelling → removal oxide layer on oxide layer.Just form form as shown in Figure 5 afterwards, in N type extension N-EPI, form DP trap DP, be positioned at the top of P trap BP.
Fig. 6 is the sectional view that dark phosphorus injects and advances in the foregoing description.This step specifically comprises with the lower part: at first form oxide layer 601 → coat photoresist (not drawing among the figure) → etching photoresist and form also propelling → removal photoresist → removal oxide layer 601 (shown in Figure 6 is the situation of also not removing oxide layer) of window (position of DN correspondence does not illustrate among the figure) → injections phosphonium ion on oxide layer.Just form form as shown in Figure 6 afterwards, form the dark phosphorous diffusion district DN of N type in N type extension N-EPI, its degree of depth reaches the BN zone and part is deep in the BN zone.
Fig. 7 is the sectional view that the base advances in the foregoing description.This step specifically comprises with the lower part: at first form oxide layer 701 → coat photoresist 702 → etching photoresist and form also propelling → removal photoresist 702 → removal oxide layer 701 (shown in Figure 7 is the situation of also not removing oxide layer and photoresist) of window (position of SP correspondence) → injections boron ion on oxide layer.Just form form as shown in Figure 7 afterwards, form base SP in N type extension N-EPI, it is positioned at the top in BN zone.
Fig. 8 is the sectional view that dense boron injects and advances in the foregoing description.This step specifically comprises with the lower part: at first form oxide layer 801 → coat photoresist (not shown) → etching photoresist and form window (position of DB correspondence) on oxide layer, as shown in Figure 8, dense boron injection zone has three places, one place is the base, two places are arranged in two DP traps respectively in addition, position of window is corresponding with these positions → and to inject the boron ion and advance, its degree of depth of BD district that wherein is positioned at the base surpasses the degree of depth of base, but does not reach the N trap; Its degree of depth of DB district that is arranged in two DP traps is no more than the degree of depth of DP trap → removal photoresist → removal oxide layer 801 (shown in Figure 8 is the situation of also not removing oxide layer and photoresist).Just form form as shown in Figure 8 afterwards, in base SP, form dense boron diffusion district DB, in two DP traps, also form dense boron diffusion district DB.In the process that the base advances, its temperature and the time that continues are one of important improvement steps of the present invention, and temperature was 950 ℃～1000 ℃ when the base advanced in this embodiment, and the time that the base advances is about 100 minutes.The junction depth of the base that the use above-mentioned parameter obtains is at 0.7 μ m.
Fig. 9 is the sectional view that the emitter region advances in the foregoing description.This step specifically comprises with the lower part: at first form oxide layer 901 → coat photoresist (not shown) → etching photoresist and form window (position of SN correspondence) on oxide layer, as shown in Figure 9, dense boron injection zone has two places, one place is base (not contacting with dense boron diffusion district DB), another place is arranged in dark phosphorous diffusion district DN, position of window is corresponding with these positions → and to inject arsenic (AS) ion and advance, its degree of depth of SN district that wherein is positioned at the base is no more than the degree of depth of base; Its degree of depth of SN district that is arranged in dark boron diffusion district DN is no more than the DN degree of depth → removal photoresist → removal oxide layer 901 (shown in Figure 9 is the situation of also not removing oxide layer and photoresist).Just form form as shown in Figure 9 afterwards, in base SP, form emitter region SN, in dark phosphorous diffusion district DN, also form emitter region SN.In the process that the emitter region advances, its temperature and the time that continues also are one of important improvement steps of the present invention, and in this embodiment, temperature was 950 ℃～1000 ℃ when the emitter region advanced, and the time that the emitter region advances is 30～60 minutes.Simultaneously, the present invention adopts heavy dose of arsenic (As) ion that injects as the emitter region, and for example, in this embodiment, the As dosage of injection is not less than 1E15 (10 15 powers, promptly 10
15), the injection energy of ions is 20～80KeV.The junction depth of the emitter region that the use above-mentioned parameter obtains is at 0.4 μ m.
Figure 10 is the sectional view of perforate in the foregoing description.This step specifically comprises with the lower part: at first form the oxide layer 1001 that oxide layer 1001 → coat photoresist (not shown) → etching photoresist forms window (the corresponding position of SN and DB zone) → etching window position correspondence on oxide layer, keep the oxide layer 1001 → removal photoresist of other parts simultaneously.Just form form as shown in figure 10 afterwards, on two emitter region SN and dense boron diffusion district DB, form perforate.In this embodiment, adopt dry etching and wet etching process combined during perforate, so-called dry etching is exactly that using gases carries out etching, and use during wet etching solution to carry out etching, use dry etching separately or make wet etching can't reach 1.5 * 1.5 μ m diameters and the quality perforate preferably of expectation, because as using dry etching separately, the aperture border gradient of leaving is steeper, is unfavorable for wiring.Use wet etching separately, then can not satisfy the requirement of aperture live width.So method that the present invention adopts both to combine.
Figure 11 is the sectional view of aluminium wiring in the foregoing description.This step is simple relatively, injects aluminium in above-mentioned perforate respectively, has just formed wiring, single perforate and on aluminium be designated as C, B, E respectively, represent three utmost points of triode.
Because this technology is two-layer wiring, therefore above-mentioned opening step and aluminium wiring step all carry out twice, and to finish twice installation work, between twice wiring, the present invention has also added the processing step of a planarization, the described above mistake again.Re-lay one deck such as the BPSG material of (B+P+silicon Glass promptly contains the silex glass of B+ and P+ ion) exactly,, can make smooth surface after covering this layer because it has flowability.
At last, the good protective layer of regrowth can be finished technology.
Figure 12-the 16th adopts the sectional view of the various different components that manufacturing process of the present invention makes.Wherein Figure 12 is the cross section structure figure of NPN pipe, and Figure 13 is the cross section structure figure of lateral PNP pipe, and Figure 14 is the cross section structure figure of longitudinal P NP pipe, and Figure 15 is the cross section structure figure of SP and IR resistance, and Figure 16 is the cross section structure figure of mos capacitance.
Adopt the manufacturing process of technique scheme and parameter, the device smallest cell dimension of its manufacturing is 1.5 * 1.5 μ m, has dwindled chip size so greatly.And its base junction depth is 0.7 μ m, and the emitter region junction depth is 0.4 μ m, and the high-frequency element that can be made into like this is used for the high frequency occasion.
The foregoing description provides to being familiar with the person in the art and realizes or use of the present invention; those skilled in the art can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (4)
1. two-layer wiring bipolar fabrication technology is characterized in that:
Temperature is 950 ℃～1000 ℃ when carrying out the base propelling, and the time that the base advances is 100 minutes;
Temperature is 950 ℃～1000 ℃ when carrying out the emitter region propelling, and the time that the emitter region advances is 30～60 minutes;
Adopt heavy dose of arsenic ion that injects as the emitter region, the dosage of injection is not less than 1E15, and the injection energy of ions is 20～80KeV.
2. manufacturing process as claimed in claim 1 is characterized in that, specifically comprises following processing step:
Making N trap → on substrate, make step → growth zero layer structure → isolation injection DP trap → injection phosphonium ion of P trap → growth N type extension on the substrate and carrying out dark phosphorus propelling → base propelling → injection boron ion and advance → emitter region propelling → ground floor connects up; comprise perforate and aluminium wiring → planarisation step → second layer wiring, comprise perforate and aluminium wiring → formation protective layer.
3. manufacturing process as claimed in claim 2 is characterized in that, in the processing step of perforate, adopts dry etching and wet etching process combined.
4. manufacturing process as claimed in claim 3 is characterized in that, described zero layer structure growth is specifically designed to exposure on described extension.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100182612A CN100367477C (en) | 2004-05-12 | 2004-05-12 | Technique for fabricating bipolar device under improved two-layer wiring |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100182612A CN100367477C (en) | 2004-05-12 | 2004-05-12 | Technique for fabricating bipolar device under improved two-layer wiring |
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| CN1697145A CN1697145A (en) | 2005-11-16 |
| CN100367477C true CN100367477C (en) | 2008-02-06 |
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| CNB2004100182612A Expired - Lifetime CN100367477C (en) | 2004-05-12 | 2004-05-12 | Technique for fabricating bipolar device under improved two-layer wiring |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211843B (en) * | 2006-12-30 | 2010-05-19 | 上海先进半导体制造股份有限公司 | Small size contact hole two polar-type fabrication process |
| CN108470715B (en) * | 2018-04-04 | 2020-08-28 | 华越微电子有限公司 | Double-layer wiring planarization processing technology |
| CN113838747A (en) * | 2020-06-23 | 2021-12-24 | 上海先进半导体制造有限公司 | Semiconductor device with epitaxial layer and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1349661A (en) * | 1999-04-30 | 2002-05-15 | 罗姆股份有限公司 | Semicondcutor device having bipolar transistors |
| US20020105054A1 (en) * | 1999-09-27 | 2002-08-08 | Taiwan Semiconductor Manufacturing Company | High voltage transistor using P+ buried layer |
| US6440812B2 (en) * | 1995-08-25 | 2002-08-27 | Micron Technology, Inc. | Angled implant to improve high current operation of bipolar transistors |
| CN1381881A (en) * | 2001-04-18 | 2002-11-27 | 上海贝岭股份有限公司 | Process for preparing bipolar IC |
-
2004
- 2004-05-12 CN CNB2004100182612A patent/CN100367477C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6440812B2 (en) * | 1995-08-25 | 2002-08-27 | Micron Technology, Inc. | Angled implant to improve high current operation of bipolar transistors |
| CN1349661A (en) * | 1999-04-30 | 2002-05-15 | 罗姆股份有限公司 | Semicondcutor device having bipolar transistors |
| US20020105054A1 (en) * | 1999-09-27 | 2002-08-08 | Taiwan Semiconductor Manufacturing Company | High voltage transistor using P+ buried layer |
| CN1381881A (en) * | 2001-04-18 | 2002-11-27 | 上海贝岭股份有限公司 | Process for preparing bipolar IC |
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