Disclosure of Invention
The invention aims to provide a method for effectively avoiding hot spots and uniformly distributing test heat on the surface of a chip in the SOC test process, thereby protecting the tested chip, improving the yield of the chip, reducing the test time and reducing the test cost.
The problems of the present invention are described below:
given a SOC, comprising N IP cores i (1. Ltoreq. I. Ltoreq.N), for each Core i Test T i ={w i ,t i ,p i ,v i Where w is 1. Ltoreq. I.ltoreq.N) i Is T i Width, t, of assigned test channel (TAM) i Time required for the test, p i For maximum power consumed during the test, v i Is a test vector; let the total width of the test channel (TAM) be W max Maximum test allowable Power of P max The maximum allowable temperature rise is Δ T max The shortest distance d that two cores can simultaneously test is allow (ii) a Determining each Core i The width of the test channel (TAM), and the time to start the test, are required to meet the following criteria:
(i) The heat during the test is distributed on the SOC surface as evenly as possible;
(ii) Core at any time i All of which are less than Δ T max ;
(iii) The total power consumed by the test at any time is less than P max ;
(iv) The overall test time of the SOC is shortest;
criteria (i) and (ii) are that heat is required to be evenly distributed over the SOC surface during the test, and that the temperature rise on each Core is less than Δ T max Thereby avoiding hot spots. Whereas previous studies only considered (iii) and (iv), although (iii), i.e., the overall power was less than P, was considered max It cannot guarantee that no hot spot occurs locally, i.e. that the chip can work safely.
The SOC test method provided by the invention is a solution to the above problems. The method comprises the following specific steps:
1. establishing an SOC test temperature-rising table by using a heat diffusion formula to describe Core in an SOC test i The temperature rise value of (1), the temperature rise table comprising Core i Self-power-consumption-induced temperature rise and other simultaneous eventsCore tested j (j ≠ i) two parts of heating caused by power consumption;
2. establish a criterion whether two cores can be tested simultaneously: testing when cores which are close to each other in space are different, wherein the proximity degree of the cores is determined by actual testing requirements;
3. constructing a test compatibility chart: g t =(V t ,E t ) Wherein, V t Represents a test T for a node i ,E t A line connecting two nodes indicates that two tests can be performed simultaneously;
4. extract Parallel Test Set (PTS): extracting a parallel test set from the test compatibility graph according to the criteria (ii) and (iii);
5. and (3) carrying out test planning: the method comprises Bin-Packing construction and global optimization aiming at the parallel test set, and the test time is shortened to the maximum extent.
Detailed Description
The following further describes embodiments of the present invention.
1. Establishing SOC test heating table
The invention can adopt the on-chip thermal diffusion formula proposed in the document [1] to calculate the temperature rise value of each Core in the SOC chip test process, and establish the SOC test temperature rise table. (other heat diffusion equations can be used to calculate)
(1) Simplified heat diffusion formula
The on-chip thermal diffusion formula proposed in document [1] is as follows:
ΔT=P×F(x,y,t)……(1)
wherein, X is the distance from the observation point to the heating source along the X-axis direction, and Y is the distance from the observation point to the heating source along the Y-axis direction; Δ T represents a temperature rise value after a lapse of time T from an observation point of Manhattan distance x + y from the heat generation source, for example, core in FIG. 1 1 And Core 5 The Manhattan distance between the heating sources is x 15 +y 15 (ii) a P is the power consumed by the heat source, in this case, each Core, and P is the maximum power P consumed in the test process max (ii) a F (x, y, t) is the diffusion factor of heat.
(2) Self power consumption induced temperature rise
For Core i The temperature rise caused by self-heating in the test process can be obtained by the formula (1) ii =P i ×F(0,0,t i ) In which P is i Is Core i The maximum power consumed by the test procedure of (1), t i For testing Core i The required time, x =0 and y =0, indicates that the observation point is at the heat generation source itself.
(3) Temperature rise due to power consumption of other cores (cores) being tested simultaneously
For Core i The temperature rise is also due to other cores being tested simultaneously j (i ≠ j) at Core i The heat on the part is dissipated, and the temperature rise of the part is expressed as sigma j ΔT ji (j ≠ i) where Δ T ji =P j ×F(X ji ,Y ji ,t ji ),P j Is Core j Maximum power consumed during the test, X ji Is Core j To Core i Distance in X-axis direction of heat source, Y ji Is Core j To Core i Distance in Y-axis direction of heat source, t ji Is Core j And Core i At the same timeTime of test, wherein t ji =|t j -t i |。
Through the above process, a test warm-up table of the SOC can be established. For example, FIG. 1 shows an SOC consisting of 5 cores, and the temperature rising table is shown in attached Table 1. Wherein, Δ T 11 Is Core 1 Self-heating caused by power consumption during testing; delta T 15 Is Core 1 Core due to power consumption during testing 5 Heating; delta T 51 Is Core 5 Due to power consumption during testingCore 1 And (4) increasing the temperature. After the Test heating table is obtained, the invention ensures a certain Core in the Test-Schedule i Temperature increase Δ T i ≤ΔT max To avoid the occurrence of hot spots, wherein Δ T max Is Core i An upper limit of temperature rise beyond which Hot spots (Hot-spots) may occur; delta T i =T ii +∑ j ΔT ji (j ≠ i) wherein Core i And Core j (i ≠ j) the tests were performed simultaneously.
2. Establishment of uniformly distributed heat standards
The present invention arranges a test sequence according to the heat generation of each Core and the position information on the SOC, thereby achieving uniform distribution of heat. This is done by not performing simultaneous tests on several cores that are spatially adjacent, thus avoiding Hot-spots and distributing heat to some extent. The invention judges Core i And Core j The Manhattan (Manhattan) distance between the two cores to determine whether the two cores can be tested simultaneously, if the distance d ji <d allow The present invention recognizes that the two cores are in close proximity and they do not allow for simultaneous testing. Wherein d is allow A constant defined for the user, d ji =|x i -x j |+|y i -y j The | being two cores i And Core j Manhattan distance between (x) i ,y i ) Is Core i (ii) a central coordinate of (x) j ,y i ) Is Core j The center coordinates of (a).
3. Extract Parallel Test Set (PTS)
A Parallel Test Set (PTS) is a set of tests that can be performed simultaneously. The invention will pass TCG [2] (Test compatibility graph-Test compatibility graph) to extract PTS, one TCG is G t =(V t ,E t ) In which V is t For a set of nodes, each node represents a test T i ,E t The connection line of every two nodes is a collection of connection lines of two nodes, and the connection line of every two nodes indicates that two tests can be performed simultaneously. As can be seen from the above description of the problems, the four criteria to be considered in the Test-Schedule (Test-Schedule) of the present invention are: (i) The heat during the test is distributed on the SOC surface as evenly as possible; (ii) Each Core at any time i All temperature rises above are less than Δ T max (ii) a (iii) The total power consumed by the test at any moment is less than P max (ii) a (iv) overall test time for SOC is shortest.
The procedure for constructing the TCG is as follows:
(1) First, the present invention establishes an initial TCG without any constraints, and the TCG is a complete graph as shown in fig. 2 (a).
(2) Consider the criteria (i) that during testing, heat is evenly distributed across the surface of the SOC, cores that are spatially adjacent cannot be tested simultaneously, and there are no wires between them in the TCG. The invention derives another TCG based on this constraint.
(3) Taking into account the criterion (ii) that the total power of two cores is less than P when they are tested simultaneously max . Again, consider criterion (iii) that two cores are tested simultaneously with their respective temperature increases less than Δ T max . The TCG of the present invention is further updated to that shown in fig. 2 (b) based on these two constraints.
And (3) PTS (partial Transmit sequence) extraction:
through these three steps, the present invention establishes a TCG that satisfies the uniform heat distribution and the power and Hot-Spot constraints, as shown in FIG. 2 (b) of the accompanying drawings. Obtaining a series from the established TCGTest set of columns, which consist of nodes of the complete subgraph in the TCG. The present invention is disclosed in the following document [3 ]]And (4) solving a complete subgraph algorithm, extracting all complete subgraphs of the TCGP, and constructing a corresponding test set. For a test set composed of complete subgraphs, noting that the test set composed of two elements must be PTS, the present invention checks the test set with more than 2 elements to determine whether criteria (ii) and (iii) are also satisfied, and if so, it is PTS; if not, each proper subset of one less element is checked and the operation is repeated until a test set is obtained that satisfies both criteria (ii) and (iii), which is a PTS. For example, each PTS obtained in FIG. 2 (b) is PTS 1 ={T 1 ,T 2 ,T 4 }、PTS 2 ={T 1 ,T 3 }、PTS 3 ={T 3 ,T 5 }。
4. Bin-Packing construction facing PTS and global optimization
After a series of PTS is obtained, test-scheduling can be carried out, and the Test-scheduling process in the invention is based on Bin-Packing initial construction facing the PTS and is combined with global optimization. Fig. 3 is a schematic diagram of constructing an initial test plan, and fig. 4 is a schematic diagram of global optimization. The process is as follows:
first Step (Step 1) and second Step (Step 2):
first give each test T i (1 ≦ i ≦ N) assigning the optimal test channel (TAM) width w i_op (w i_op ≤W max ) Thereby minimizing testing time. If a certain PTS j In each test T i (T i ∈PTS j ) The sum of the assigned test channels (TAM) is greater than W max Decreasing at PTS at this time j The test channel (TAM) width of the test T with the shortest test time is reduced by one every time the TAM is detected, and such operations are repeated until PTS j In each test T i (T i ∈PTS j ) The sum of the assigned test channels (TAM) is less than or equal to W max 。
Third Step (Step 3) and fourth Step (Step 4):
for each test T i According to test time t i Sorting in descending order, placing in set TS, packing one by one, each time testing T i Packing is carried out and then T is put i And deleted from the TS. And update T i State of (2) and state of session. When to T i When Packing is carried out, whether each session can accommodate T or not is checked firstly i . If there are multiple sessions, T can be accommodated i The one with the smallest time span is selected if no single session can accommodate T i Then see if there are consecutive sessions that can accommodate T i If there are also multiple choices, then pick the one with the smallest time span; if neither case is satisfied, then T is applied i After the last session. As shown in FIG. 3 as T 3 Can go to sessionS 3 Or sessionS 4 But due to sessionS 3 Is less than S 4 Then T 3 Is put to sessionS 3 。
Step 5 (Step 5) and Step 6 (Step 6):
put one T at a time i The state of session and T are updated afterwards i The state of (c). As shown in fig. 3, there are foursessions are S respectively 1 、S 2 、S 3 、S 4 The end time of each session and a certain T i Corresponds to the end time of (2), and the start time of each session is also associated with a certain T i Corresponds to the start time of (c). A test T i There may be only one session, such as T 4 Or T 5 There may also be multiple sessions such as T 1 Or T 2 . While only one test, such as S, may be performed in a session 3 、S 4 It is also possible to perform multiple tests such as S 1 、S 2 The test channel (TAM) width of each session must be less than or equal to W max 。
(i)T i Is in a state of T _ status 1 ={t 0 ,t 1 ,w i Se } is represented by 0 Represents T i Starting time, t 1 Represents T i End time, w i Represents T i Allocated TAM width, se denotes T i Which sessions are divided. As shown by T in FIG. 3 1 Is T _ status 1 ={t 0 =0,t 1 =1600,w 1 =8,se={S 1 ,S 2 ,S 3 }}。
(ii)session i Is in a state of S _ status 1 ={t 0 ,t 1 Test, TAM _ avail } where t is 0 Indicating session i Starting time, t 1 Indicating session i End time, test represents session i Which tests T are included, TAM _ avail indicates session i There are also how many TAMs that are not used. As shown by S in FIG. 3 4 Is S _ status 4 ={t 0 =1600,t 1 =2400, test={T 3 },TAM_avail=8}。
Step 8 (Step 8):
after the previous 7 steps, an initial test strategy is obtained, which is further globally optimized as shown in fig. 4 (a), by increasing the width of the test channel (TAM) for the test T that determines the whole SOC test time, thereby reducing the whole SOC test time by reducing the test time of the test T, and ensuring that the TAM width of each session cannot exceed w when increasing the TAM width for the test T max This operation is repeated until the test time of the SOC cannot be reduced. For example, T in FIG. 4 5 And T 1 Directly determines the test time of the whole SOC, firstly considering T 5 Increase the width of TAM when T 5 When the TAM width of the T can not be increased, the T is increased 1 Due to sessionS 1 Has run out of TAM, therefore T 1 The TAM width of (a) cannot be increased any more.
Pseudo code of PTS-oriented Bin-Packing construction and combination of global optimization process is as follows:
PTS Oriented Bin-Packing Procedure
Step 1:Assign the most optimal TAM width to every test T i _(1≤i≤N);
Step 2:Check every PTS such that the total TAM width of a PTS do not exceed W max ;
Step 3:Sort every test T i (1≤i≤N)in TS (TS={…T…})in descending order of
test time;
Step 4:Schedule the first test T i in TS and then remove it from TS;
Step 5:Update test T i (1≤i≤N)status;
Step 6:Update session status;
Step 7:If TS≠φthen go to step 4;
Step 8:Increase the TAM widths of the tests which dominate the total SOC test
time;
results and analysis of the experiments
The invention will be used for ITC02benchmark SOC [4] : h953 D695, f2126, q12710 as test cases. FIG. 2 shows the results of d695 test cases, the results being the total test time in clock cycles, and the results are compared with the document [5 ]]The experimental results of (a) were compared. Wherein the same reference is adopted [5 ]]The same constraint, i.e. the constraint that only the test power consumption is considered. In table 2, the "W" column indicates a test channel width (TAM); the "lower limit" column represents the lower limit of the test time; "[5]Results "column represents document [5 ]]The experimental results in (1); the "results herein" list indicates the experimental results of the present invention; the "improved" column indicates the results herein versus document [5 ]]The time of the results improves. As can be seen from the attached Table 2, in the same constraint barThe results of the present invention are improved to different degrees under different test channels (TAM) because the Bin-Packing algorithm of the present invention is globally optimized after obtaining an initial result by a construction method (see the pseudo code step 8), and the document [5 ]]There is not a global optimization process.
The attached table 3 is a test result of the test cases h953, d695, f2126 and q12710, the attached table 3 has two parts, the first part only considers the constraint of power consumption, and the second part considers the constraint of Hot-Spot, uniform heat distribution and power consumption; the "SOC" column represents a test case; "W" column indicates the width of the test channel; "t" s
max "column indicates the highest temperature during the test;
the column indicates the average temperature of the test procedure; "Δ (%)" column is the percentage of change in experimental results under different constraints. For example, in attached Table 3, for test case h
953 When the width of the test channel is 16 and only the power consumption constraint is considered, the experimental result t
max =6248、
When constraints of Hot-Spot, uniform heat distribution and power consumption are considered, the experimental result t
max =5995、
Thus the maximum temperature t
max Δ (%) = (5995-6248)/6248 = -4.0%, average temperature
Δ (%) = (2168-1593)/2168 = -26.5%. Therefore, after hot spot avoidance and uniform heat distribution are considered, the maximum temperature and the average temperature in the testing process are greatly reduced, and the problem of heating caused by strong testing power consumption in the chip testing process is effectively solved.
ΔT 11 |
ΔT 12 |
ΔT 13 |
ΔT 14 |
ΔT 15 |
ΔT 21 |
ΔT 22 |
ΔT 23 |
ΔT 24 |
ΔT 25 |
ΔT 31 |
ΔT 32 |
ΔT 33 |
ΔT 34 |
ΔT 35 |
ΔT 41 |
ΔT 42 |
ΔT 43 |
ΔT 44 |
ΔT 45 |
ΔT 51 |
ΔT 52 |
ΔT 53 |
ΔT 54 |
ΔT 55 |
Table 1: SOC test thermometer (example)
SOC
|
W
|
Lower limit of
|
[5]Results
|
Results herein
|
Improvements in or relating to
|
d695
|
16
|
39437
|
47574
|
43457
|
4117
|
24
|
26289
|
--
|
31139
|
--
|
32
|
23670
|
29039
|
25968
|
3071
|
40
|
20439
|
--
|
20549
|
--
|
48
|
15698
|
28441
|
15698
|
12743
|
56
|
14660
|
--
|
14780
|
--
|
64
|
13228
|
20004
|
13420
|
6584
|
Table 2 shows a comparison of the test results of the test case d695
|
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