CN100367041C

CN100367041C - System level chip detecting method capable of avoiding heat point and uniformly distributing heat

Info

Publication number: CN100367041C
Application number: CNB2005100273796A
Authority: CN
Inventors: 陈建; 周晓方; 赵长虹; 周电
Original assignee: Fudan University
Current assignee: Lilianxin Tianjin Electronic Components Co ltd
Priority date: 2005-06-30
Filing date: 2005-06-30
Publication date: 2008-02-06
Anticipated expiration: 2025-06-30
Also published as: CN1715936A

Abstract

The present invention belongs to the technical field of an integrated circuit computer aided test, particularly to a method for avoiding occurring hot spots and evenly distributing testing heat in the process of a system-level chip test. The method comprises the procedures of establishing an SOC testing heating table, constructing a testing compatible picture, extracting parallel test collection, carrying out a test plan, etc., wherein the test plan comprises: the Bin-Packing initial constitution of a parallel test collection combined with overall optimization, and the test time is maximally shortened. The method of the present invention can effectively avoid occurring the hot spots, and ensures homogeneous distribution of the testing heat quantity.

Description

System-on-chip testing method capable of avoiding hot spots and uniformly distributing heat

Technical Field

The invention belongs to the technical field of integrated circuit computer aided design and computer aided test, and particularly relates to a method for effectively avoiding hot spots and uniformly testing heat distribution in a system-on-chip (SOC) test process.

Technical Field

With the development of semiconductor manufacturing processes and the increase of functional requirements for individual chips, the demand for SOCs has become greater and greater. An SOC implements the functionality of the entire system on a single chip, possibly integrating microprocessor cores, DSP cores, memory cores, ASIC cores, digital-to-analog hybrids, RF circuits, and the like. The design of the SOC is based on an IP Core (Core), which shortens the design time, but increases the test difficulty and the test cost. In testing an SOC, first the Core to be tested is isolated from its surrounding circuitry by Test wrapper logic (Test wrapper) and second Test stimuli and Test responses are transmitted between pins (pins) of the SOC and the Core through Test channels (TAMs). The Test-Schedule (Test-Schedule) is how to reasonably arrange the Test of each Core under the condition of limited Test resources, so that the total Test time is shortest under the condition of meeting various constraints.

The powerful functions of the SOC bring great power consumption and heat generation, and the improvement of the integration level enables the heat to be more concentrated, so that Hot spots (Hot-spots) can be generated when the chip works. The occurrence of hot spots will make the chip extremely unstable and even burn out the chip. In the test mode, the power of the SOC is higher than that of the normal working mode due to the higher turnover frequency and even reaches 2 to 3 times of that of the normal working mode, so that the chip can be burnt during testing or cannot be tested due to unstable performance caused by high heat generation, and the yield is reduced. Therefore, the power heating problem caused by the function and the integration level must be considered during the test. In order to protect the system-on-chip in the test mode, the test sequence of each Core (Core) must be arranged reasonably, so that Hot-Spot (Hot-Spot) is avoided during testing, heat can be uniformly distributed on the system-on-chip, and the yield is improved. However, current research on system-on-chip testing only considers the shortest testing time under the condition that power meets the constraint, and does not relate to the problem of how to avoid Hot-Spot and heat sharing in testing. The invention provides a method for testing and planning SOC (Test-Schedule) by considering the problems of hot spots and heat sharing.

Disclosure of Invention

The invention aims to provide a method for effectively avoiding hot spots and uniformly distributing test heat on the surface of a chip in the SOC test process, thereby protecting the tested chip, improving the yield of the chip, reducing the test time and reducing the test cost.

The problems of the present invention are described below:

given a SOC, comprising N IP cores _i (1. Ltoreq. I. Ltoreq.N), for each Core _i Test T _i ＝{w _i ，t _i ，p _i ，v _i Where w is 1. Ltoreq. I.ltoreq.N) _i Is T _i Width, t, of assigned test channel (TAM) _i Time required for the test, p _i For maximum power consumed during the test, v _i Is a test vector; let the total width of the test channel (TAM) be W _max Maximum test allowable Power of P _max The maximum allowable temperature rise is Δ T _max The shortest distance d that two cores can simultaneously test is _allow (ii) a Determining each Core _i The width of the test channel (TAM), and the time to start the test, are required to meet the following criteria:

(i) The heat during the test is distributed on the SOC surface as evenly as possible;

(ii) Core at any time _i All of which are less than Δ T _max ；

(iii) The total power consumed by the test at any time is less than P _max ；

(iv) The overall test time of the SOC is shortest;

criteria (i) and (ii) are that heat is required to be evenly distributed over the SOC surface during the test, and that the temperature rise on each Core is less than Δ T _max Thereby avoiding hot spots. Whereas previous studies only considered (iii) and (iv), although (iii), i.e., the overall power was less than P, was considered _max It cannot guarantee that no hot spot occurs locally, i.e. that the chip can work safely.

The SOC test method provided by the invention is a solution to the above problems. The method comprises the following specific steps:

1. establishing an SOC test temperature-rising table by using a heat diffusion formula to describe Core in an SOC test _i The temperature rise value of (1), the temperature rise table comprising Core _i Self-power-consumption-induced temperature rise and other simultaneous eventsCore tested _j (j ≠ i) two parts of heating caused by power consumption;

2. establish a criterion whether two cores can be tested simultaneously: testing when cores which are close to each other in space are different, wherein the proximity degree of the cores is determined by actual testing requirements;

3. constructing a test compatibility chart: g _t ＝(V _t ，E _t ) Wherein, V _t Represents a test T for a node _i ，E _t A line connecting two nodes indicates that two tests can be performed simultaneously;

4. extract Parallel Test Set (PTS): extracting a parallel test set from the test compatibility graph according to the criteria (ii) and (iii);

5. and (3) carrying out test planning: the method comprises Bin-Packing construction and global optimization aiming at the parallel test set, and the test time is shortened to the maximum extent.

Drawings

FIG. 1 is a layout of an SOC.

Fig. 2 is a configuration of TCG. Fig. 2 (a) shows a TCG without any constraint, and fig. 2 (b) shows a TCG in which a plurality of constraints are taken into consideration.

Fig. 3 is a diagram of constructing an initial test strategy.

FIG. 4 is a global optimization of an initial test strategy. Fig. 4 (a) is before global optimization, and fig. 4 (b) is after global optimization.

Detailed Description

The following further describes embodiments of the present invention.

1. Establishing SOC test heating table

The invention can adopt the on-chip thermal diffusion formula proposed in the document [1] to calculate the temperature rise value of each Core in the SOC chip test process, and establish the SOC test temperature rise table. (other heat diffusion equations can be used to calculate)

(1) Simplified heat diffusion formula

The on-chip thermal diffusion formula proposed in document [1] is as follows:

ΔT＝P×F(x，y，t)……(1)

wherein, X is the distance from the observation point to the heating source along the X-axis direction, and Y is the distance from the observation point to the heating source along the Y-axis direction; Δ T represents a temperature rise value after a lapse of time T from an observation point of Manhattan distance x + y from the heat generation source, for example, core in FIG. 1 ₁ And Core ₅ The Manhattan distance between the heating sources is x ₁₅ +y ₁₅ (ii) a P is the power consumed by the heat source, in this case, each Core, and P is the maximum power P consumed in the test process _max (ii) a F (x, y, t) is the diffusion factor of heat.

(2) Self power consumption induced temperature rise

For Core _i The temperature rise caused by self-heating in the test process can be obtained by the formula (1) _ii ＝P _i ×F(0，0，t _i ) In which P is _i Is Core _i The maximum power consumed by the test procedure of (1), t _i For testing Core _i The required time, x =0 and y =0, indicates that the observation point is at the heat generation source itself.

(3) Temperature rise due to power consumption of other cores (cores) being tested simultaneously

For Core _i The temperature rise is also due to other cores being tested simultaneously _j (i ≠ j) at Core _i The heat on the part is dissipated, and the temperature rise of the part is expressed as sigma _j ΔT _ji (j ≠ i) where Δ T _ji ＝P _j ×F(X _ji ，Y _ji ，t _ji )，P _j Is Core _j Maximum power consumed during the test, X _ji Is Core _j To Core _i Distance in X-axis direction of heat source, Y _ji Is Core _j To Core _i Distance in Y-axis direction of heat source, t _ji Is Core _j And Core _i At the same timeTime of test, wherein t _ji ＝|t _j -t _i |。

Through the above process, a test warm-up table of the SOC can be established. For example, FIG. 1 shows an SOC consisting of 5 cores, and the temperature rising table is shown in attached Table 1. Wherein, Δ T ₁₁ Is Core ₁ Self-heating caused by power consumption during testing; delta T ₁₅ Is Core ₁ Core due to power consumption during testing ₅ Heating; delta T ₅₁ Is Core ₅ Due to power consumption during testingCore ₁ And (4) increasing the temperature. After the Test heating table is obtained, the invention ensures a certain Core in the Test-Schedule _i Temperature increase Δ T _i ≤ΔT _max To avoid the occurrence of hot spots, wherein Δ T _max Is Core _i An upper limit of temperature rise beyond which Hot spots (Hot-spots) may occur; delta T _i ＝T _ii +∑ _j ΔT _ji (j ≠ i) wherein Core _i And Core _j (i ≠ j) the tests were performed simultaneously.

2. Establishment of uniformly distributed heat standards

The present invention arranges a test sequence according to the heat generation of each Core and the position information on the SOC, thereby achieving uniform distribution of heat. This is done by not performing simultaneous tests on several cores that are spatially adjacent, thus avoiding Hot-spots and distributing heat to some extent. The invention judges Core _i And Core _j The Manhattan (Manhattan) distance between the two cores to determine whether the two cores can be tested simultaneously, if the distance d _ji ＜d _allow The present invention recognizes that the two cores are in close proximity and they do not allow for simultaneous testing. Wherein d is _allow A constant defined for the user, d _ji ＝|x _i -x _j |+|y _i -y _j The | being two cores _i And Core _j Manhattan distance between (x) _i ，y _i ) Is Core _i (ii) a central coordinate of (x) _j ，y _i ) Is Core _j The center coordinates of (a).

3. Extract Parallel Test Set (PTS)

A Parallel Test Set (PTS) is a set of tests that can be performed simultaneously. The invention will pass TCG ^[2] (Test compatibility graph-Test compatibility graph) to extract PTS, one TCG is G _t ＝(V _t ，E _t ) In which V is _t For a set of nodes, each node represents a test T _i ，E _t The connection line of every two nodes is a collection of connection lines of two nodes, and the connection line of every two nodes indicates that two tests can be performed simultaneously. As can be seen from the above description of the problems, the four criteria to be considered in the Test-Schedule (Test-Schedule) of the present invention are: (i) The heat during the test is distributed on the SOC surface as evenly as possible; (ii) Each Core at any time _i All temperature rises above are less than Δ T _max (ii) a (iii) The total power consumed by the test at any moment is less than P _max (ii) a (iv) overall test time for SOC is shortest.

The procedure for constructing the TCG is as follows:

(1) First, the present invention establishes an initial TCG without any constraints, and the TCG is a complete graph as shown in fig. 2 (a).

(2) Consider the criteria (i) that during testing, heat is evenly distributed across the surface of the SOC, cores that are spatially adjacent cannot be tested simultaneously, and there are no wires between them in the TCG. The invention derives another TCG based on this constraint.

(3) Taking into account the criterion (ii) that the total power of two cores is less than P when they are tested simultaneously _max . Again, consider criterion (iii) that two cores are tested simultaneously with their respective temperature increases less than Δ T _max . The TCG of the present invention is further updated to that shown in fig. 2 (b) based on these two constraints.

And (3) PTS (partial Transmit sequence) extraction:

through these three steps, the present invention establishes a TCG that satisfies the uniform heat distribution and the power and Hot-Spot constraints, as shown in FIG. 2 (b) of the accompanying drawings. Obtaining a series from the established TCGTest set of columns, which consist of nodes of the complete subgraph in the TCG. The present invention is disclosed in the following document [3 ]]And (4) solving a complete subgraph algorithm, extracting all complete subgraphs of the TCGP, and constructing a corresponding test set. For a test set composed of complete subgraphs, noting that the test set composed of two elements must be PTS, the present invention checks the test set with more than 2 elements to determine whether criteria (ii) and (iii) are also satisfied, and if so, it is PTS; if not, each proper subset of one less element is checked and the operation is repeated until a test set is obtained that satisfies both criteria (ii) and (iii), which is a PTS. For example, each PTS obtained in FIG. 2 (b) is PTS ₁ ＝{T ₁ ，T ₂ ，T ₄ }、PTS ₂ ＝{T ₁ ，T ₃ }、PTS ₃ ＝{T ₃ ，T ₅ }。

4. Bin-Packing construction facing PTS and global optimization

After a series of PTS is obtained, test-scheduling can be carried out, and the Test-scheduling process in the invention is based on Bin-Packing initial construction facing the PTS and is combined with global optimization. Fig. 3 is a schematic diagram of constructing an initial test plan, and fig. 4 is a schematic diagram of global optimization. The process is as follows:

first Step (Step 1) and second Step (Step 2):

first give each test T _i (1 ≦ i ≦ N) assigning the optimal test channel (TAM) width w _{i_op} (w _{i_op} ≤W _max ) Thereby minimizing testing time. If a certain PTS _j In each test T _i (T _i ∈PTS _j ) The sum of the assigned test channels (TAM) is greater than W _max Decreasing at PTS at this time _j The test channel (TAM) width of the test T with the shortest test time is reduced by one every time the TAM is detected, and such operations are repeated until PTS _j In each test T _i (T _i ∈PTS _j ) The sum of the assigned test channels (TAM) is less than or equal to W _max 。

Third Step (Step 3) and fourth Step (Step 4):

for each test T _i According to test time t _i Sorting in descending order, placing in set TS, packing one by one, each time testing T _i Packing is carried out and then T is put _i And deleted from the TS. And update T _i State of (2) and state of session. When to T _i When Packing is carried out, whether each session can accommodate T or not is checked firstly _i . If there are multiple sessions, T can be accommodated _i The one with the smallest time span is selected if no single session can accommodate T _i Then see if there are consecutive sessions that can accommodate T _i If there are also multiple choices, then pick the one with the smallest time span; if neither case is satisfied, then T is applied _i After the last session. As shown in FIG. 3 as T ₃ Can go to sessionS ₃ Or sessionS ₄ But due to sessionS ₃ Is less than S ₄ Then T ₃ Is put to sessionS ₃ 。

Step 5 (Step 5) and Step 6 (Step 6):

put one T at a time _i The state of session and T are updated afterwards _i The state of (c). As shown in fig. 3, there are foursessions are S respectively ₁ 、S ₂ 、S ₃ 、S ₄ The end time of each session and a certain T _i Corresponds to the end time of (2), and the start time of each session is also associated with a certain T _i Corresponds to the start time of (c). A test T _i There may be only one session, such as T ₄ Or T ₅ There may also be multiple sessions such as T ₁ Or T ₂ . While only one test, such as S, may be performed in a session ₃ 、S ₄ It is also possible to perform multiple tests such as S ₁ 、S ₂ The test channel (TAM) width of each session must be less than or equal to W _max 。

(i)T _i Is in a state of T _ status ₁ ＝{t ₀ ，t ₁ ，w _i Se } is represented by ₀ Represents T _i Starting time, t ₁ Represents T _i End time, w _i Represents T _i Allocated TAM width, se denotes T _i Which sessions are divided. As shown by T in FIG. 3 ₁ Is T _ status ₁ ＝{t ₀ ＝0，t ₁ ＝1600，w ₁ ＝8，se＝{S ₁ ，S ₂ ，S ₃ }}。

(ii)session _i Is in a state of S _ status ₁ ＝{t ₀ ，t ₁ Test, TAM _ avail } where t is ₀ Indicating session _i Starting time, t ₁ Indicating session _i End time, test represents session _i Which tests T are included, TAM _ avail indicates session _i There are also how many TAMs that are not used. As shown by S in FIG. 3 ₄ Is S _ status ₄ ＝{t ₀ ＝1600，t ₁ ＝2400， test＝{T ₃ }，TAM_avail＝8}。

Step 8 (Step 8):

after the previous 7 steps, an initial test strategy is obtained, which is further globally optimized as shown in fig. 4 (a), by increasing the width of the test channel (TAM) for the test T that determines the whole SOC test time, thereby reducing the whole SOC test time by reducing the test time of the test T, and ensuring that the TAM width of each session cannot exceed w when increasing the TAM width for the test T _max This operation is repeated until the test time of the SOC cannot be reduced. For example, T in FIG. 4 ₅ And T ₁ Directly determines the test time of the whole SOC, firstly considering T ₅ Increase the width of TAM when T ₅ When the TAM width of the T can not be increased, the T is increased ₁ Due to sessionS ₁ Has run out of TAM, therefore T ₁ The TAM width of (a) cannot be increased any more.

Pseudo code of PTS-oriented Bin-Packing construction and combination of global optimization process is as follows:

PTS Oriented Bin-Packing Procedure

Step 1：Assign the most optimal TAM width to every test T _i _(1≤i≤N)；

Step 2：Check every PTS such that the total TAM width of a PTS do not exceed W _max ；

Step 3：Sort every test T _i (1≤i≤N)in TS (TS＝{…T…})in descending order of

test time；

Step 4：Schedule the first test T _i in TS and then remove it from TS；

Step 5：Update test T _i (1≤i≤N)status；

Step 6：Update session status；

Step 7：If TS≠φthen go to step 4；

Step 8：Increase the TAM widths of the tests which dominate the total SOC test

time；

results and analysis of the experiments

The invention will be used for ITC02benchmark SOC ^[4] : h953 D695, f2126, q12710 as test cases. FIG. 2 shows the results of d695 test cases, the results being the total test time in clock cycles, and the results are compared with the document [5 ]]The experimental results of (a) were compared. Wherein the same reference is adopted [5 ]]The same constraint, i.e. the constraint that only the test power consumption is considered. In table 2, the "W" column indicates a test channel width (TAM); the "lower limit" column represents the lower limit of the test time; "[5]Results "column represents document [5 ]]The experimental results in (1); the "results herein" list indicates the experimental results of the present invention; the "improved" column indicates the results herein versus document [5 ]]The time of the results improves. As can be seen from the attached Table 2, in the same constraint barThe results of the present invention are improved to different degrees under different test channels (TAM) because the Bin-Packing algorithm of the present invention is globally optimized after obtaining an initial result by a construction method (see the pseudo code step 8), and the document [5 ]]There is not a global optimization process.

The attached table 3 is a test result of the test cases h953, d695, f2126 and q12710, the attached table 3 has two parts, the first part only considers the constraint of power consumption, and the second part considers the constraint of Hot-Spot, uniform heat distribution and power consumption; the "SOC" column represents a test case; "W" column indicates the width of the test channel; "t" s _max "column indicates the highest temperature during the test;

the column indicates the average temperature of the test procedure; "Δ (%)" column is the percentage of change in experimental results under different constraints. For example, in attached Table 3, for test case h ₉₅₃ When the width of the test channel is 16 and only the power consumption constraint is considered, the experimental result t _max ＝6248、

When constraints of Hot-Spot, uniform heat distribution and power consumption are considered, the experimental result t _max ＝5995、

Thus the maximum temperature t _max Δ (%) = (5995-6248)/6248 = -4.0%, average temperature

Δ (%) = (2168-1593)/2168 = -26.5%. Therefore, after hot spot avoidance and uniform heat distribution are considered, the maximum temperature and the average temperature in the testing process are greatly reduced, and the problem of heating caused by strong testing power consumption in the chip testing process is effectively solved.

ΔT ₁₁	ΔT ₁₂	ΔT ₁₃	ΔT ₁₄	ΔT ₁₅
ΔT ₁₁	ΔT ₁₂	ΔT ₁₃	ΔT ₁₄	ΔT ₁₅	ΔT ₂₁	ΔT ₂₂	ΔT ₂₃	ΔT ₂₄	ΔT ₂₅
ΔT ₃₁	ΔT ₃₂	ΔT ₃₃	ΔT ₃₄	ΔT ₃₅	ΔT ₂₁	ΔT ₂₂	ΔT ₂₃	ΔT ₂₄	ΔT ₂₅
ΔT ₃₁	ΔT ₃₂	ΔT ₃₃	ΔT ₃₄	ΔT ₃₅	ΔT ₄₁	ΔT ₄₂	ΔT ₄₃	ΔT ₄₄	ΔT ₄₅
ΔT ₅₁	ΔT ₅₂	ΔT ₅₃	ΔT ₅₄	ΔT ₅₅	ΔT ₄₁	ΔT ₄₂	ΔT ₄₃	ΔT ₄₄	ΔT ₄₅

Table 1: SOC test thermometer (example)

SOC	W	Lower limit of	[5]Results	Results herein	Improvements in or relating to
SOC	W	Lower limit of	[5]Results	Results herein	Improvements in or relating to	d695	16	39437	47574	43457	4117
24	26289	--	31139	--			16	39437	47574	43457	4117
24	26289	--	31139	--	32		23670	29039	25968	3071
40	20439	--	20549	--	32		23670	29039	25968	3071
40	20439	--	20549	--	48		15698	28441	15698	12743
56	14660	--	14780	--	48		15698	28441	15698	12743
56	14660	--	14780	--	64		13228	20004	13420	6584
Table 2 shows a comparison of the test results of the test case d695							13228	20004	13420	6584

Reference to the literature

[1]Yi-Kan Cheng and Sung-Mo Kang.An Efficient Method for Hot-spot Identification in ULSI Circuits[A].In：Proceedings of the IEEE International Conference on Computer-Aided Design，San Jose，CA，USA，1999.124~127.

[2]G.L.Craig，C.R.Kime.and K.K.Saluja.Test Scheduling and Control for VLSI Built-in Self-Test[J].IEEE Transactions on Computers，1988，3(9)：1099~1109.

[3]M.C.Golumbic.Algorithmic Graph Theory and Perfect Graphs[M].New York： Academic Press，1980.

[4]E.J.Marinissen，V.Iyengar and K.Chakrabarty.ITC 2002SOC test benchmark initiative[OL].http://www.extra.research.philips.com/itc02socbenchm，2000.

[5]V.Iyengar，K.Chakrabarty，and E.J.Marinissen.Integrated wrapper/TAM co-optimization，constraint-driven test scheduling，and tester data volume reduction for SOCs[A].In：Proceedings of the Design Automation Conference，New Orleans，LA，USA，2002.673~678.

Claims

1. A system-on-chip testing method capable of avoiding hot spots and uniformly distributing heat is characterized by comprising the following specific steps:

(1) Establishing a system-on-chip SOC test temperature-rising table by using a heat diffusion formula to describe Core in the system-on-chip SOC test _i The temperature rise value of (1), the temperature rise table comprising a nuclear Core _i Core with self-power-consumption induced temperature rise and other simultaneous tests _j Two parts of temperature rise caused by the power consumption of (1), wherein j is not equal to i;

(2) Establishing a standard for uniformly distributing heat: testing is performed when the nuclear cores that are spatially adjacent to each other are not simultaneously in space, where the spatial distances are Manhattan distances, d _allow A constant defined for the user, d _ij ＝|x _i -x _j |+|y _i -y _j I is two nuclear Core _i And Core of nucleus _j Manhattan distance between (x) _i ，y _i ) Is Core of nucleus _i (x) of (a) _j ，y _j ) Is Core of nucleus _j If d is the center coordinate of _ij ＜d _allow Core of nuclear _i And Core of nucleus _j Simultaneous testing is not allowed;

(3) Constructing a test compatibility graph: g _t ＝(V _t ，E _t ) Wherein V is _t For a set of nodes, each node represents a test T _i ， E _t The method is a set of connecting lines of two nodes, and the connecting lines on every two nodes indicate that two tests can be simultaneously carried out;

(4) Extracting a parallel test set PTS: extracting a parallel test set from the test compatibility graph according to the criteria (ii) and (iii);

(5) And (3) carrying out test planning: the method comprises a box placing Bin-Packing structure facing the parallel test set PTS and global optimization, and the test time is shortened to the maximum extent.

Wherein the criterion (ii) is the respective Core at any time _i All temperature rises above are less than Δ T _max Criterion (iii) is arbitraryThe total power consumed by the test is less than the maximum allowable test power P _max 。

2. The test method of claim 1, wherein the heat diffusion formula is

ΔT＝P×F(x，y，t)……(1)

Wherein, X is the distance from the observation point to the heating source along the X-axis direction, and Y is the distance from the observation point to the heating source along the Y-axis direction; Δ T represents a temperature rise value after a time T from an observation point where the manhattan distance from the heat source is x + y, P is power consumed by the heat source, and F (x, y, T) is a diffusion factor of heat;

core of nucleus _i The temperature rise caused by the power consumption is as follows:

ΔT _ii ＝P _i ×F(0，0，t _i )

wherein P is _i Is Core of nucleus _i The maximum power consumed by the test procedure of (1), t _i For testing nuclear Core _i The required time, x =0 and y =0, indicates that the observation point is at the heat generation source;

other Core cores _j Temperature rise due to power consumption of the simultaneous test of i ≠ j: sigma _j ΔT _ji Wherein, Δ T _ji ＝P _j ×F(X _ji ，Y _ji ，t _ji )，P _j Is Core of nucleus _j Maximum power, X, consumed during the test _ji Is Core of nucleus _j To Core _i Distance in X-axis direction of heat source, Y _ji Core of nucleus _j To the nucleus Core _i Distance in Y-axis direction of heat source, t _ji Is Core of nucleus _j And Core of nucleus _i Time of simultaneous testing, wherein t _ji ＝|t _j -t _i |。

3. The test method according to claim 2, wherein the step of constructing the test compatibility map is as follows:

(1) Firstly, establishing an initial test compatibility graph TCG without any constraint condition, wherein the test compatibility graph TCG at the moment is a complete graph;

(2) According to criterion (i): in the testing process, heat is uniformly distributed on the SOC surface of the system level chip, core cores which are adjacent to each other in spatial position cannot be tested simultaneously, and a connecting line does not exist between the Core cores and the TCG in the TCG to obtain another TCG;

(3) According to criterion (ii), when two cores are tested simultaneously, their respective temperature increases are both less than Δ T _max According to criterion (iii): when two cores are tested simultaneously, the total power of the two cores is less than P _max And obtaining a new test compatibility chart TCG.

4. The testing method according to claim 3, characterized in that said step of extracting parallel test sets PTS is as follows: extracting complete subgraphs from the obtained test compatibility graph TCG and constructing a corresponding test set; for a test set composed of complete subgraphs, the test set composed of two elements is a parallel test set PTS; for test sets of more than 2 elements, determining whether criteria (ii) and (iii) are met, and if so, determining a parallel test set PTS; if not, each proper subset of one less of its elements is checked and such operations are repeated until a test set is obtained that satisfies criterion (ii) and criterion (iii), which is the parallel test set PTS.

5. The testing method according to claim 4, wherein the boxed sub Bin-Packing construction and global optimization for the parallel test set PTS comprises the following steps:

(1) First give each test T _i I is more than or equal to 1 and less than or equal to N, and the optimal test channel width w is distributed _{i_op} ，w _{i_op} ≤W _max Thereby minimizing testing time; if a parallel test set PTS _j In each test T _i ，T _i ∈PTS _j The sum of the assigned test channels is greater than W _max At this time, the PTS in the parallel test set is reduced _j The test channel width of the test T with the shortest test time is reduced by one per test channel TAM and such operations are repeated until the parallel test set PTS _j In each test T _i The sum of the allocated test channels TAM is less than or equal to W _max ；

(2) For each test T _i According to test time t _i Arranging in descending order, placing in a set TS, and placing Packing one by one, each time for a test T _i After Packing is carried out, T is put _i Delete from TS and update T _i And the state of the paragraph session; when for T _i When Packing is carried out, whether each paragraph session can contain T or not is checked firstly _i (ii) a If there are multiple paragraphs that can accommodate T _i The one with the smallest time span is selected if there is no single oneParagraph session can accommodate T _i Then see if there are consecutive paragraph sessions that can accommodate T _i If there are multiple choices, then choose the one with the smallest time span; if neither case is satisfied, then T is applied _i Put after the last paragraph session;

(3) Each time put a T _i Then, the state of the session and T are updated _i The state of (1);

(i)T _i is in a state of T _ status _i ＝{t ₀ ，t ₁ ，w _i Se } is represented by ₀ Represents T _i Starting time, t ₁ Represents T _i End time, w _i Represents T _i The width of the assigned test channel TAM, se denotes T _i Which paragraphs session are divided;

(ii) Paragraph session _i Is in S _ status _i ＝{t ₀ ，t ₁ Test, TAM _ avail } where t is ₀ Represents a paragraph session _i Starting time, t ₁ Represents a paragraph session _i End time, test denotes the paragraph session _i Which tests T are included, TAM _ avail denotes the paragraph session _i How many unused test channels TAM remain;

(4) Increasing the width of the test channel TAM for the test T determining the test time of the whole SOC, thereby reducing the test time of the whole SOC, and ensuring that the width of the test channel TAM of each session cannot exceed W when the width of the test channel TAM is increased for the test T _max This operation is repeated until the test time of the system on chip SOC cannot be reduced.