CN100356362C - Signal transmission system - Google Patents

Abstract

A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.

Description

Signal transmitting apparatus

The application is that application number is 200410032115.5, the applying date is on June 6th, 1997, denomination of invention is divided an application for the application of " signal transmitting apparatus ".

Technical field

The present invention relates to be installed in the signal transmission technology between the parts (integrated circuit is its representative components) in the devices such as workstation or personal computer, relate in particular to the effective technology in the high speed transmission of signals.

Background technology

Fig. 3 illustrates 1 example of the memory circuitry that is using in current workstation or the personal computer.

The 30th, be installed on the memory module of a plurality of storer LSI31, the 32nd, Memory Controller is used for storage LSI31 is controlled, and sends to storer LSI31 and to write data, receive sense data etc. from storer LSI31.

In addition, in Memory Controller 32, often adopt integrated circuit, as the control section of storer LSI31, send write data division and receive the sense data part with assert that herein storer LSI is a clock synchronized memory device.For example can adopt SD.RAM (Shhchronous Dyuamic Random Access Memory-Synchronous Dynamic Random Access Memory) as clock synchronized memory device.

This Memory Controller is installed on the motherboard 33, and memory module 30 is installed on the motherboard by connector 34.

Among Fig. 3, the piece number of the memory module of being installed on motherboard is 8, but module piece number can decide piece number commonly used according to purpose of scale, specification or the user of system etc.

The ball bearing made using motion of this memory circuitry is for described down.From the control signal of Memory Controller output with write signal wiring 35 on the data-signal flat board of usefulness, be transferred to the storer LSI31 on each module through contact 36, the distribution 37 on the memory module on connector 34, the memory module.In addition, when data are read, by being input to Memory Controller 32 from the distribution 35 on the distribution on the module of storer LSI31 37, contact 36, connector 34, the motherboard.

Such distribution 35 is called memory bus.In many memory buss in Fig. 3, only illustrate one.

In addition, in SDRAM, except that above-mentioned control signal, data-signal, also provide clock signal, but in Fig. 3, the distribution that clock is used is not shown.The distribution that clock is used directly or according to frequency division or distribution mode distributes the storer LSI in being located at Memory Controller and memory module from signal source.

In such storage system, wait in the signal transmission line between the integrated circuit components single phase clock system mode that the employing trigger that has is used.

For example be described in detail in the 356th page-360 pages in " VLSI system design circuit and installation basis " (ball is kind publishes, put down into 7 years) about this technology.

It shown in Fig. 2 the simplest example of single phase clock mode.Output circuit shown in Figure 2 is the transmission circuit that was connected by 1: 1 with input circuit.Among the figure, trigger circuit 24 and output circuit 26 are arranged in circuit block 21, in circuit block 22, input circuit 27 and trigger circuit 25 are arranged in addition.The 23rd, the signal that is used for exporting from circuit block frame 21 is sent to the transmission line of circuit square frame 22.

In trigger circuit 24,25, from the direct clock of signal source of clock input or the clock of handling through over-allocation, frequency division.In addition, the input signal of trigger circuit 24 is not shown in Fig. 2, but produces in that circuit block 21 is inner, and in addition, the output of trigger circuit 25 also is input among other circuit in the circuit block 25 usually.

In addition, in the above description, suppose that the input signal of trigger circuit 24 produces in circuit block 21, produce and be directly inputted to situation in the trigger circuit but also have in other circuit block.Equally, the output of trigger circuit 25 also is not limited to the input circuit in the circuit block 22.Sometimes also directly or by distribution link in other circuit block.

The basic functional principle of the circuit shown in Fig. 2 is as follows.

In trigger circuit 24,25, provide clock.Trigger circuit 24 make in the clock latched data of last one-period and the clock synchronization line output of going forward side by side, and with the importation of this data transmission to output circuit 26, from output these data are outputed to transmission line 23.The data of transmitting on transmission line via input circuit 27, are transferred to the data input unit of trigger 25, with the mode of clock synchronization under with this data latching.

If the single phase clock system, the clock that is input to each trigger is designed to make their phase place consistent with each other.The method that extensively adopts in the technology that makes the phase place unanimity is: by signal source of clock or from the signal wiring length unanimity to the clock importation of each circuit block of distribute end or frequency division side, or make the volume load unanimity of the distribution of this clock signal, or make the distribution time-delay consistent.

In this single phase clock system, the technology that is widely used in the method for effectively transmitted signal is: will receive an end and latch this transmission method of signal in the next cycle in cycle of output signal.In this mode, cycle length t _CycleMust satisfy following formula.

t _cycle＞t _delay(max)+t _pd(max)+t _setup(max)+t _skew(max)

Herein, t _{Delay (max)}Be the timer access time of circuit block 21, that is, from clock be imported into circuit block 21 to data from circuit block 21 output times, t _{Pd (max)}Be to the travel-time that is input to before the circuit block 22, t from the signal of circuit block 21 output _{Setup (max)}Be the Time Created of circuit block 22, that is, before the clock that is input to circuit block 22, must determine to be input to the time of the logical value (height, or low) of the signal of circuit block 22, last, t _SkewIt is the deviation between the clock that is input to respectively in the circuit block 21,22.

(max) that is annotated in the formula means the temperature with separately, the maximal value separately that the deviation of process etc. is taken into account.

In the memory circuitry shown here, when the connection distribution between the circuit block (herein being Memory Controller and memory module) was long, above-mentioned travel-time tpd kept big value.For example, be 400mil (about 1cm) when making the connector spacing, when memory module was 16, tpd was 3-4ns.

Suppose that tpd (max) is 4ns, when periodicity is 33MZ, be no more than about 1,, may satisfy by the high speed of circuit block for the ratio of the tpd of this cycle 30ns

t _cycle＞t _delay(max)+t _pd(max)+t _setup(max)+t _skew(max)

But for example, if periodicity is increased to 250MHZ, then this cycle becomes and t _{Pd (max)}No matter how identical 4ns manages to make the circuit block high speed, can not realize this system.Though be less than the degree of 250MHZ, because the influence that the microminiaturization of equipment etc. produce becomes big, in fact, the periodicity about 100MHZ, t _{Delay (max)}, t _{Setup (max)}, t _{Skew (max)}High speed also become

t _cycle＞t _delay(max)+t _pd(max)+t _setup(max)+t _skew(max)

Relation, if surpass the high speed of this periodicity, be impossible in design.

In addition, when how research realizes high speed, except that delay as described above is calculated, study the method for guaranteeing window in addition.When time-delay is calculated, for discuss can be under the consistent state of the clock phase that makes output circuit and input circuit carry out the signal transmission, when window was taken into account, by the deviation adjustment is added on the clock phase, just making more, high speed became possibility.

So-called the deviation adjustment be added to clock phase be meant, for example, when Fig. 3, with the clock of supplying with Memory Controller relatively, or early or stagger late and supply with the clock phase of memory module.

For example, when comparing the former the time delay when writing fashionable time delay and reading than morning, if the method for above-mentioned time delay, consistent and the decision cycle for the time delay when reading, and when window taken into account, supply with the clock phase of storer LSI by staggering in advance, just can export sense data in advance, the result, in Memory Controller, therefore the clock synchronization that just makes storer LSI regularly and the time delay of the clock synchronization of the next cycle of Memory Controller before regularly, can guarantee the time of the time delay when reading sometimes.That is, guarantee window during the time, replace following formula, use window time t in discussion _Window, i.e. t _Window=t _Cycle+ tOH-t _{Delay (max)}Design.

TOH is called the data output holding time, is after next clock being input to the output circuit piece that carries out signal output, and output is converted to the time before (its cycle) data.This time is and t _{Delay (min)}, i.e. t _DelayMinimum value consistent or greater than time of this minimum value.

With the t that tries to achieve like this _WindowValue be the basis, satisfy following formula and get final product.

t _window＞t _pd(max-min)+t _setup(max)+t _hold(max)

Herein, so-called t _{Pd (max-min)}, be t _PdMaximal value and minimum value poor, under the situation of Fig. 3, so-called maximal value is meant the most long-range module seen from the Memory Controller angle and the travel-time between the Memory Controller, and so-called minimum value is meant the module of short range and the travel-time between the Memory Controller.That is so-called t, _{Delay (max)}Be that expression is because the different amount of travel-time that the position of memory module produces.

To the discussion of carrying out this window time time delay that writes and read to the data of memory module respectively, simultaneously if satisfy

t _window＞t _pd(max-min)+t _setup(max)+t _hold(max)

Afterwards, also can set the deviate of clock phase, so that can be separately time width t _Window-t _{Pd (max-min)}In guarantee Time Created and retention time.

By this method, can seek several high speeds, still, if device size for example in memory circuitry shown in Figure 3, the piece number of installed module becomes for a long time, t _{Pd (max-min)}Value can not ignore, so high speed still become the difficulty.

Promptly, the transmission of image height speed is desired like that, the influence that difference produced by the signal propagation time of the memory module from the Memory Controller to the short range and the signal propagation time from Memory Controller to long-range memory module becomes big, and difficulty takes place in the high speed design of storage system.

Same problem does not depend on storage system, be and clock synchronization and the problem that between the transmission circuit that carries out signal, causes, for example, even also same problem can take place for the processor bus in the multiprocessing system that has used many microprocessor.

Summary of the invention

The invention reside in, with clock signal synchronously and carry out addressing these problems in the system of signal transmitting and receiving.

The objective of the invention is to, provide to reduce and send out the signal transmitting apparatus of receiving imbalance because the signal propagation time between the circuit postpones caused signal.

Other purpose of the present invention can be understood from following detailed description.

For achieving the above object, the invention provides a kind of signal transmitting apparatus, with distribution the 1st circuit block and a plurality of the 2nd circuit block are coupled together, wherein, the 1st circuit block possesses the 1st output circuit of output the 1st data-signal, the 1st receiving circuit of reception the 2nd data-signal, the 2nd circuit block possesses the 2nd receiving circuit that receives above-mentioned the 1st data-signal, the 2nd output circuit of above-mentioned the 2nd data-signal of output, and it is characterized in that comprising: above-mentioned the 1st circuit block also possesses: the 3rd output circuit of clock signal; Receive the 3rd receiving circuit of above-mentioned clock signal, above-mentioned the 2nd circuit block also possesses: the 4th receiving circuit that receives above-mentioned clock signal, above-mentioned the 2nd receiving circuit synchronously latchs above-mentioned the 1st data-signal with the above-mentioned clock signal that is received by above-mentioned the 4th receiving circuit, above-mentioned the 2nd output circuit is synchronously exported above-mentioned the 2nd data-signal with the above-mentioned clock signal that is received by above-mentioned the 4th receiving circuit, above-mentioned the 1st receiving circuit synchronously latchs above-mentioned the 2nd data-signal with the above-mentioned clock signal that is received by above-mentioned the 3rd receiving circuit, above-mentioned distribution is connected up, make above-mentioned the 1st circuit block and above-mentioned a plurality of the 2nd circuit block are connected in series, and seeing the 2nd nearest circuit block than seeing from above-mentioned the 1st circuit block to turn back and turn back to from above-mentioned the 1st circuit block in farthest the farther position of the 2nd circuit block, between any one of above-mentioned the 1st circuit block and above-mentioned a plurality of the 2nd circuit blocks, above-mentioned the 1st circuit block is connected with above-mentioned distribution with above-mentioned a plurality of the 2nd circuit blocks, the transmission time of feasible above-mentioned the 1st data-signal and the transmission time of above-mentioned the 2nd data-signal and certain from above-mentioned the 2nd circuit block to above-mentioned the 1st circuit block from above-mentioned the 1st circuit block to above-mentioned the 2nd circuit block.

In addition, at the clock output circuit of having purchased clock signal, export the 1st circuit of the 1st signal, receive a plurality of the 2nd circuit of described the 1st signal, dispose and install the substrate of these a plurality of the 2nd circuit, transmit the 1st distribution of described clock signal, and transmit from described the 1st circuit to the signal transmitting apparatus of the 2nd distribution of the signal of described the 2nd circuit, make described the 1st distribution from described clock output circuit distribution, and be connected in series with described a plurality of the 2nd circuit, described the 2nd distribution is from described the 1st circuit layout, parallel-series is connected to described a plurality of memory module, makes the described the 1st then, the 2nd distribution is connected with described the 2nd circuit.

By doing like this, clock signal arrives the distance of any the 2nd circuit and arrives the relativeness of the distance of its 2nd circuit from the 1st signal of the 1st circuit output.No matter roughly the same distance how, can both be stipulated in the installation site of the 2nd circuit, synchronous and when latching the 1st signal in the 2nd circuit and clock signal, can suppress the influence in the propagation delay time between the circuit of the 1st signal.

In addition, described the 1st, the 2nd distribution is designed to respectively, turning back with position far away from described the 1st circuit described the 2nd circuit farthest, get back to from nearest described the 2nd circuit of described the 1st circuit, by described the 2nd a circuit part be connected described the 1st distribution and described the 2nd distribution folded back position before, remaining described the 2nd circuit just can reduce load density after being connected the described folded back position time of the described the 1st and the 2nd distribution.

Again at the clock output circuit of having purchased clock signal, export the 1st signal, receive the 1st circuit of the 2nd signal, receive described the 1st signal, export a plurality of the 2nd circuit of described the 2nd signal, dispose and install the substrate of these a plurality of the 2nd circuit, transmit the 1st distribution of described clock signal, from 2nd distribution of described the 1st circuit to described the 2nd circuit transmissioning signal, and from described the 2nd circuit to the signal transmitting apparatus of the 3rd distribution of described the 1st circuit transmissioning signal, described the 1st distribution from described clock circuit by distribution, and be connected in series with described a plurality of the 2nd circuit, the described the 2nd, the 3rd distribution from described the 1st circuit by distribution, parallel-series is connected to described a plurality of memory module, described the 2nd distribution is designed to, turning back with position far away from described the 1st circuit the 2nd circuit farthest, return up to from nearest described the 2nd circuit of described the 1st circuit, the described the 1st, the 3rd distribution is designed to respectively so that turning back with position far away from described the 1st circuit described the 2nd circuit farthest, arrival is returned up to from later described the 1st circuit of nearest described the 2nd circuit of described the 1st circuit, in described the 1st distribution and described the 2nd distribution, the part of described the 2nd circuit was connected before the folded back position of described the 1st distribution and described the 2nd distribution, remaining described the 2nd circuit is connected after the described folded back position of the described the 1st and the 2nd distribution, in described the 3rd distribution, about connecting described the 1st distribution and described a part of the 2nd circuit before the folded back position of the 1st distribution, be connected after the folded back position of described the 3rd distribution, be connected before the folded back position of described the 3rd distribution about described remaining the 2nd circuit.

By doing like this, clock signal arrives the distance of any the 2nd circuit and arrives the relativeness of the distance of its 2nd circuit from the 1st signal of the 1st circuit output, and the clock signal of the 2nd circuit and clock signal when the 2nd signal of output arrives distance before the 1st circuit and the 2nd circuit and exports the 2nd signal synchronously arrives the relativeness of the distance before the 1st circuit, no matter the installation site of the 2nd circuit how, can both stipulate approximately identical distance, in the 2nd circuit and clock signal synchronously and when latching the 1st signal, and the 1st circuit when latching the 2nd signal, can suppress the 1st, the influence in the propagation delay time between the circuit of the 2nd signal.

In addition, suppose such structure, and also can accomplish when memory module one side output data, output is used for receiving at Memory Controller one side joint the timing signal of data, this structure has the 1st output circuit of output the 1st signal, export the 2nd output circuit of the 2nd signal, receive the 1st receiving circuit of the 3rd signal, the 1st circuit block with the 2nd receiving circuit that receives the 4th signal, and have the 3rd receiving circuit that receives described the 1st signal and be used to the 3rd output circuit that receives the 4th receiving circuit of described the 2nd signal and export the 3rd signal and a plurality of the 2nd circuit blocks of exporting the 4th output circuit of the 4th signal, make described the 1st signal of transmission between described the 1st circuit block and described the 2nd circuit block respectively, described the 2nd signal, the 1st distribution of described the 3rd signal and described the 4th signal, the 2nd distribution, the 3rd distribution and the 4th distribution are from the 1st circuit the 2nd circuit block position farthest, or turn back in the position more farther than described position and layout, about described the 1st signal and described the 3rd signal, the part of described the 2nd circuit block is connected from described the 1st circuit block to the distribution of described folded back position, remaining described the 2nd circuit block is connected than on the more preceding distribution of the described point (position) that turns back, for described the 2nd signal and described the 4th signal, when the 1st signal is connected from the distribution of described the 1st circuit block before described folded back position, described the 2nd circuit block is connected on the distribution than the described front more turned back a little, other described the 2nd circuit block is connected from described the 1st circuit block to the distribution of described folded back position, the 2nd receiving circuit and the 3rd signal Synchronization also latch the 4th signal, and the 4th receiving circuit and the 1st signal Synchronization and latch the 4th signal.

Description of drawings

Fig. 1 represents about the annexation of the Memory Controller of the application examples of the 1st embodiment of the present invention and memory module and distribution model.

Fig. 2 represents the signal transmitting apparatus of existing single phase clock system mode.

Fig. 3 represents the mounting structure and the circuit of existing storage system.

Fig. 4 represents about the annexation of the Memory Controller of the 1st embodiment of the present invention and memory module and distribution model.

Fig. 5 represents about the annexation of the Memory Controller of the 2nd embodiment of the present invention and memory module and distribution model.When making the present invention be applicable to input and output common type circuit, be illustrated in when reading and write the fashionable reverse example of direction that makes clock signal.

Fig. 6 represents the Memory Controller of application examples of the present invention the 1st embodiment and the annexation and the distribution model of memory module.

Fig. 7, Fig. 8 represent about the annexation of the Memory Controller of the application examples of the 2nd embodiment of the present invention and memory module and distribution model.

Fig. 9 represents the Memory Controller of relevant the present invention the 3rd embodiment and the annexation and the distribution model of memory module.Expression is applicable to the example of unidirectional signal transmission.

Figure 10, Figure 11 represent the Memory Controller of application examples of relevant the present invention the 3rd embodiment and the annexation and the distribution model of memory module.

Figure 12 represents the Memory Controller of the present invention the 4th embodiment and the annexation and the distribution model of memory module.

Mounting structure when Figure 13, Figure 14, Figure 15, Figure 16 represent to make the present invention be applicable to storage system.

Figure 17 represents the frame assumption diagram of information handling system.

Figure 18 represents the profile of memory module.

Figure 19 represents the data-signal distribution on the memory module.

Figure 20 represents the address control clock signal distribution on the memory module.

Figure 21 represents the SDRAM circuit of the input and output divergence type on the memory module.

Signal when Figure 22 represents to insert buffer circuit on the address control clock signal distribution on the memory module connects.

Signal when Figure 23 represents to insert resistance on the data-signal distribution on the memory module connects.

Signal when Figure 24 represents to insert resistance on the address control clock signal distribution on the memory module connects.Figure 25 is with the address on the buffer circuit resistance insertion memory module.Signal in the time of on the control clock signal distribution connects.Figure 26 represents the SDRAM circuit of the input and output common type on the memory module.Figure 27 is illustrated in the address control clock signal input circuit of the SDRAM on the memory module.

Figure 28 represents that the PLL circuit is in the clock output circuit of the Memory Controller of Memory Controller inside.Figure 29 represents that the PLL circuit is in the clock output circuit of the Memory Controller of Memory Controller outside.Figure 30 represents that the PLL circuit is in the clock input circuit of the Memory Controller of Memory Controller inside.Figure 31 represents that the PLL circuit is in the clock input circuit of the Memory Controller of Memory Controller outside.Figure 32 represents that the PLL circuit is positioned at the Memory Controller of the input and output common type of Memory Controller inside.Figure 33 represents that the PLL circuit is positioned at the Memory Controller of the input and output common type of Memory Controller outside.Figure 34 represents to have the clock input in the memory module of PLL circuit.

Figure 35 represents to possess again the Memory Controller of timing circuit.

Figure 36 A has represented to use the storage system of the present invention of timing circuit more of the present invention.

Figure 36 B is the expander graphs of a PLL circuit with frequency dividing circuit shown in X in Figure 36 A.

Figure 37 represents the present invention the 5th embodiment.

Figure 37 B shows the inner or outside PLL circuit with frequency dividing circuit at Memory Controller.

Figure 38 represents that the PLL circuit is positioned at the clock output circuit of Memory Controller of the input and output divergence type of Memory Controller inside.Figure 39 represents that the PLL circuit is positioned at the clock output circuit of the Memory Controller of depositing the input and output divergence type of paying device controller outside.Figure 40 represents to have the clock input in the memory module of SDRAM of input and output divergence type.Figure 41 represents to have the clock input in the memory module of the SDRAM that inserts resistance and input and output divergence type.

Figure 42 represents to have the memory module of the SDRAM of the buffer circuit of register type and input and output common type.The memory module of Figure 43 represents to have low speed (Slow) type buffer circuit and input and output common type SDRAM circuit.Figure 44 represents to have the memory module of inserting resistance and low speed type buffer circuit and input and output common type SDRAM circuit.Figure 45 represents to have the memory module of inserting resistance and depositing the buffer circuit and the input and output common type SDRAM circuit of type.

Figure 46 represents the present invention the 6th embodiment.Figure 47 represents the variation of the present invention the 6th embodiment.The bus structure of representing unidirectional terminal.Figure 48 represents the variation of the 6th embodiment of the present invention.

Figure 49 represents the 7th embodiment of the present invention.Figure 50, Figure 51 represent the variation of the 4th embodiment.

Figure 52 represents timing circuit again.

Figure 53 represents to connect an embodiment of the memory module circuit of the 6th embodiment.

Figure 54 represents to connect an embodiment of the memory module circuit of the 7th embodiment.

Figure 55 represents the 8th embodiment of the present invention.

Embodiment

Below, use accompanying drawing to describe one embodiment of the present of invention in detail.

In the present embodiment, the memory bus with storage system is that example describes.As mentioned above, the present invention also is applicable to desired all laminar bus of high speed transmission of signals such as workstation or personal computer, signal wirings such as system bus promptly shown in Figure 17 (processor bus), memory bus, peripheral bus.Certainly also be not limited to storage system.

Now one embodiment of the present of invention (the 1st embodiment) are described.

About the drawing of present embodiment in respect of: the distribution of Memory Controller and memory module be connected aspect, see shown in Fig. 4, Fig. 6, Fig. 1, see Figure 28-31 and shown in Figure 35 aspect the detail of Memory Controller, seeing Figure 21, Figure 40, shown in Figure 41 aspect the detail of memory module.In addition, see Figure 13-16, Figure 18-20, Figure 22-shown in Figure 25 in the variation of the system of being installed.

At first, use Fig. 4 that the basic substrate distribution model of present embodiment and being connected of substrate distribution and connector mainly are described.

Output circuit 11,12 and input circuit 13,14 are arranged in Memory Controller 32.

Wherein, output circuit 11, input circuit 13 are circuit that clock signal is used, and in addition, output circuit 12, input circuit 14 are that circuit, the distribution 15 that data-signal is used is distributions of using for the clock of transfer clock, distribution 16 is distributions that data write usefulness, and distribution 17 is distributions that data are read usefulness.

34A-34F is a connector, the memory component that its connection had installed already etc., memory module described later etc.

Memory Controller 32 and distribution 15,16,17 and connector 34A-34F etc. be installed in Fig. 3 33 shown in substrate (motherboard) in.

Transmission line 15A when 15B, 16A, 17A are installed in Memory Controller 32 on the substrate (module) that is different from motherboard, is the distribution that is introduced in the module.In addition, even often introduce as required when Memory Controller is installed on the motherboard, but not necessarily need by the wire laying mode on the motherboard.

Connector 34A-34F is configured to be mounted to row as shown in Figure 3 on motherboard.Distribution 15-17 extends so that report to the leadship after accomplishing a task with connector 34A-34F respectively in turn from Memory Controller 32, turn back (revolution of U type) in the front that is positioned at from the connector of Memory Controller 32 position farthest, layout becomes to report to the leadship after accomplishing a task with connector 34A successively from connector 34F once more.In Fig. 4, the junction of distribution 15-17 and connector 34A-34F is represented with black circle (●).

The distribution 16 that distribution 15 and the data that clock is used write usefulness was connected with connector 34A-34C...34E before distribution folded back position separately respectively, was connected with connector 34F...34D-34B after folded back position.

The distribution 17 that data are read usefulness is connected with the distribution 16 opposite relations that data write usefulness with the distribution of using with clock 15.That is, before the position of turning back of distribution 17, be connected, after folded back position, be connected with 34E...34C-34A with connector 34-34D...34F.

By the mode of cross-over configuration, it is identical that distribution is born.

In Fig. 4, each data signal line 18 that line is represented clock cable 16 respectively, write the data signal line 17 of usefulness and read usefulness, but the different distribution of each bar as required also can be with different bar numbers, and this is the self-explantory fact.

Memory module 30 has been installed in connector 34A-34F.The example of from Figure 18 to Figure 27, representing memory module.In memory module 30, as shown in figure 18, a plurality of storer LSI are housed.Storer LSI it would be desirable the storer of clock synchronization type, for example SDRAM.SDRAM and clock (signal) are synchronous, are to be taken into control signal, address signal, perhaps write the storer of data, sense data.

In memory module 30, data line as shown in figure 19, the contact 36 of module and the lead-in wire of SDRAM are connected in 1: 1 ratio.The control signal address signal as shown in figure 20, the contact 36 of module and the lead-in wire of a plurality of SDRAM are connected.In Figure 20, show the example that signal is assigned to all SDRAM, but also run into the situation of distributing to a part that is positioned at the SDRAM on the module from 1 contact 36, for example run into that a plurality of CAS (column address strobe) signal is input to 1 situation in the module.

In addition, as shown in figure 22, these situations are arranged, that is, buffer circuit 61 is housed between contact 36 and SDRAM, and as shown in Figure 23 resistance is housed in data signal line, in the control signal address signal line, resistance is housed as shown in Figure 24; And 60 two kinds of assemblies of buffer circuit 61 and resistance are housed as shown in Figure 25.

The resistance of packing in Figure 23 etc. is to be used for handling the resistance that the impedance matching of distribution on the motherboard and the distribution on the memory module is used, and the spy of the former application of its details the applicant is willing to flat 5-334631 number (spy opens flat 7-202947 number), specially is willing to existing being described in detail in flat 7-26495 number (spy opens flat 7-283836 number) patent.

Notice 1 SDRAM in the above-mentioned memory module 30, and whole circuit that omits other circuit shown in Figure 21.The SDRAM of Figure 21 shows the type that input circuit separates with output circuit.The output circuit 52 that in SDRAM, comprises the input circuit 50 that is taken into clock, the input circuit 51 that is taken into data and output data.

Existing SDRAM is that the importation of input circuit and the output of output circuit become shared input and output type in LSI, to narrate in the back about this point, here the lead-in wire specification of the type that is separated with the output at the importation of LSI internal input circuit and output circuit is an example, below its principle of work is described simply.

SDRAM31 is taken into data by input circuit 50 and the clock synchronization that is taken in input circuit 51, or from output circuit 52 output datas, and carries out and write or sense data in the back synchronously with clock signal.

Usually in the storage system of present embodiment, above-mentioned memory module 30 realizes with all or part of form that is connected to connector 34.

Below, illustrate to the memory module 30 of the storage system of each connector that memory module shown in Figure 21 30 is connected to motherboard shown in Figure 4 and carry out the processing example that data write.

Storer control 32 writes the data and the clock signal of usefulness respectively from output circuit 12,11 outputs.Clock signal also can send when writing processing, also can do conventional output.

The clock signal that is output is transmitted on the distribution 15 that clock is used, and presses connector 34A, 34C ..., 34E, 34F ..., the sequential delivery of 34D, 34B is to each connector, turns back to Memory Controller again.Write data also with the distribution of using with the clock connector that is linked in sequence equally, therefore with same sequential delivery to each connector.

The SDRAM31 of memory module 30 that connects any connector 34 is synchronous with the clock signal that receives in input circuit 50, and is taken into data from the input circuit 51 of front.

Memory Controller is when sense data, and Memory Controller 32 sends and comprises clock signal and be used for the control signals such as address that data are read.Write equally with above-mentioned, receive by SDRAM from the control signal of Memory Controller 32 outputs.

The clock signal that SDRAM31 is received suitable data and input circuit 50 outputs to the distribution 17 that data are read usefulness synchronously and from output circuit 52.

The distribution 17 that data are read usefulness is connected with connector to write the opposite order of the data of usefulness with data.If the described memory module of supposition is connected to connector 34, then SDRAM31 make from the data of output circuit 52 output from connector 34A by with 34C..., 34E, 34F ... the tie point of the connector of 34D, 34B arrives Memory Controller.Clock signal during the SDRAM31 output data is utilized to data output synchronous at connector 34A.This clock signal is the same with the data of the distribution 17 of reading usefulness, from connector 34A through with 34C..., 34E, 34F ..., 34D, the tie point of 34B is got back to Memory Controller.

The distribution that Memory Controller 32 is used by the clock that is received in receiving circuit 13 and the clock signal of returning synchronously after, receiving circuit 14 is taken into the data of reading.

To can ignore for the delay time difference between the circuit of clock signal between the circuit and data-signal about equally from the distance of the position arrival Memory Controller 32 of memory module 30 from memory module 30 arrival Memory Controllers 32 and clock signal in sense data.

Like this, no matter the link position of memory module is how, clock signal and write data-signal and can both make the time (distance) that arrives any memory module unanimous on the whole.In addition, can make and arrive from memory module that sense data arrives and clock signal is unanimous on the whole from the time that this memory module turns back to Memory Controller.

Like this, no matter the position of memory module is how, data are write the fashionable travel-time and the travel-time sum when reading all is roughly steady state value, and in above-mentioned formula

t _window＞t _pd(max-min)+t _setup(max)+t _hold(max)

In, can reduce t _{Pd (max-min)}Value, guarantee the surplus of window.

That is, as previously mentioned, because time t _Window＞t _{Pd (max-min)}Elongated, therefore, can be easy to get time greater than the value of Time Created and retention time.

In addition, as shown in Figure 4, be exactly an example with the method for attachment that is connected alternately as the connector of the front and back of the folded back position of distribution of connector and distribution.

In clock distribution 15, if the part under will be from output circuit 11 (from Memory Controller farthest) to connector 34 is as " outlet part ", again will be from 34 times part conducts " loop feature " of connector to input circuit, equally in writing data wiring, part that also will be from output circuit to connector 34F is as " outlet part ", with remainder (promptly turning back to the part of memory module one side of the front that is positioned at the outlet part) as " returning part ", and, about the sense data distribution, will be from connector 34F to input circuit 14 part as " returning part ", remainder (promptly, part at the moment at returning part, part from connector 34A to connector 34F), then observes following rule and also can connect connector as " outlet part ".

(1) with " outlet part " when the clock distribution is connected to connector,

Write the distribution that data use and be connected with connector with " outlet part ",

The distribution that sense data is used carries out distribution with " returning part ".

When (2) the clock distribution being connected to connector with " loop feature ",

Write the distribution that data use and be connected with connector with " returning part ",

The distribution that sense data is used carries out distribution with " outlet part ".

Be further to improve precision, consider also can carry out after the following situation layout of distribution.

The distribution length of the distribution 15 of the input circuit 50 in (1) making from output circuit 11 to module is consistent with the distribution length of distribution 16 of input circuit 51 in from output circuit 12 to module, makes the distribution load consistent.

The distribution length of the distribution 16 of the input circuit 51 in (2) making from output circuit 12 to module between each module is consistent with the distribution length of 14 the distribution 17 from the output circuit in the module 52 to input circuit, makes the distribution load consistent.

Adopt the precision of above-mentioned way distribution length unanimity, the consistent precision of distribution load, just reaching increases t _Window-t _{Pd (max-min)}The effect of value.

In addition, as the means that make clock phase produce deviation following method is arranged, that is:

(1) is provided for producing in any distribution on distributing to the clock distribution of Memory Controller or memory module the circuit of propagation delay, for example the method for delay circuit.This circuit also can be arranged on all distributions, also can only be provided with in certain signal.

(2) the delay circuit function in (1) is remained on the post a letter method of source or distribution, frequency division source one side of clock.At this moment, also can be arranged to, so that can regulate this delay by outside lead.For this reason, just exist in these clock sources several delay circuits are installed, the method for they being selected from the outside, and, prepare a plurality of delay circuits, and in these circuit, specify the method for using several circuit etc. from the outside.

In addition, in the distribution of connected storage controller and connector, when clock signal and data-signal are connected to connector,, disperse and be connected to " outlet part " and " time part " (or returning part) better with " outlet part " with only be connected and compare with only with " loop feature " (or returning part).This is because the load that is connected to connector is disperseed, and can suppress the decline of impedance of the actual effect of signal wiring.

Have following several as the effect that suppresses this impedance decline.

(1) when the output of output circuit is converted, can suppress to be transferred to the decline of the signal amplitude of memory module at first.

Especially, when little amplitude signal, owing to the signal amplitude of impedance decline from the 1st waveform of output circuit output diminishes, the result, the noise margin of input signal diminishes, and produces misoperation sometimes and occurs, and the reason of this situation will prevent.

(2) can improve multiduty quality.

Just as memory module, because the difference of user's using method, have plenty of in all connectors all installed modules, the but installed module and other connector is in idle state in a part of connector only that has.Like this, when using method changes to some extent, in order to guarantee the performance under all states, the characteristic of this device, the variable quantity of the practical impedance by reducing distribution just can be guaranteed to improve the quality the characteristic and the performance margin of this device.

By connector connected mode as shown in Figure 4, also the method with regard to " outlet part " and " part (or part of returning) of returning " is cross-linked just can produce above-mentioned effect to greatest extent.

Moreover, as the method for the decline that suppresses impedance, can enumerate such example, that is, with the impedance ratio of the impedance of distribution 15,16 or 17 and module, use low (impedance) signal wiring.For example stipulate (for example 40-60 Ω) about 50 Ω.

By installed module, the impedance of actual effect drops to 20-40 Ω, and this value is the distribution of 50 Ω or the distribution of 75 Ω, becomes value about equally.That is, at this moment, use the distribution of 50 Ω that the difference of the impedance before and after installed module is diminished.

In the present embodiment, show 4 circuit 11-14 and be in 1 example within the circuit block 32, still self-evident, the scope of application of the present invention is not subjected to the restriction of its structure, and these circuit also can be dispersed in a plurality of circuit blocks.What certainly, be in good location aspect performance and manufacturing cost is that 4 circuit are included in a structure in the circuit block 32.

If consider the structure of physical storage controller, then only the output circuit of clock signal being separated in other the circuit block also is the desired circuit structure.

In addition, in the present embodiment, show, use clock distribution of the present invention but only data are write for carrying out in memory module that data write and from memory module, carrying out data and read the example that all is suitable for aspect two, and data are read, also can use existing technology.Also can with the alternative of compromise structure example of such prior art and circuit structure, also all identical therewith among the embodiment afterwards.

Compare with the embodiment shown in above-mentioned Fig. 4, increase shown in Figure 6 is from the example of the terminal resistance of described distribution 15 to 17.40-45 represents terminal resistance among Fig. 6.Certainly, terminal resistance will be connected on the terminal power supply.

The example of two ends shown in Figure 6 terminal is even but an end terminal also has this effect.For making the better effects if of terminal, can use the two ends terminal, sense be folk prescription to the time, when control signal wire and address signal line, can be unidirectional terminal for example.At this moment, carrying out the place of terminal can be in a side on output circuit opposite.

It is a lot of that the resistance value of terminal resistance uses the impedance of transmission line to carry out the example of terminal (termination), and for making better effects if, the real impedance values that also can use transmission line is as terminal.From the effect aspect, use the better effects if of the real impedance values of transmission line as terminal.But, although this is worth not strict conformance, as long as have ± deviation about 20 Ω just can play the effect of terminal.

Shown in Figure 1, be branched wirings (15A, 15B, 16A, 17A) and distribution (15,16,17) in order to make the example of impedance matching series matching resistor (46,47,48,49).This build-out resistor is in order to make the signal short arcization on the distribution 15-17, to take impedance matching to be suppressed at the signal reflex of distribution take-off point between distribution, with this end in view being inserted into.

Relevant this build-out resistor, the spy that the inventor is former have been applied for is willing to flat 5-334631 number (spy opens flat 7-202947 number), specially is willing to be described in detail in flat 7-26495 number (spy opens flat 7-283836 number) patent documentation.

This resistance from branched wirings to the transmission of the signal of main wiring, the effect at the take-off point inhibitory reflex is arranged.This resistance value can be set at that (16A introduces half value of the resistance value of distribution (15,16,17) in resistance value 17A) for 15A, 15B from branched wirings.But,, when main wiring practical impedance step-down, also can use the resistance value of the real impedance values replacement main wiring of main wiring because memory module is to be contained on the main wiring.

It would be desirable that the roughly desired value with this resistance is taken in the 0.5-1.5 times of left and right sides scope of the value of trying to achieve in the past.But,, also be effective aspect the high speed that short arcization produced even be taken at about 2 times.

Like this, when employing possesses build-out resistor shown in Figure 1 (46,47,48,49), it would be desirable in memory module one side also possess resistance such shown in Figure 23,24,25.It would be desirable that the resistance between the distribution (15,16,17) to distribution in memory module and motherboard carries out impedance matching, and realize the value of the short arcization on the distribution 15-17.Definite method of the resistance value of this resistance is also the same with described build-out resistor 46-49.At this moment, branched wirings is calculated as the distribution in the memory module.

Secondly, other embodiments of the invention shown in Fig. 5 (embodiment 2).In the clear and definite in the above-described embodiments content, every following examples that are applicable to too, just repeated description no longer.Only difference is described.

Present embodiment will be separated into the clock of reading usefulness and the clock that writes usefulness from the clock signal of Memory Controller output, and the transmission direction of the distribution of using with identical clock 15 signal when reading and when writing fashionable change and respectively they are carried out transmission manner.Herein, the output circuit that writes the clock of usefulness is 11, and the clock output circuit of reading usefulness is 11A, and receiving the receiving circuit that uses Memory Controller to be taken into the clock of the data of reading is 13.12,14 is respectively circuit 12, the received data circuit 14 of output data.

In addition, though in Fig. 5 and not shown, and again at output circuit 11, in the time of all will using during the work of 11A two ends, it would be desirable that respectively the control theory circuit with its output is contained in the memory controller 32.

Identical with the 1st embodiment, in clock distribution 15, if will be from the part conduct " outlet part " of output circuit 11 (farthest) to connector 34F from Memory Controller, and with the destination of " outlet part ", promptly, will be from the part conduct " loop feature " of connector 34F towards connector 34A, in data wiring 16, from output circuit 12 part towards connector 34F as " outlet part ", as " part of returning ", also can be connected on remaining part (promptly turning back to the part of memory module one side of the destination that is positioned at the outlet part) on the connector with it in accordance with under the condition of following rule.

(1) when with " outlet part " when the clock distribution is connected with connector,

The distribution that data are used is connected with connector with " outlet part ".

(2) when the clock distribution being connected with connector with " loop feature ",

" returning part " of data with distribution is connected with connector.

By doing like this, the data-signal distribution is reduced by half, that is, reduce to write from 2 groups of distribution that write special-purpose distribution and read usefulness and read shared 1 group, can produce and the identical effect of embodiment shown in the 1st.

The importation that writes the output of output circuit of clock signal of usefulness and the input circuit of the clock of reading usefulness can be in the inside or outside connection of circuit block (integrated circuit and element).(shown in Figure 5) at the inner example that connects of circuit block.

In addition, the 2nd embodiment is applicable to that the storer LSI that is installed on the memory module is the I/O common type, promptly has an example of the type of the imput output circuit that comprises input circuit, output circuit simultaneously.In this embodiment, the circuit in the employed module becomes the structure shown in Figure 26 for Figure 21 of the 1st embodiment.Become the output circuit 51 that connects output data etc. and receive the form of the receiving circuit 52 of data etc.

Fig. 7 is a type (with Fig. 6 same type of the 1st embodiment) of passing through distribution 15,16 and branched wirings 15A-16A connected storage controller 32 in embodiment 2, and Fig. 8 is the type (type identical with Fig. 1 of the 1st embodiment) of having passed through build-out resistor 46-48 between branched wirings 15A-16A and distribution 15,16.

The following describes the 3rd embodiment.In the 2nd embodiment, show embodiment for the two-way signaling of data-signal etc., and about folk prescriptions such as address signal or control signals to transmission,, just form easily to as shown in Figure 11 as Fig. 9 by removing the path that clock turns back to Memory Controller.Even this only is applicable to that also data-signal also only uses the circuit that writes.

But at this moment, the clock of 2 kinds of the clock that clock that data are used and other signal are used becomes supplies with each memory module, but the clock circuit that also can use data to use is taken into address signal and control signal.At this moment, when 2 clocks are arranged as the 2nd embodiment, also can use to write special clock and be taken into address signal, control signal with SDRAM.In addition, the circuit in the memory module at this moment just becomes type shown in Figure 27 for the Figure 21 among the 1st embodiment.

Shown in Figure 12 is the 4th embodiment that is applied to the 2nd embodiment.When using the shared Memory Controller of I/O, provide identical with the 1st embodiment method that only allows in the one way propagation clock signal of using.

That is,, write data-signal by output circuit output from output circuit 11 clock signals.At this moment, will transmit electricity road (being divided into output circuit 12 and input circuit 14 in the drawings) and transmission line 16 of switch 90 couples together.By doing like this, just can make clock signal and data-signal respectively via about equally distribution length is transferred to the memory module on the connector from Memory Controller 32 to connector 34A～34F.

In addition, when reading, switch 90 connects imput output circuit and transmission line 16B, latchs the data that transmit from 16B by the clock of sending here from 15B.Like this, just can use the clock control mode shown in the 1st embodiment, and be applicable to circuit with I/O data shared line.

In above illustrated embodiment 1～4, the clock that is taken into data is different with the common phase place of Memory Controller clock internal.That is,, be necessary to change clock (be meant herein to give up and return clock change use internal clocking), so that can control again by Memory Controller inside for re-using sense data in Memory Controller inside.Therefore, also can be in advance with timing circuit again, for example FIFO (First-in First-out (first in first out)) circuit is installed in the upstream of input circuit 14.In addition, the size of the clock that comes based on transmission on distribution 15 and the phase deviation of internal clocking, Memory Controller also can have the means whether judgement can be latched in which of internal clocking in cycle.

In addition,, make the clock of output consistent, just can be easy to be taken into data with the phase place of returning the clock that comes by using distribution length, delay circuit etc.

Figure 35 just shows the example of an embodiment who possesses described timing circuit again in Memory Controller 32.Timing circuit is at least by D type latch cicuit 25A again, and trigger circuit 25B constitutes.D type latch cicuit 25A has such function, that is, when the clock of being imported during for high (or low) level, the data that are transfused to are passed through, and the data when being converted into low level (or high level) remain to clock and become height (or low) level again.

In D type latch cicuit 25A, return clock, 2 φ ' positive logic, NOR-logic and be transfused to as clock, in addition, in trigger circuit 25B, the internal clocking of Memory Controller 32,2 φ positive logics or negative logic are transfused to as clock.

Any as for will among these clocks, selecting for use, then will be according to Memory Controller 32 clock internal 2 φ and the phase place extent careful selection of returning clock 2 φ ' that come.

For example, when the phase place extent of 2 φ and 2 φ ' moves half phase place just, for proofreading and correct this skew, the clock of input 2 φ ' negative logic in D type latch cicuit 25A, the clock of input 2 φ positive logics in trigger circuit 25B.

In addition, when the phase place extent of 2 φ and 2 φ ' was consistent just, the positive logic clock of 2 φ ' was transfused in D type latch cicuit 25A, and 2 φ positive logic clocks are transfused in trigger circuit 25B.

In addition, as other embodiment, when phase place was consistent separately, it is unnecessary that trigger circuit 25B becomes, and therefore also the output of 25A directly can be sent to Memory Controller inside.

When in memory module separately except from the clock of Memory Controller output, the clock of the action usefulness of memory module also can remain on above-mentioned timing circuit again one side of memory module during with other distribution supply.

Figure 36 A illustrates an embodiment of the circuit that makes timing circuit more shown in Figure 35 be applicable to Figure 12.In addition, in Figure 36 A, shown is not from Memory Controller but from the example of the clock distribution circuit output clock φ of the front of connector 34A.Clock supply method shown in Fig. 1 promptly, also can be supplied with clock from Memory Controller, but the atc of Memory Controller wants Zao than the atc of storer LS1 usually., compare with writing for this reason, read and become strict.Therefore, with the output circuit of clock move in the Memory Controller connector 34A near, clock phase can be remained on the front, make to write with to read the needed time consistent.

In addition, present embodiment is shown in the 2nd embodiment shown in Figure 12 in the example, self-evident other embodiment that also goes for.In addition, be positioned at the example of the outside of Memory Controller at PLL (the Phase Locked loop-phase-locked loop) 70A with frequency dividing circuit 71A shown in Figure 36 A.32 as shown in Figure 36 B, and in other words, the PLL70A with frequency dividing circuit 71A is the clock signal frequency division that the extended view of ' X ' shown in Fig. 3 A will be supplied to through clock distribution circuit 361 grades from clock signal transtation mission circuit 360.Self-evident, this PLL70 (A) also can be positioned at the inside of Memory Controller.

Moreover Figure 37 A is depicted as the 5th embodiment of the present invention.In the present embodiment, the wire laying mode of transmission line 15,16 is: by 2 connector row 34A～34F, 34G～34M transition.

Among the embodiment shown in above-mentioned, showing and going up the connector row that connect at " outlet distribution " is identical example even with the connector that is connected on " loop distribution ", but in the present embodiment, ((34G in legend～34M) is different to the 34A in the example of figure～34F) be listed as with the connector that is connected " loop distribution " on to connector row that go up to connect at " outlet distribution ".Therefore, the bar number of the transmission line that is disposed below connector becomes half (from " outlet distribution " and " loop distribution " to " outlet distribution " or any one distribution " loop distribution "), can be convenient to wiring, reduce the number of plies of the signal wiring of substrate.

In addition, in Figure 37 A, show the example that transmission line 15,16 is connected with all connector, but also can connect a part of connector, for example connect every a connector.

Certainly, among the figure shown in before Figure 37 A, connector is connected to any one of " outlet distribution " or " loop distribution ", but all unconnected connector of which distribution also can be arranged.For example, make parallel and 2 distributions of layout of distribution, also can be divided into the even number connector, promptly connect 34B, 34D ..., the distribution of 34F and odd number connector promptly, connect 34A, 34D ..., the distribution of 34E.Figure 37 B shows the PLL circuit 70A with frequency dividing circuit 7A, these circuit or can be outside Memory Controller 32 or within it.

Moreover self-evident, the embodiment shown in Figure 37 A not only can be applicable to Figure 36 A, and the embodiment shown in Figure 12 based on Figure 36 A can also be applicable to other embodiment.

Next, relevant the 6th embodiment is described.In the 1st～the 5th embodiment, when the data that Memory Controller 32 1 side joints harvesting storage module is read, Memory Controller 32 receives it in the back synchronously by output distribution 15 and the synchronizing signal that receives.In the 6th embodiment, suppose it is such structure, that is, memory module one side of output data produces the flop signal of the timing become the data that are used to take to receive memory module output.Below elaborate.

The 6th embodiment shown in Figure 46.

The output circuit 172 of clock output circuit 171, clock synchronization type and input circuit 181 are housed and by the input circuit 182 of this input circuit 181 with the signal Synchronization that is taken in Memory Controller 161.

Output circuit 172, input circuit 182 are circuit that data are used.

In addition, transmission line 114～117th, under the modular occasion of Memory Controller or according to the distribution that the layout on the motherboard is carried out, not wanting must be so, and the present invention is not had or not the restriction of distribution in addition.

In following examples, 4 circuit shown in the figure are the examples that are made of 1 circuit block, but these circuit also can be divided into a plurality of circuit blocks.

In addition, distribution 110 is such distributions, that is, in order to be taken into the signal of Memory Controller 161 outputs from actual installation each memory module on connector 140～145, this distribution is the distribution of using from Memory Controller 161 output signals under the clock condition of necessity.

In addition, distribution 111 is to be used for transmitting necessary trigger pip (returning clock) so that be taken into the distribution of the data that the storer on the memory module reads, the storer output of this trigger pip from reading in Memory Controller.

This trigger pip goes out data for one and only exports a pulse with different from the clock of Memory Controller output.

And, can read in and output data from Memory Controller one end in order to make this trigger pip, it would be desirable foundation (preparation) more than the time at Memory Controller, but more late than data.Moreover, it would be desirable in the time that trigger pip is sent and to be longer than the retention time of Memory Controller, thereby the data of storer output are kept in order to satisfy the retention time of Memory Controller.

In addition, in Figure 46, in order to stress every distribution clock signal and the data-signal of transmission memory circuit respectively, so other circuit is all omitted, though in these input circuits and output circuit, only draw wherein 1 group, but self-evident, the present invention is not subjected to this limited in number.

Place shown in the bullet (●) is the contact of distribution and connector.

That is, in the example of Figure 46, the clock signal of exporting from Memory Controller is transferred to connector 140,142 by signal transmission line 110 ..., 141.The signal wiring 112 that data write usefulness also is connected with connector by the identical order of the distribution of using with clock.

Then, the data distribution 113 of reading usefulness and the distribution of using from the trigger pip of storer output 111 is connected with connector to write the opposite order of the data of usefulness with data.That is, data are write distribution by 141,143 from Memory Controller ... 140 order is connected with each connector.

Like this, no matter how the position of memory module is provided with, the transmission time sum when data are write the fashionable transmission time and read all can be reached an agreement.

At this moment, the distribution that the distribution that ideal is uses clock signal, the distribution that trigger pip is used and data write usefulness is perhaps read the transmission time separately of the distribution of usefulness and is all designed unanimity.

If also leave the not connector of plug-in mounting memory module, equate the pseudo-module of load with memory module by plug-in mounting, also be to suppress because the change of mounting blocks number causes the method that practical impedance changes.

Figure 46 illustrates 1 embodiment of two ends terminal, but distribution 110,112 as shown in figure 47 is such, every the signal of making one-way transmission also can only be used unit/terminal.Can reduce installation number of packages, the reduction current drain of parts like this.In addition, when the length of distribution 114～117 enough in short-term, for example, when the transmission time on these distributions approximately less than signal waveform leading edge time or back along the time 1/6 the time, also might save resistance 150～153.But at this moment, because the signal amplitude in the bus 110 becomes big, so it would be desirable that the way of the short arcization that adopts the signal amplitude itself that makes output circuit output etc. is corrected, its example is seen Figure 48.

And the applicant is willing to that the spy the little amplitude circuit that flat 5-334631 number (spy opens flat 7-202947 number) delivers also can be suitable in this circuit.That is, 110 the signal transmission from branched wirings 114～117 to main wiring, resistance 150～153 has the effect of the reflection that is suppressed at the take-off point place.Also can get the setting value of the value of the resistance value that from the resistance value of branched wirings, deducts main wiring as this resistance.But, because memory module is mounted on the main wiring, thus when the practical impedance step-down of main wiring, also can use than before the little value of value.

It would be desirable resistance value roughly is taken in about 0.5 to 1.5 times the scope of the value of trying to achieve in the past.

Below the 7th embodiment is described as follows.But, every part of having introduced in the above-described embodiments, owing to also be applicable in following examples, therefore repeated description not.Only difference is described.

In the 6th embodiment, show the input circuit of Memory Controller 161, memory module 162 and the example of each self-separation of output circuit, and, be to adopt 1 embodiment of imput output circuit in Memory Controller 161, the memory module 162 shown in Figure 49.So-called imput output circuit, be meant, for example if use illustrated Memory Controller to describe, then in circuit block 161 (for example integrated circuit), the output of output circuit 172 and the importation of input circuit 182 are coupled together, no longer set up terminal separately in the circuit block, and make it become 1 shared terminal.

At this moment, insert switch (converter) 190, write fashionable switch in data and be connected to circuit block transmission line 161 1 sides, switch is connected to transmission line 117 1 sides when data are read.

Therefore, can make with in the past shown in the equal effect of the 1st embodiment be applicable in the system with output circuit.Figure 50 is identical with Figure 47, is that Figure 51 is identical with Figure 48, is to remove the example of inserting resistance with 1 example that the circuit of Figure 49 is unidirectional when entering terminal.

Figure 53, circuit diagram shown in 54 is 1 chip of storer of representing emphatically in the memory module, Figure 53 is the circuit diagram that is applicable in the module of the embodiment shown in Figure 46, input circuit 181 is circuit of clock input usefulness, output circuit 171 is circuit that output becomes the trigger pip of returning clock, output circuit 172 is circuit of output sense data, and input circuit 182 is to be used to import the circuit that writes data.Figure 54 is the circuit example by imput output circuit input, outputting data signals.

In addition, the input circuit 181 of input clock signal comprises 1 for each chip usually, uses the clock of importing in this circuit, is taken into and writes data, control signal and address signal.

Shown in Figure 52 is another embodiment, is to make " outlet distribution " and " loop distribution " lead to the example of other connector.So, " outlet distribution " arranged with " loop distribution " identical one deck on the substrate distribution, under the situation that increases the substrate number of plies, the present invention is achieved.

Circuit diagram shown in Figure 55 is at length to show the clock signal of Memory Controller of the present invention and the output circuit of data-signal, the circuit of input circuit.

Trigger 191D, 191S and internal clocking synchronously move, and trigger 191L synchronously moves with the trigger pip of coming to have received the storer of (signal) in the comfortable input circuit 181.

Therefore, clock synchronization that writes data and chip internal and output from Memory Controller output, the data of reading from storer intactly guarantee to set up reception with the retention time by trigger pip, by the next stage trigger by internal clocking more regularly (make phase place consistent) with internal clocking.

Like this, just can make internal clocking consistent with phase place and carry out the exchange of the signal from the Memory Controller to the processor bus.

In addition, in the present embodiment, showing to the trigger 191S that regularly uses again is 1 grade example, certainly, progression is not limited in 1 grade, and at this moment, the phase place that is input to the clock of trigger is chosen in separately between the phase place of internal clocking and trigger pip, by using the frequency multiplied clock of internal clocking, also can realize again with multistage carrying out.

Below, narrate with regard to the improvement of clock signal transmission of the present invention.In the above-described embodiments, clock signal is to move under the loading condiction identical with data-signal.But for example, for the data of carrying out 100MHz transmit, the clock period is that 10ns (frequency is 100MHz) cycle data is 20ns (frequency is 50MHz), compares with data-signal, and clock signal must be with 2 times frequency work.Therefore, the method that clock more stably is provided in the present invention is shown below.

At first, make clock frequency (cycle) identical with signals such as data.Then, in inside modules or at inner 2 times the clock that generates this clock that is transfused to of storer LSI, with this clock synchronization that is generated, and being taken into, exporting of the signal of control SDRAM.

Make Memory Controller one side also have same function.

In addition,, be stabilized in about 50%, also can use PLL, become 4 times, carry out afterwards returning to 2 times behind the frequency division for 1 time for making duty (load) though be 2 multiplication method.Usually, can carry out 2 (N+1) multiplication, carry out frequency division with N as natural number.

From Figure 28 to shown in Figure 34 be exactly to adopt such method.

In Figure 28, use frequency dividing circuit to make clock 2 φ produce the clock φ of 0.5 times frequency with PLL (Phase Locked Loop) 70, use output circuit 11 by Memory Controller 32 these clocks of output.Synchronous with original clock 2 φ again, from output circuit 12 output signals.

An embodiment when Figure 29 illustrates PLL (Phase Locked Loop) 70 that frequency dividing circuit has and is positioned at the elder generation of output circuit 11.The Memory Controller 32 of the PLL (Loocked Loop) 70 that the present invention also is applicable to do not have frequency dividing circuit and contain by this method.

Among Figure 30, the PLL (phase looked loop) 70 that use frequency dividing circuit 71 has makes clock 2 φ ' of clock φ ' generation 2 overtones bands that received by receiving circuit 13, uses this clock 2 φ ', latchs the signal that is received by receiving circuit 14 in trigger 25.Herein, latch clock is 2 φ ', is not to supply with Memory Controller clock internal 2 φ.2 φ and 2 φ ' frequency equate, but 2 φ ' are the clocks that sends and return from Memory Controller, are the clocks by φ ' generation, usually, and the phase place difference.

1 embodiment when Figure 31 illustrates PLL (phase locked loop) 70 that frequency dividing circuit 71 has and is positioned at receiving circuit 13 fronts.By this method, the Memory Controller of the PLL (phase locked loop) 70 that the present invention also can be applicable to do not have frequency dividing circuit 71 and have.

Figure 32 illustrates 1 embodiment of clock output circuit and imput output circuit.The PLL of being had by frequency dividing circuit 71 (phase locked loop) 70 produces half the clock of frequency of internal clockings 2 φ, exports this clock by output circuit 11 by Memory Controller.In addition, receive the clock φ ' turn back to Memory Controller by input circuit, the PLL of having by frequency dividing circuit 71 (phase locked loop) 70 produces clock 2 φ ' of 2 overtones bands.Data and clock 2 φ also output synchronously from output circuit 12 is exported are also received synchronously by data and clock 2 φ ' that receiving circuit received.

Figure 33 is identical with Figure 31, is that PLL (phase locked loop) 70 that frequency dividing circuit 71 has lays respectively at that output circuit 11 is earlier, an embodiment during input circuit 13 fronts.

Figure 34 is illustrated in the memory module, 70 o'clock 1 embodiment of PLL (phaselocked loop) that uses frequency dividing circuit 71 to have.To on memory bus, transmit next φ ' supply synchronized model storer 31, when for example the clock of SDRAM goes between, for making the clock recovery original state that in Memory Controller one side frequency is become half, the PLL (phase locked loop) 70 that just uses frequency dividing circuit 71 to have, with the frequency frequency multiplication, produce clock 2 φ ', and it is supplied with storer 31.

In the example shown in Figure 32, Figure 33, show the example of the Memory Controller of 1/0 circuit types with receiving circuit and output circuit both sides, and in Figure 38 and Figure 39, receiving circuit and output circuit are applicable to the Memory Controller of 1/0 divergence type of the terminal that has separately.The difference of Figure 38 and Figure 39 is the same with the difference of Figure 32, Figure 33, all is that the PLL circuit is when being positioned at the inside of Memory Controller and the difference when being positioned at the outside.

And, provide memory module shown in Figure 40 for the memory module of 1/0 divergence type.This is the example application for 1/0 divergence type of Figure 34 of 1/0 circuit types.

In addition, the present invention also is applicable to the memory module (Figure 42) with impact damper of depositing type, has just the memory module (Figure 43) of impact damper (using as intermediate buffer, is the impact damper of latch-type not, also is called through-type, bus driver).

In addition, for the above-mentioned embodiment of the invention of having introduced, also the present invention is also effective certainly when memory module one side is inserted resistance.By this resistance, seek little amplitudeization, much less, can adopt impedance matching, prevent reflecting background.

Figure 41 is an embodiment who has appended resistance in Figure 40, Figure 44, and 45 is respectively an embodiment who has appended resistance in Figure 42,43.

The state of the circuit board that the one embodiment of the present of invention that illustrate Figure 13～Figure 14 realize.Figure 13 illustrates Memory Controller 32 and is directly installed on the motherboard, is installed in memory module 30 on the daughter board by connector 34 storer 1C (SDRAM) 31 and is installed in state on the motherboard.

Figure 14 be Memory Controller 32 is installed on the daughter board and modularization example.In addition, Figure 15, Figure 16 illustrate not by connector storer 1C31 are directly installed on example on the motherboard.

Above-mentioned several embodiment also can be used to connect high-speed cache and processor.Moreover, as shown in figure 17, in workstation and personal computer, buses miscellaneous such as processor bus, memory bus, peripheral bus are arranged.In the present invention, be to represent with the example that is connected to of memory module and memory module, but the self-evident memory bus that the invention is not restricted to is even in other bus, no matter no matter perhaps be to use or without connector, also whether modularization is all same effectively.In addition, even be not that circuit board is installed, applicable to a plurality of LSI are housed in 1 multimode in the assembly yet.

Adopt the present invention, it is such to make storage system, even in that to exist signal transmission time long and owing in the differentiated system, also may carry out the design of high speed transmission of signals the time delay that the position of module causes.

Claims (6)

1. signal transmitting apparatus, with distribution the 1st circuit block and a plurality of the 2nd circuit block are coupled together, wherein, the 1st circuit block possesses the 1st output circuit of output the 1st data-signal, the 1st receiving circuit of reception the 2nd data-signal, the 2nd circuit block possesses the 2nd receiving circuit that receives above-mentioned the 1st data-signal, the 2nd output circuit of above-mentioned the 2nd data-signal of output, it is characterized in that comprising:

Above-mentioned the 1st circuit block also possesses: the 3rd output circuit of clock signal; Receive the 3rd receiving circuit of above-mentioned clock signal,

Above-mentioned the 2nd circuit block also possesses: receive the 4th receiving circuit of above-mentioned clock signal,

Above-mentioned the 2nd receiving circuit synchronously latchs above-mentioned the 1st data-signal with the above-mentioned clock signal that is received by above-mentioned the 4th receiving circuit,

Above-mentioned the 2nd output circuit is synchronously exported above-mentioned the 2nd data-signal with the above-mentioned clock signal that is received by above-mentioned the 4th receiving circuit,

Above-mentioned the 1st receiving circuit synchronously latchs above-mentioned the 2nd data-signal with the above-mentioned clock signal that is received by above-mentioned the 3rd receiving circuit,

Above-mentioned distribution is connected up, make above-mentioned the 1st circuit block and above-mentioned a plurality of the 2nd circuit block are connected in series, and seeing the 2nd nearest circuit block than seeing from above-mentioned the 1st circuit block to turn back and turn back to from above-mentioned the 1st circuit block in farthest the farther position of the 2nd circuit block

Between any one of above-mentioned the 1st circuit block and above-mentioned a plurality of the 2nd circuit blocks,

Above-mentioned the 1st circuit block is connected with above-mentioned distribution with above-mentioned a plurality of the 2nd circuit blocks, the transmission time of feasible above-mentioned the 1st data-signal and the transmission time of above-mentioned the 2nd data-signal and certain from above-mentioned the 2nd circuit block to above-mentioned the 1st circuit block from above-mentioned the 1st circuit block to above-mentioned the 2nd circuit block.

2. signal transmitting apparatus according to claim 1 is characterized in that:

Above-mentioned distribution comprises the 1st distribution that transmits above-mentioned the 1st data-signal, the 2nd distribution of above-mentioned the 2nd data-signal of transmission, the 3rd distribution of the above-mentioned clock signal of transmission,

Respectively than seeing that from the 1st circuit block the farther position of the 2nd circuit farthest connects up to above-mentioned the 1st, the 2nd and the 3rd distribution with turning back,

On the distribution till from above-mentioned the 1st circuit block to folded back position, in the above-mentioned the 1st and the 3rd distribution, above-mentioned a plurality of the 2nd circuit blocks at least one coupled together, on than above-mentioned folded back position distribution more forward, connects remaining above-mentioned the 2nd circuit block,

For the 2nd circuit block that till the folded back position of above-mentioned the 1st distribution, connects, on the folded back position distribution more forward of above-mentioned the 2nd distribution, carry out being connected of above-mentioned the 2nd distribution and above-mentioned the 2nd circuit block, for remaining above-mentioned the 2nd circuit block, on the distribution till the folded back position of above-mentioned the 2nd distribution, carry out being connected of above-mentioned the 2nd distribution and above-mentioned the 2nd circuit block

Above-mentioned the 3rd receiving circuit receives above-mentioned clock signal via above-mentioned the 3rd distribution.

3. signal transmitting apparatus according to claim 2 is characterized in that:

Above-mentioned the 1st, the 2nd and the 3rd distribution possesses terminal resistance.

4. signal transmitting apparatus according to claim 3 is characterized in that:

Between above-mentioned the 1st output circuit and above-mentioned the 1st distribution, possesses the 1st branched wirings that is used to transmit above-mentioned the 1st data-signal, between above-mentioned the 2nd receiving circuit and above-mentioned the 2nd distribution, possesses the 2nd branched wirings that is used to transmit above-mentioned the 2nd data-signal, between above-mentioned the 3rd output circuit and above-mentioned the 3rd distribution, possess the 3rd branched wirings that is used to transmit above-mentioned clock signal, between above-mentioned the 3rd receiving circuit and above-mentioned the 3rd distribution, possess the 4th distribution that is used to transmit above-mentioned clock signal.

5. signal transmitting apparatus according to claim 4 is characterized in that:

Between above-mentioned the 1st distribution and above-mentioned the 1st branched wirings, possesses the 1st resistive element, between above-mentioned the 2nd distribution and above-mentioned the 2nd branched wirings, possesses the 2nd resistive element, between above-mentioned the 3rd distribution and above-mentioned the 3rd branched wirings, possess the 3rd resistive element, between above-mentioned the 3rd distribution and above-mentioned the 4th branched wirings, possess the 4th resistive element.

6. signal transmitting apparatus according to claim 5 is characterized in that:

The resistance value of above-mentioned the 1st resistive element be positioned at deduct value after half the value of resistance of above-mentioned the 1st distribution from the value of the resistance of above-mentioned 1 branched wirings half to 2 times scope, in addition, the resistance value of above-mentioned the 2nd resistive element be positioned at deduct value after half the value of resistance of above-mentioned the 2nd distribution from the value of the resistance of above-mentioned the 2nd branched wirings half to 2 times scope, the resistance value of above-mentioned the 3rd resistive element be positioned at deduct value after half the value of resistance of above-mentioned the 3rd distribution from the value of the resistance of above-mentioned the 3rd branched wirings half to 2 times scope, and then the resistance value of above-mentioned the 4th resistive element be positioned at deduct value after half the value of resistance of above-mentioned the 3rd distribution from the value of the resistance of above-mentioned the 4th branched wirings half to 2 times scope.

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