CN100353544C - 功率放大器器件 - Google Patents
功率放大器器件 Download PDFInfo
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- CN100353544C CN100353544C CNB03806524XA CN03806524A CN100353544C CN 100353544 C CN100353544 C CN 100353544C CN B03806524X A CNB03806524X A CN B03806524XA CN 03806524 A CN03806524 A CN 03806524A CN 100353544 C CN100353544 C CN 100353544C
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Abstract
功率放大器器件包括具有输出电极的一个或多个晶体管(16)和在该晶体管上的薄膜电容器。该电容器包括第一导电层(18),也是晶体管的输出端子。该电容器还包括第一介电层(20)和第二导电层(22),该第二导电层通过至少一条第一连接线(30)连接到所述第一导电层(18)。第二连接线(34)将所述第二导电层(22)连接到功率放大器器件的输出端子(40)。如此建立并联LC电路,以及设计使得所述并联LC电路在由所述功率放大器放大的频率的谐波(2F0、3F0、4F0、5F0等等)处出现谐振。
Description
本发明涉及具有功率放大器IC器件的功率放大器器件。
从V.J.Tyler的“A new high-efficiency power amplifier(一种新型高效功率放大器)”,M.Marconi Review 21,1958年第三季刊的96-109页中已知高效功率的技术,其中特殊的谐振电路附属在非线性有源器件的输出端,该谐振电路为基本信号F0的不希望的谐波提供高阻抗。这样任何频率成分都可以从输出信号中消除。该成分的功率被锁定并得到放大级的较高效率。
在图1中示出了这样一种晶体管输出电路的基本结构,该输出电路包含电感(L3)2、场效应晶体管(T1)4、包含电感(L1)6和电容(C1)8的并联谐振电路、包含电感(C2)10的第二并联谐振电路。电容(L2)12和等于负载的电阻(14)在包含负载的电阻的一端连接在一起。电感10和电容12组成的并联电路的另一端是连接到地的电路。电感6和电容8组成的并联谐振电路的另一端连接到另一个电感2并连接到场效应晶体管4的漏极,其源极连接到地。
包含电感10和电容12的并联谐振电路被上面提及的文章建议作为理想的滤波电路,用于完全抑制放大器输出端处所有在基本信号F0的频率以下的频率成分和上面的谐波(包含信号的频率2F0,3F0,...nF0)。
当3F0谐波抑制被使用时,该放大器的最大的漏极/集电极效率可以通过上面提及的文章预测为大约88.4%。在2F0谐波抑制情况下,放大器的理论效率为84.9%。以及例如,当3F0+5F0谐波抑制被使用时,那么所预测的效率可以达到92%。
该方法在由分离的功率晶体管构建的放大器中的实施有主要的缺点,那就是通常由电感6和电容8组成的并联谐振电路不能直接用于功率晶体管4的漏极/集电极。
事实上,在实际常用的电路中,通过对电源应用DC去耦电路,可以对基本信号F0以下的频带实现同样的效果,该DC去耦电路连接到晶体管输出外壳并对应于RF信号包络的频带在低频时呈现低阻抗。RF输出匹配电路或阻抗变换电路可以作为由微波传输带线路变压器和陶瓷电容器组成的低通滤波器出现,其中高频成分可以被有效地抑制到小于-50dBc的水平。但是由于在器件集电极/漏极和匹配电路之间引入了外壳和接合线寄生元件,因此无论是什么结构,在晶体管输出端产生的这些2F0、3F0、以及其它成分都不能被位于晶体管的外壳之外的输出匹配电路有效地控制。
因此,总是有一些不希望的成分存在于晶体管的芯片输出和放大器输出电路的其余部分之间,这些成分严重降低了该技术的效力,尤其是在RF频带的上端。
在传统功率放大器设计中存在两个主要的问题,其中功率晶体管被制造为具有铅薄板、陶瓷盖和连接芯片与那些铅板的金线的分离元件。首先,谐振电路必须尽可能地接近晶体管芯片的漏极/集电极,否则谐振电路不能有效地工作。其次,在RF频带的低端,在具有分离器件的传统的功率放大器设计中,很难在电介质衬底上开发和构建谐振电路,并且在高于数百MHz的频率处构建高质量和可控的谐振电路是不可能的(例如,在900MHz功率放大器的情况中,该电路应在3F0=2.7GHz处提供谐振)。
本发明的目的在于提供一种具有谐振频率抑制特性的改进的功率效率的功率放大器器件。为实现该目的,提供一种功率放大器,该放大器具有包含输出电极的功率放大器器件;与输出电极连接的第一导电层;在第一导电层上面的第一介电层;在第一介电层上面的第二导电层,该第二导电层通过期望长度的第一传输线电气连接到第一导电层,由此建立了第一并联LC电路,该电路包含在所述第一(18)和所述第二导电层之间的电容以及由所述传输线形成的电感,所述第一并联LC电路在由所述功率放大器器件放大的频率(F0)的谐波(2F0,3F0,4F0,5F0,...)处谐振,该第一LC电路通过另外的传输线连接到器件的输出端子。
本发明允许在功率晶体管的漏极/集电极处直接构建多谐振器电路,该电路在抑制不希望的谐波或频率成分中非常有效。通过在IC器件的输出电极处直接实现谐波调谐电路,功率放大器的输出电路的新型结构可以提高器件的功率效率(理论上大于85%)。该结构可以简单地通过在IC器件的输出端子表面上逐步地增加隔离层以及紧接着的另一个金属层来实现。
从US-A6060951可知具有谐波匹配电路的功率放大器器件。然而,谐波电路紧接着功率放大器IC器件而不是在其上面。已知的功率放大器器件因此具有以下缺点,功率放大器IC器件和谐波电路之间的内部连接是必需的。此外,作为设计局限性的结果,谐波电路的电容器和电感器具有有限值,这限制了器件在工作频率的应用。器件工作在RF频带的低频边界时不能适当地运行。此外,谐波电路通过半导体衬底相对于地存在相对较高的寄生分布电容。这损坏了谐振器所要求的抑制特性。更为不利的是它的低Q因子,以及由此导致的不足的效率。而且,电容器被设计为内部连接中的间隙。这具有电容器电场非线性的缺点,并且是设计中的缺陷。
替代地,在本发明的功率放大器器件中,寄生电容减小。这涉及由于电容器位于晶体管的上面的事实产生的对地的寄生电容。还涉及在IC器件的输出电极(通常是集电极或漏极)和第一导电层之间的任何寄生电容。
本发明中提供的电容实际上是薄膜电容器。作为电感的传输线可以用薄膜技术提供。然而,优选的是这些都用连接线实现。大体上,一条线已经足够,但是通常优选的是使用一对线以便使电阻最小。
由于可以有效地决定接合线的长度,所以谐波电路可以很容易地调谐。这基于以下理解,电感是通过并联线的长度和/或数量而不是通过任何其他元件决定的。另一个优点是只有空气包围电感L1的线,所以它提供高Q(品质因数)。而且,改变谐振电路用于另一个频率是灵活而且容易的。通过上面提及的生产中的技术容易实现足够的电感。这可以用现有的设备精确地实现。可以看出,每个谐振电路可以有不止一条线存在。
本发明的器件的另一个优点是可以选择介电层的材料使得电容器最优化。这是可以做到的,由于介电层不构成IC器件的部分,并通过第一导电层与IC器件分离,于是防止了任何寄生电容。具有高介电常数和具有低介电常数的合适的材料是本身已知的。
在实施例中第二介电层存在于所述第二导电层的上面,在第二介电层的上面存在第三导电层,该第三导电层利用第二传输线连接到第二导电层,于是定义了串联在第一LC电路和另外的传输线之间的第二并联LC电路,并且在不同于第一LC电路的放大信号的任何其它谐波频率处谐振。第二传输线优选地实现为连接线。本发明的该实施例可以实现不止一个串联的谐振电路,而在它们之间没有任何寄生元件,否则该寄生元件会严重降低该技术的效率。
根据本发明的功率放大器器件的优选实施例,导电层和介电层及连接线的结构被重复用于任何要消除的谐波频率。重复上述结构的可能性还有利于功率效率的提高。
根据另一个实施例,该器件还具备在放大器器件的基频(F0)处谐振的谐振电路,该谐振电路包含具有连接到第一导电层的电感和连接到地的电容器的串联LC电路。为得到更好的性能控制和谐波相位控制,器件芯片的寄生输出电容可以有利地通过并联电感补偿,该电感通过MOS电容器连接到地,只允许RF电流通过电感。利用在F0处提供谐振的电感,功率放大器器件成为没有寄生电容的几乎理想的开关元件。这将可以获得比功率晶体管的F类工作更好的控制。
在另一个实施例中,以这样的方式修改输出电路,使得它更容易满足F类工作条件。这些条件得到满足,是因为在频率F0和3F0处都提供输出电容补偿,以及这些装置在3F0处提供电压峰化。例如,由于器件输出端处的电压波被拉平以及从“开”状态到“关”状态的过渡时间被缩短,因此所述电压峰化可以实现。具有本实施例的输出电路的高效功率放大器可以实现为分离元件,也可以实现为集成的MMIC方案。
RF功率晶体管的输出电路(例如LDMOST或双极性),通常有非常大的输出寄生电容。当希望在RF频带的频率处设计F类功率放大器时,这是最难解决的问题。例如,对于45W、1GHz的LDMOST,输出电容Cout一般在30-40pF左右。因此,从“开”状态到“关”状态的晶体管过渡时间不够短。
根据本发明的串联连接到RF功率晶体管的并联LC电路具有以下优点,它可以为晶体管输出端处的期望谐波提供理想的“开路”和电压峰化。这已经减小了过渡时间的问题。然而,寄生输出电容降低了该方法的效率的优点。通过实施3F0陷波电路,效率可以进一步得到提高。利用3F0陷波电路可以实现,把三次谐波3F0的能量用于拉平晶体管输出端处的电压波。这样可以满足F类工作条件。
根据优选实施例,功率放大器IC器件是一个晶体管。可替代地,功率放大器IC器件可以是多个晶体管,因此实现用于不止一个晶体管的单个谐波电路。然而,优选的是每个晶体管有一个谐波电路。在晶体管是MOSFET的情况下,输出电极是漏极。尤其优选的是晶体管是LDMOS类型。LDMOS型的晶体管应用在功率放大器中具有极好的品质。由于它们具有横向结构,所以有足够的尺寸可以在晶体管上面提供电容器。在晶体管是双极性晶体管的情况下,输出电极是集电极。
晶体管优选地在硅衬底中定义。然而,本发明不限于此,也可以用于任何其它半导体衬底的晶体管。在硅衬底的情况下,晶体管可以有一个多晶硅层,该层作为第一导电层,并且MOSFET的栅极也在该层中定义。于是,栅极和电容器电极是相互隔离的。
在本文所附的以及构成本文一部分的权利要求中具体提出了体现本发明特点的这些和其它不同的优点以及新颖性特征。然而,为了更好地理解本发明、其优点、以及通过其使用所实现的目的,应当参考构成本文的另外部分的附图,以及伴随的具有本发明的优选实施例的说明和描述的描述材料。
现在参考附图描述本发明的优选实施例,其中:
图1是众所周知的高效功率放大器输出电路的基本结构;
图2是功率放大器器件的一个例子,该器件具有串联连接在晶体管漏极或集电极金属化区域上面的两个并联谐振器和输出电容的补偿电路。
图3是图2中所示例子的等效示意图;以及
图4是LDMOS晶体管的可能结构;
图5是参考电路的等效示意图;
图6是本发明的优选实施例的等效示意图;
图7是显示阻抗作为图5参考电路的频率的函数的曲线图;以及
图8是显示阻抗作为本发明优选实施例的频率的函数的曲线图。
图2示出了功率放大器器件的一个例子,该器件具有两个并联谐振器或谐振电路,它们串联连接在功率放大器IC器件16的漏极或集电极金属化区域的上面并形成输出电容的补偿电路。
在所示实施例中,功率放大器包含功率放大器IC器件16的芯片;金属层18,该层是漏极或集电极触点;绝缘体层20;与金属层18形成电容器的另一个金属层22;另一个绝缘体层24;以及与金属层22形成电容器的再一个金属层26。两条接合线(也可以包含并联的一对接合线)28和30形成谐振器电路的电感,以及接合线32(也可以包含并联的一对接合线)是寄生输出电容(Cout)36的补偿电感并连接到晶体管输出铅板40。输出接合线34(也可以包含并联的一对接合线)。接合线32连接到接地的MOS电容器38。
层18、20和22形成一个电容器。与层18、20和22形成的电容器并联的是由接合线30(也可以包含并联的一对接合线)形成的电感。该包含电容器和电感的并联电路形成第一并联谐振器。三层22、24和26形成第二电容器。与该电容器并联的是接合线28的电感。该结构形成第二并联谐振器,该谐振器包含电感和电容。第二并联谐振器串联连接到第一并联谐振器。
接合线34连接到层26的顶表面,在其底表面上的顶表面被连接到功率放大器件16的输出端子40。寄生输出电容36位于层18和功率放大器IC器件的散热片之间。为了补偿该寄生输出电容36,有必要使用包含接合线32的电路,该接合线32形成电感,该电感串联连接到MOS电容器38并与电容36一起并联谐振。
当调谐到2F0或3F0时,仅仅一个谐振器提供具有两次或三次谐波峰化的模式,相应地,它产生预测的功率效率为84.9%或88.4%。当两个谐振器都被用于串联连接在晶体管芯片的集电极或漏极区域的上面时,器件效率可以提高更多,而且在3F0和5F0谐波峰化处可以达到92%。
为了得到更好的性能控制和谐波相位控制,功率放大器IC器件16的寄生输出电容36可以通过接合线32的并联电感补偿,该接合线32通过MOS电容器38连接到地,只允许RF电流通过接合线32的电感。
当接合线32的电感调谐为在F0处谐振时,功率晶体管成为没有寄生电容的几乎理想的开关元件。这将可以得到对功率晶体管的F类工作的更好的控制。接合线32的电感和电容38在3F0处谐振,现在成为功率晶体管的一部分并且不构成“输出网络”。因此,保证了补偿电路尽可能地靠近功率放大器IC器件16,而在晶体管漏极/集电极和补偿电路之间没有任何显著的寄生元件。
在3F0谐振的电路包含由层18、20和22形成的电容,以及由接合线28形成的电感。因此谐振电路直接在功率晶体管芯片的表面上实现。电容被实现为在漏极接触层上(如图2中所示)的串联电容器,在这种情况下,该漏极接触层被用作由层18、20和22形成的电容的下面板。优选地由用金制成的接合线28形成的电感(大约0.3nH)把晶体管16的漏极触点与上面板26连接起来,该板26然后通过另一条接合线/多条接合线连接到外壳铅板40或输出端子40。
在使用中,由层18、20和22形成的电容的值和由接合线28形成的电感的值是相对较小的,例如分别为10pF和0.3nH。因此,在功率放大器的芯片表面处实现电容和电感不是一项困难的工作。同样,可以容易地通过改变并联接合线的长度、数量和感应耦合,把期望的谐振频率调节到任何其它频率。
这是一种非常有利的方法,因为(1)只有空气包围L1的线,产生高Q;(2)在功率放大器的漏极/集电极的芯片铅板和谐振电路之间没有显著的寄生元件;(3)谐振电路是灵活或易于调节为另一个频率的;以及(5)谐振电路在生产中易于实现。
图3示出了图2结构的等效电路。该等效电路包含连接到场效应晶体管44的栅极的信号源42。场效应晶体管44的源极连接到地并连接到电容器46的一端。场效应晶体管44的漏极与电容46的另一端连接并与电容52、电感54和电感48的一端连接。电感48与电容50的一端连接。电容50的另一端与地连接。电容52的另一端与电容56的一端、电感54和电感58的一端连接。电容56的另一端连接到电感58的另一端和电感60。电感60的另一端与输出端62连接。
电容46是图2中输出电容36的等效电容。为了补偿输出电容46,使用电感48和电容50的串联电路。电感48等效于接合线32以及电容50等效于MOS电容38。包含电感48和电容50的电路是功率晶体管的一部分并且不是“输出网络”的一部分。该电路在等于或接近于F0的频率处具有并联谐振。
包含电感54和电容52的第一并联谐振器调谐到2F0或3F0,并提供具有二次或三次谐波峰化的模式,相应地,该第一并联谐振器产生预测的功率效率84.9%或88.4%。与第一谐振器串联的第二并联谐振器包含电容56和电感58。可以构造第二并联谐振器以得到更好的电压波形和更高的效率,它可以调谐到五次谐波。在第二并联谐振器和输出端62之间是由接合线34形成的电感60。输出端62等效于功率放大器器件的输出端子40。
图4示出了本发明实施例中的LDMOS晶体管的可能结构。该结构包括芯片64、例如用多晶硅制成的下面板66、绝缘体层68和形成第一并联谐振器的电容的上面板70。接合线71连接在下面板66的触点79和上面板70的触点78之间。接合线72连接在下面板66的触点77和上面板70的触点76之间。接合线71和72形成第一并联谐振器的电感。接合线82连接在触点76和外壳铅板88之间。接合线84连接在触点78和外壳铅板88之间。接合线86连接在触点80和外壳铅板88之间。接合线82、84和86连接第一并联谐振器与外壳铅板88或输出端88。
在本发明的优选实施例中,在输出电路中应用3F0陷波电路。参考图5到8解释其效果。图5是没有谐波陷波电路的参考电路的等效示意图。图6是具有谐波陷波电路和3F0陷波电路的优选实施例的等效示意图。图7和8分别是显示作为图5和6中示出的电路频率的函数的阻抗的曲线图。为了清楚地表示,在图3、5和6中使用相同的参考符号,代表相同元件。
图5的电路包括电感48和电容50,它们用于补偿输出电容46。在本例中,输出电容46是40pF,电感48是0.4nH,以及电容50是16pF。除此之外,为了在三次谐波频率3F0处提供输出电容的补偿,它包括另一个连接到地的LC网络,该网络包含0.7nH的电感49和1000pF的电容51。
该参考电路所得到的性能在图7中示出。在这里,阻抗的实数部分用上面的线表示,虚数部分用下面的线表示。很明显,阻抗的实数部分有两个明显的最大值m1和m2,一个接近基频F0,一个在三次谐波3F0频率处。
图6电路对应于图4电路外加另一个LC网络,该网络包括0.7nH的电感49和1000pF的电容51。图8的相应曲线显示阻抗的实数部分也具有两个最大值m1和m2。第一最大值m1不是接近而是在基频F0处。第二最大值m2依然在三次谐波3F0频率处。与参考电路的性能相比较,在频率3F0处,阻抗的虚数和实数部分都高得多,也就是,存在较大的谐振。使用包含电容器52和电感器54的三次谐波陷波电路在三次谐波频率3F0处产生凹口或断路。这在晶体管的漏极处拉平电压波,并为F类工作模式创造条件。
简而言之,功率放大器器件包括具有输出电极的一个或多个晶体管以及在该晶体管上的薄膜电容器。电容器包括第一导电层,也是晶体管的输出端子。它还包括第一介电层和第二导电层,该第二导电层通过至少一条第一连接线连接到所述第一导电层。第二连接线将所述第二导电层连接到功率放大器器件的输出端子。如此建立并联LC电路,以及设计使得所述并联LC电路在所述功率放大器放大的频率的谐波处出现谐振。
由本文覆盖的本发明的新特性和优点已经在前面的描述中阐明。然而,在许多方面,可以理解这种公开只是示例性的。在不超出本发明的范围的情况下,可以做出详细的变化,尤其是与部件的形状、尺寸以及结构有关的变化。当然,本发明的范围是用所附的权利要求表述的语言来限定的。
Claims (10)
1.一种功率放大器,包括:
-具有输出电极的功率放大器器件(16);
-与该输出电极连接的第一导电层(18);
-在该第一导电层(18)上面的第一介电层(20);
-在该第一介电层(20)上面的第二导电层(22),该第二导电层(22)通过所需长度的第一传输线(30)电气连接到该第一导电层(18),
由此,建立了第一并联LC电路,该电路包括在所述第一(18)和所述第二(22)导电层之间的电容器以及由所述第一传输线(30)形成的电感,所述第一并联LC电路在由所述功率放大器器件(16)放大的频率(F0)的谐波(2F0,3F0,4F0,5F0,...)处谐振,该第一LC电路通过另一条传输线(34)连接到该器件的输出端子(40)。
2.根据权利要求1的功率放大器,其中第二介电层(24)存在于所述第二导电层(22)的上面,在该第二介电层(24)上存在第三导电层(26),该第三导电层利用第二传输线(28)连接到该第二导电层(22),由此定义串联连接在第一LC电路和另一条传输线(40)之间的第二并联LC电路,并且在不同于第一LC电路的放大信号的任何其他谐波频率处谐振。
3.如前面任一项权利要求所述的功率放大器,其中所述第一和第二传输线(30,28)被实现为一条或多条连接线。
4.如权利要求1所述的功率放大器,其中所述另一条传输线被实现为连接线。
5.如权利要求2或3所述的功率放大器,其中所述谐振电路结构被重复用于任意要被消除的谐振频率。
6.如权利要求1所述的功率放大器,还具备用于在所述放大器器件(16)的基频(F0)处谐振的谐振电路,该谐振电路包括串联LC电路,其中电感(32)连接在第一导电层(18)和另一侧连接到地的电容器(38)之间。
7.如权利要求5所述的功率放大器,还包括连接到用于在基频(F0)处谐振的所述谐振电路的补偿电路(49,51)。
8.如权利要求7所述的功率放大器,其中所述补偿电路是连接到地的串联LC网络。
9.如权利要求1所述的功率放大器,其中所述功率放大器器件(16)包括至少一个LDMOS类型的晶体管。
10.如权利要求9所述的功率放大器,其中所述第一导电层(18)包含多晶硅,晶体管的栅极也在该层中定义,该栅极和作为电容器电极的第一导电层区域相互隔离。
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