CN100346575C - Bit order converter - Google Patents
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- CN100346575C CN100346575C CNB2003101182511A CN200310118251A CN100346575C CN 100346575 C CN100346575 C CN 100346575C CN B2003101182511 A CNB2003101182511 A CN B2003101182511A CN 200310118251 A CN200310118251 A CN 200310118251A CN 100346575 C CN100346575 C CN 100346575C
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Abstract
The present invention relates to a bit order converter which comprises a first input transistor, a second input transistor, a first bias voltage transistor, a second bias voltage transistor, a first switch transistor and a second switch transistor. In the present invention, when the present invention is in a signal converting state, a critical voltage thereof is reduced by raising the electric potential of a base of the second input transistor to enable current flowing through the second input transistor to become large, so the signal converting time can be shortened. The bit order converter of the present invention enables a circuit of the whole bit order converter to be simplified and can reach the effect of reducing the critical voltage. Accordingly, the operating speed at the time of signal conversion can be higher under the condition that the original functions of the circuit is not affect, so the present invention is more practical.
Description
Technical field
The present invention relates to a kind of rank transducer, particularly relate to a kind of rank, position transducer that shortens signal change-over time with active substrate bias technology.
Background technology
Multimedia society improves rapidly, is indebted to the tremendous progress of semiconductor subassembly or man-machine display device mostly.With regard to display, (Cathode Ray Tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode ray tube always.Yet, operate the environment of most terminating machine/display equipments on the table for the individual, or with the incision of the viewpoint of environmental protection, if predicted with the trend of saving the energy, cathode ray tube is because of still existing a lot of problems in space utilization and the energy resource consumption, and can't effectively provide solution for the demand of light, thin, short, little and low consumpting power.Therefore, have that high image quality, space utilization efficient are good, (Thin Film Transistor Liquid Crystal Display TFTLCD) becomes the main flow in market to the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless gradually.
In LCD, position rank transducers (Level Shifter) are for scanning the important circuit of driver and data driver in the panel of LCD, and it can be converted to the electronegative potential input signal high potential output signal.Low temperature polycrystalline silicon (the Low-TemperaturePoly-Silicon of the normal use of LCD now, abbreviation LTPS) has higher critical voltage and lower mobility, therefore, along with the increase of panel picture element, the deficiency that the operation of LCD speed of use low temperature polycrystalline silicon can become gradually.
Figure 1A is the circuit diagram of existing a kind of rank transducer.This rank transducer 50 comprises the first input transistors Mn1, the first substrate bias circuit 510, the first switching transistor Mp1, the second input transistors Mn2, the second substrate bias circuit 530 and second switch transistor Mp2.The gate terminal 502 of the first input transistors Mn1 is coupled to the signal source of first clock signal, source terminal 506 ground connection.The output 516 of the first substrate bias circuit 510 is coupled to the substrate 508 of the first input transistors Mn1, and input 518 is coupled to the gate terminal 502 of the first input transistors Mn1.The drain electrode end 524 of the second input transistors Mn2 is coupled to output 560, and gate terminal 522 is coupled to the signal source of second clock signal, source terminal 526 ground connection.The output 536 of the second substrate bias circuit 530 is coupled to the substrate 528 of the second input transistors Mn2, and input 538 is coupled to the gate terminal 522 of the second input transistors Mn2.The drain electrode end 544 of the first switching transistor Mp1 is coupled to voltage source, and gate terminal 542 and source terminal 546 are coupled to the drain electrode end 504 of the first input transistors Mn1.The drain electrode end 554 of second switch transistor Mp2 is coupled to voltage source, and gate terminal 552 is coupled to the gate terminal 542 of the first switching transistor Mp1, and source terminal 556 is coupled to the drain electrode end 524 of the second input transistors Mn2.
Wherein, the first substrate bias circuit 510 and the second substrate bias circuit 530 comprise buffer 512,514 and buffer 532,534 respectively.
The manner of execution of last rheme rank transducer is a logic high potential for working as first clock signal, when the second clock signal is logic low potential, the first input transistors Mn1, the first switching transistor Mp1 and second switch transistor Mp2 will be switched on, the second not conducting of input transistors Mn2.Transfer logic low potential and work as first clock signal to by logic high potential, when the second clock signal transfers logic high potential to by logic low potential, the first input transistors Mn1, the first switching transistor Mp1 and second switch transistor Mp2 will end, the second substrate bias circuit 530 will add a high potential in the substrate 528 of the second input transistors Mn2 this moment, to suppress the critical voltage of transistor seconds Mn2, to put forward the service speed of high level transducer 50.But in rank, existing position transducer 50, it makes that because of having the first substrate bias circuit 510 and the second substrate bias circuit 530 the circuit volume of rank, whole position transducer 50 is quite big.
Application number is that 03101695.2 Chinese patent application has disclosed a kind of rank converter circuit, and it is to utilize a bias transistor to realize biasing to the input transistors substrate.Shown in Figure 1B, the source electrode termination input signal IN of bias transistor 55, the substrate of drain electrode termination input transistors 1, grid termination output signal OUT (when bias transistor 55 is the P type) or anti-phase output signal XOUT (when bias transistor 55 is the N type).When input signal IN was electronegative potential, input transistors 1 ended, and output signal OUT also is an electronegative potential, and bias transistor 55 conductings are when input signal IN is introduced into the substrate of input transistors 1 when high potential changes by electronegative potential.Finished upset to conducting when input transistors 1, output signal OUT becomes high potential, and bias transistor 55 ends, and stops the high potential biasing to input transistors 1 substrate.Though this kind bias mode is simple, in today that the power supply and the signal level of integrated circuit is tending towards lower voltage, the mode effect that this kind setovered to the substrate of input transistors 1 by means of the low level of input signal is limited.
Application number is that 10/342,172 U.S. Patent application has disclosed rank, another kind of position converter circuit shown in Fig. 1 C, the source terminal ground connection of bias transistor 26, the substrate of drain electrode termination input transistors 24, grid termination input signal IN.When input signal IN is electronegative potential, input transistors 24 and bias transistor 26 all end, output signal OUT is a high potential, this moment input transistors 24 substrate by self electric charge accumulation set up bias voltage in advance, when input signal IN is quickened the upset of input transistors 24 when high potential changes by electronegative potential.In fact this kind bias mode does not add any bias voltage in the substrate of input transistors.The effect of bias transistor just input transistors finish from by to the upset of conducting the time with its substrate zero offset, reduce to flow into the perforation electric current of input transistors substrate, and can improve the critical voltage of input transistors, so that when electronegative potential changes, quicken the upset of input transistors from high potential to cut-off state at input signal.
This shows that rank, above-mentioned existing position transducer still has many defectives, and demands urgently further being improved.In order to solve a problem that the rank transducer exists, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that rank, above-mentioned existing position transducer exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, actively studied innovation, in the hope of founding rank, a kind of novel position transducer, not only circuit is simple but also have a better substrate biasing effect to make it.
Summary of the invention
The object of the present invention is to provide a kind of rank, position transducer of substrate biasing better effects if, technical problem to be solved is by simple biasing circuit, substrate to input transistors adds the bias voltage that is higher than incoming signal level, critical voltage with further reduction input transistors, the reversal rate of circuit is quicker when making the input signal conversion, and can adapt to the power supply of integrated circuit and the development trend of signal level lower voltage, thereby be suitable for practicality more, and have industrial utilization.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of rank transducer according to the present invention proposes is electrically coupled to a voltage source, one first clock signal and a second clock signal.This rank transducer comprises a switching circuit, a transistor seconds group and a transistor seconds group.
This switching circuit has one first output and one second output, receives this voltage source.
This first transistor group comprises one first input transistors and one first bias transistor.Wherein this first input transistors has drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this first input transistors is coupled to this first output, the source terminal ground connection of this first input transistors, the gate terminal of this first input transistors receive this first clock signal; This first bias transistor has drain electrode end, source terminal and gate terminal.
This transistor seconds group one end is electrically coupled to this second output, and other end ground connection determines between this second output and the ground with this second clock signal whether conducting.
Rank, position of the present invention transducer is characterised in that, the drain electrode end of this first bias transistor is coupled to this first output, the source terminal of this first bias transistor is coupled to the substrate of this first input transistors, the gate terminal of this first bias transistor receive this first clock signal and this second clock signal one of them.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Rank, aforesaid position transducer, wherein said switching circuit comprises one first switching transistor and a second switch transistor.This first switching transistor has drain electrode end, source terminal and gate terminal, and the drain electrode end of this first switching transistor is coupled to this voltage source, and the source terminal of this first switching transistor and gate terminal are coupled to this first output; This second switch transistor has drain electrode end, source terminal and gate terminal, this second switch transistor drain end is coupled to this voltage source, the transistorized source terminal of this second switch is coupled to this second output, and the transistorized gate terminal of this second switch is coupled to this first output.
Rank, aforesaid position transducer, wherein said switching circuit comprises one first switching transistor and a second switch transistor.This first switching transistor has drain electrode end, source terminal and gate terminal, the drain electrode end of this first switching transistor is coupled to this voltage source, the source terminal of this first switching transistor is coupled to this first output, and the gate terminal of this first switching transistor is coupled to this second output; This second switch transistor has drain electrode end, source terminal and gate terminal, this second switch transistor drain end is coupled to this voltage source, the transistorized source terminal of this second switch is coupled to this second output, and the transistorized gate terminal of this second switch is coupled to this first output.
Rank, aforesaid position transducer, this first input transistors and this first bias transistor of wherein said the first transistor group are the N type metal oxide semiconductor, the gate terminal of this first bias transistor is coupled to this first clock signal.
Rank, aforesaid position transducer, this first input transistors of wherein said the first transistor group is the N type metal oxide semiconductor, this first bias transistor is a P-type mos, and the gate terminal of this first bias transistor is coupled to this second clock signal.
Rank, aforesaid position transducer, wherein said transistor seconds group comprises one second input transistors and one second bias transistor.This second input transistors has drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this second input transistors is coupled to this second output, the source terminal ground connection of this second input transistors, the gate terminal of this second input transistors receive this second clock signal; This second bias transistor has drain electrode end, source terminal and gate terminal, the drain electrode end of this second bias transistor is coupled to the gate terminal of this second input transistors, the source terminal of this second bias transistor is coupled to the substrate of this second input transistors, the gate terminal of this second bias transistor be coupled to this second output and this first output one of them.
Rank, aforesaid position transducer, this second input transistors and this second bias transistor of wherein said transistor seconds group are the N type metal oxide semiconductor, the gate terminal of this second bias transistor is coupled to this second output.
Rank, aforesaid position transducer, this second input transistors of wherein said transistor seconds group is the N type metal oxide semiconductor, this second bias transistor is a P-type mos, and the gate terminal of this second bias transistor is coupled to this first output.
Rank, aforesaid position transducer, wherein said transistor seconds group comprises one second input transistors and one second bias transistor.This second input transistors has drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this second input transistors is coupled to this second output, the source terminal ground connection of this second input transistors, the gate terminal of this second input transistors receive this second clock signal; This second bias transistor has drain electrode end, source terminal and gate terminal, the drain electrode end of this second bias transistor is coupled to this second output, the source terminal of this second bias transistor is coupled to the substrate of this second input transistors, the gate terminal of this second bias transistor receive this second clock signal and this first clock signal one of them.
Rank, aforesaid position transducer, this second input transistors and this second bias transistor of wherein said transistor seconds group are the N type metal oxide semiconductor, the gate terminal of this second bias transistor is coupled to this second clock signal.
Rank, aforesaid position transducer, this second input transistors of wherein said transistor seconds group is the N type metal oxide semiconductor, this second bias transistor is a P-type mos, and the gate terminal of this second bias transistor is coupled to this first clock signal.
By above technical scheme as can be known, rank, position of the present invention transducer is by the drain electrode of bias transistor, the substrate that source electrode is introduced input transistors with output end voltage, because the output signal level of rank, position transducer is apparently higher than the input signal level, so with respect to the bias mode of input signal voltage being introduced the input transistors substrate or with respect to input transistors by the time by electric charge accumulation set up the mode of bias voltage, rank, position of the present invention transducer has the following advantages and beneficial effect:
1, when input signal be electronegative potential, input transistors and bias transistor all end, the quiescent biasing voltage of setting up in the substrate of input transistors is higher than input signal voltage, biasing intensity to the input transistors substrate is big, can further reduce the critical voltage of input transistors, in case input signal becomes high potential, can further accelerate input transistors by the upset that ends to conducting, and can adapt to the lower voltage of input signal level.
2, be high potential when input signal is risen to by electronegative potential, input transistors and bias transistor overturn to conducting by ending.If input transistors is by lagging behind bias transistor by the switching process to conducting, then because the conducting resistance that the conducting resistance that bias transistor presents in switching process presents than input transistors descends fast, make substrate bias voltage fast rise on the basis of quiescent biasing voltage of input transistors, the critical voltage of input transistors is descended fast, further accelerate input transistors by the upset that ends to conducting.Because the conducting resistance that input transistors presents reduces rapidly, its substrate bias voltage also reduces rapidly subsequently.Above-mentioned phenomenon illustrates that biasing circuit of the present invention has adaptation function, can adjust the size of bias voltage according to the property difference of input transistors and bias transistor automatically.
In sum, rank, position of the present invention transducer with than the better substrate biasing of rank, existing position transducer effect, and can reach the function of further reduction critical voltage, make that the conversion speed of output signal is faster, and can adapt to the lower voltage of input signal level.Rank, position of the present invention transducer has above-mentioned plurality of advantages and practical value, not seeing has similar circuit to publish or use and really genus innovation, and rank, more existing position transducer has the effect of enhancing, thereby be suitable for practicality more, having more the extensive value of industry, really is a new and innovative, progressive, practical new invention.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Figure 1A is the circuit diagram of existing a kind of rank transducer.
Figure 1B is that application number is the circuit diagram of a kind of rank transducer disclosing of 03101695.2 Chinese patent application.
Fig. 1 C is that application number is the circuit diagram of a kind of rank transducer disclosing of 10/342,172 U.S. Patent application.
Fig. 2 A is the position rank converter circuit figure according to a kind of N type metal oxide bias transistor of preferred embodiment of the present invention.
Fig. 2 B is the position rank converter circuit figure according to a kind of P type metal oxide bias transistor of preferred embodiment of the present invention.
Fig. 3 A is the circuit diagram according to a kind of transistor seconds group of a preferred embodiment of the present invention.
Fig. 3 B is the circuit diagram according to the another kind of transistor seconds group of a preferred embodiment of the present invention.
Fig. 3 C is the circuit diagram according to another transistor seconds group of a preferred embodiment of the present invention.
Fig. 3 D is the circuit diagram according to another transistor seconds group of a preferred embodiment of the present invention.
Fig. 4 A is the circuit diagram according to a kind of switching circuit of a preferred embodiment of the present invention.
Fig. 4 B is the circuit diagram according to the another kind of switching circuit of a preferred embodiment of the present invention.
The reference numeral explanation
30,32,50: rank, position transducer 100: the first transistor group
102,112,122: gate terminal 132,142,152: gate terminal
502,522,542,552: gate terminal 104,114,124: drain electrode end
134,144,154: drain electrode end 504,524,544,554: drain electrode end
106,116,126: source terminal 136,146,156: source terminal
506,526,546,556: source terminal 108,128,508,528: substrate
130: transistor seconds group 140: switching circuit
184: the second outputs of 182: the first outputs
The substrate bias circuit 512,514,532,534 in 510: the first: buffer
518,538: input 516,536,560: output
530: the second substrate bias circuit Mn1: first input transistors
Mn2: the second input transistors Mn1*, Mp1*: first bias transistor
Mn2*, Mp2*: the second bias transistor Mp1: first switching transistor
Mp2: second switch transistor
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, to rank, position its embodiment of transducer, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
In the circuit diagram of the rank, position of a preferred embodiment of the present invention shown in Fig. 2 A transducer, rank, position transducer 30 is to be electrically coupled to voltage source, first clock signal and second clock signal.This rank transducer 30 comprises the first transistor group 100, transistor seconds group 130 and switching circuit 140.
In the present embodiment, the first transistor group 100 comprises the first input transistors Mn1 and the first bias transistor Mn1*, is the N type metal oxide semiconductor.This first input transistors Mn1 has drain electrode end 104, source terminal 106, gate terminal 102 and substrate 108.The drain electrode end 104 of the first input transistors Mn1 is coupled to source terminal 106 ground connection of first output, 182, the first input transistors Mn1, and gate terminal 102 receives and whether determines the conducting first input transistors Mn1 according to first clock signal.The first bias transistor Mn1* has drain electrode end 114, source terminal 116 and gate terminal 112, the drain electrode end 114 of the first bias transistor Mn1* is coupled to first output 182, source terminal 116 is coupled to the substrate 108 of the first input transistors Mn1, and gate terminal 112 receives and whether determines the conducting first bias transistor Mn1* according to first clock signal.
Position rank transducer and Fig. 2 A difference of another preferred embodiment of the present invention shown in Fig. 2 B are, the first bias transistor Mp1* is a P-type mos, and the gate terminal 112 of the first bias transistor Mp1* is coupled to the second clock signal, and determines whether conducting according to the second clock signal.
In preferred embodiment of the present invention, transistor seconds group 130 can have polytype, even also can be existing substrate bias circuit.Fig. 3 A to Fig. 3 D expresses the circuit of four kinds of transistor seconds groups of preferred embodiment of the present invention respectively, but all not as limit.
See also shown in Fig. 3 A, first kind of transistor seconds group 130 comprises the second input transistors Mn2 and the second bias transistor Mn2*, is the N type metal oxide semiconductor.This second input transistors Mn2 has drain electrode end 124, source terminal 126, gate terminal 122 and substrate 128, the drain electrode end 124 of the second input transistors Mn2 is coupled to second output 184, source terminal 126 ground connection of the second input transistors Mn2, the gate terminal 122 of the second input transistors Mn2 receives the second clock signal.And the second bias transistor Mn2* has drain electrode end 134, source terminal 136 and gate terminal 132, the drain electrode end 134 of the second bias transistor Mn2* is coupled to the drain electrode end 124 of the second input transistors Mn2, the source terminal 136 of the second bias transistor Mn2* is coupled to the substrate of the second input transistors Mn2, and the gate terminal 132 of the second bias transistor Mn2* is coupled to the gate terminal 122 of the second input transistors Mn2.
See also shown in Fig. 3 B, second kind of transistor seconds group 130 comprises the second input transistors Mn2 and the second bias transistor Mn2*, is the N type metal oxide semiconductor.This second input transistors Mn2 has drain electrode end 124, source terminal 126, gate terminal 122 and substrate 128, the drain electrode end 124 of the second input transistors Mn2 is coupled to second output 184, source terminal 126 ground connection of the second input transistors Mn2, the gate terminal 122 of the second input transistors Mn2 receives the second clock signal.The second bias transistor Mn2* has drain electrode end 134, source terminal 136 and gate terminal 132, the drain electrode end 134 of the second bias transistor Mn2* is coupled to the gate terminal 122 of the second input transistors Mn2, the gate terminal 132 that the source terminal 136 of the second bias transistor Mn2* is coupled to substrate 128, the second bias transistor Mn2* of the second input transistors Mn2 is coupled to the drain electrode end 124 of the second input transistors Mn2.
See also shown in Fig. 3 C, the third transistor seconds group 130 comprises the second input transistors Mn2 and the second bias transistor Mp2*, wherein the second input transistors Mn2 is the N type metal oxide semiconductor, and the second bias transistor Mp2* is a P-type mos.This second input transistors Mn2 has drain electrode end 124, source terminal 126, gate terminal 122 and substrate 128, the drain electrode end 124 of the second input transistors Mn2 is coupled to second output 184, source terminal 126 ground connection of the second input transistors Mn2, the gate terminal 122 of the second input transistors Mn2 receives the second clock signal.And the second bias transistor Mp2* has drain electrode end 134, source terminal 136 and gate terminal 132, the drain electrode end 134 of the second bias transistor Mp2* is coupled to the drain electrode end 124 of the second input transistors Mn2,132 of the gate terminal that the source terminal 136 of the second bias transistor Mp2* is coupled to substrate 128, the second bias transistor Mp2* of the second input transistors Mn2 can be the gate terminal 102 that is coupled to first output 182 or the first input transistors Mn1.
See also shown in Fig. 3 D, the 4th kind of transistor seconds group 130 comprises the second input transistors Mn2 and the second bias transistor Mp2*, wherein the second input transistors Mn2 is the N type metal oxide semiconductor, and the second bias transistor Mp2* is a P-type mos.This second input transistors Mn2 has drain electrode end 124, source terminal 126, gate terminal 122 and substrate 128, the drain electrode end 124 of the second input transistors Mn2 is coupled to second output 184, source terminal 126 ground connection of the second input transistors Mn2, the gate terminal 122 of the second input transistors Mn2 receives the second clock signal.The second bias transistor Mp2* has drain electrode end 134, source terminal 136 and gate terminal 132, the drain electrode end 134 of the second bias transistor Mp2* is coupled to the gate terminal 122 of the second input transistors Mn2,132 of the gate terminal that the source terminal 136 of the second bias transistor Mp2* is coupled to substrate 128, the second bias transistor Mp2* of the second input transistors Mn2 can be the gate terminal 102 that is coupled to first output 182 or the first input transistors Mn1.
Please then consulting shown in Fig. 4 A, is the circuit diagram according to a kind of switching circuit of a preferred embodiment of the present invention again.This switching circuit 140, it comprises the first switching transistor Mp1 and second switch transistor Mp2.This first switching transistor Mp1 has drain electrode end 144, source terminal 146 and gate terminal 142, the drain electrode end 144 of the first switching transistor Mp1 is coupled to voltage source, the gate terminal 142 that the source terminal 146 of the first switching transistor Mp1 is coupled to first output, 182, the first switching transistor Mp1 is coupled to second output 184.Second switch transistor Mp2 has drain electrode end 154, source terminal 156 and gate terminal 152, the drain electrode end 154 of second switch transistor Mp2 is coupled to voltage source, the source terminal 156 of second switch transistor Mp2 is coupled to second output 184, and the gate terminal 152 of second switch transistor Mp2 is coupled to first output 182.
Seeing also shown in Fig. 4 B, is the circuit diagram according to the another kind of switching circuit of a preferred embodiment of the present invention.In the present embodiment, switching circuit 140 comprises the first switching transistor Mp1 and second switch transistor Mp2.Wherein, the first switching transistor Mp1 has drain electrode end 144, source terminal 146 and gate terminal 142, the drain electrode end 144 of this first switching transistor Mp1 is coupled to voltage source, and source terminal 146 and the gate terminal 142 of the first switching transistor Mp1 are coupled to first output 182.And second switch transistor Mp2 has drain electrode end 154, source terminal 156 and gate terminal 152, the drain electrode end 154 of second switch transistor Mp2 is coupled to voltage source, the source terminal 156 of second switch transistor Mp2 is coupled to second output 184, and the gate terminal 152 of second switch transistor Mp2 is coupled to the gate terminal 142 of the first switching transistor Mp1.
When the rank, position of Fig. 2 A transducer 30 is arranged in pairs or groups with the transistor seconds group 130 of Fig. 3 A, its manner of execution is a logic high potential for working as first clock signal, when the second clock signal is logic low potential, the first input transistors Mn1 and the first bias transistor Mn1* are switched on, the second input transistors Mn2 and the second not conducting of bias transistor Mn2*.Therefore, the signal on first output 182 is a logic low potential, and the signal on second output 184 is a logic high potential.At this moment, the substrate 108 of the first input transistors Mn1 is a logic low potential, has set up quiescent biasing voltage in the substrate 128 of the second input transistors Mn2.
When signal begins to change, promptly first clock signal transfers logic low potential to by logic high potential, when the second clock signal transfers logic high potential to by logic low potential, the second input transistors Mn2 and the second bias transistor Mn2* will be switched on, and the signal on second output 184 still is a logic high potential, at this moment, the second input transistors Mn2 has lower critical voltage, conducting fast, to shorten the change-over time of signal, the signal on second output 184 is a logic low potential.
When the rank, position of Fig. 2 B transducer 32 was arranged in pairs or groups with the transistor seconds group 130 of Fig. 3 C, the gate terminal 132 of the second bias transistor Mp2* received first clock signal.The manner of execution of rank, position transducer 32 is a logic high potential for working as first clock signal, when the second clock signal is logic low potential, the first input transistors Mn1 and the first bias transistor Mp1* are switched on, the second input transistors Mn2 and the second not conducting of bias transistor Mp2*.Therefore, the signal on first output 182 is a logic low potential, and the signal on second output 184 is a logic high potential.At this moment, the substrate 108 of the first input transistors Mn1 is a logic low potential, has set up quiescent biasing voltage in the substrate 128 of the second input transistors Mn2.
When signal begins to change, promptly first clock signal transfers logic low potential to by logic high potential, when the second clock signal transfers logic high potential to by logic low potential, the second input transistors Mn2 and the second bias transistor Mp2* will be switched on, and the signal on second output 184 still is a logic high potential, at this moment, the second input transistors Mn2 has lower critical voltage, conducting fast, to shorten the change-over time of signal, the signal on second output 184 is a logic low potential.
In preferred embodiment of the present invention, the position rank transducer of Fig. 2 A and Fig. 2 B can be respectively with Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D in any one transistor seconds group 130 arrange in pairs or groups.The manner of execution in its when collocation is then similar with the manner of execution of above-mentioned various collocation.In addition, it is that benchmark changes that the relation that couples during collocation is then also closed with coupling of above-mentioned various collocation, but all not as limit.
In preferred embodiment of the present invention, when the first bias transistor Mp1* is P-type mos, except above-mentioned connected mode, also can adopt for it in the mode of gate terminal 112 and 182 electric property coupling inverters of first output.
The present invention also can only adopt a bias transistor to provide bias voltage to the substrate of an input transistors, and a circuit of rank transducer is more simplified, and can reach the effect that reduces critical voltage equally.
In preferred embodiment of the present invention, the first transistor group 100, transistor seconds group 130 ought not exceeded with above-mentioned certainly with the combination of switching circuit 140.
Comprehensive the above, rank, position of the present invention transducer is strengthened the substrate biasing to input transistors, thereby can reach the effect of further reduction critical voltage.Therefore can under the condition that does not influence the circuit original function, make that the signal conversion speed is faster, be adapted to the lower voltage of input signal level more.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (11)
1, a kind of rank transducer is electrically coupled to a voltage source, one first clock signal and a second clock signal, comprising:
One switching circuit has one first output and one second output, receives this voltage source; And
One the first transistor group comprises:
One first input transistors, have drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this first input transistors is coupled to this first output, the source terminal ground connection of this first input transistors, and the gate terminal of this first input transistors receives this first clock signal; With
One first bias transistor has drain electrode end, source terminal and gate terminal; And
One transistor seconds group, an end are electrically coupled to this second output, and other end ground connection determines between this second output and the ground with this second clock signal whether conducting;
It is characterized in that, the drain electrode end of this first bias transistor is coupled to this first output, the source terminal of this first bias transistor is coupled to the substrate of this first input transistors, the gate terminal of this first bias transistor receive this first clock signal and this second clock signal one of them.
2, rank, position according to claim 1 transducer is characterized in that wherein said switching circuit comprises:
One first switching transistor has drain electrode end, source terminal and gate terminal, and the drain electrode end of this first switching transistor is coupled to this voltage source, and the source terminal of this first switching transistor and gate terminal are coupled to this first output; And
One second switch transistor, have drain electrode end, source terminal and gate terminal, this second switch transistor drain end is coupled to this voltage source, and the transistorized source terminal of this second switch is coupled to this second output, and the transistorized gate terminal of this second switch is coupled to this first output.
3, rank, position according to claim 1 transducer is characterized in that wherein said switching circuit comprises:
One first switching transistor, have drain electrode end, source terminal and gate terminal, the drain electrode end of this first switching transistor is coupled to this voltage source, and the source terminal of this first switching transistor is coupled to this first output, and the gate terminal of this first switching transistor is coupled to this second output; And
One second switch transistor, have drain electrode end, source terminal and gate terminal, this second switch transistor drain end is coupled to this voltage source, and the transistorized source terminal of this second switch is coupled to this second output, and the transistorized gate terminal of this second switch is coupled to this first output.
4, rank, position according to claim 1 transducer, this first input transistors and this first bias transistor that it is characterized in that wherein said the first transistor group are the N type metal oxide semiconductor, and the gate terminal of this first bias transistor is coupled to this first clock signal.
5, rank, position according to claim 1 transducer, this first input transistors that it is characterized in that wherein said the first transistor group is the N type metal oxide semiconductor, this first bias transistor is a P-type mos, and the gate terminal of this first bias transistor is coupled to this second clock signal.
6, rank, position according to claim 1 transducer is characterized in that wherein said transistor seconds group comprises:
One second input transistors, have drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this second input transistors is coupled to this second output, the source terminal ground connection of this second input transistors, and the gate terminal of this second input transistors receives this second clock signal; And
One second bias transistor, have drain electrode end, source terminal and gate terminal, the drain electrode end of this second bias transistor is coupled to the gate terminal of this second input transistors, the source terminal of this second bias transistor is coupled to the substrate of this second input transistors, the gate terminal of this second bias transistor be coupled to this second output and this first output one of them.
7, rank, position according to claim 6 transducer, this second input transistors and this second bias transistor that it is characterized in that wherein said transistor seconds group are the N type metal oxide semiconductor, and the gate terminal of this second bias transistor is to be coupled to this second output.
8, rank, position according to claim 6 transducer, this second input transistors that it is characterized in that wherein said transistor seconds group is the N type metal oxide semiconductor, this second bias transistor is a P-type mos, and the gate terminal of this second bias transistor is to be coupled to this first output.
9, rank, position according to claim 1 transducer is characterized in that wherein said transistor seconds group comprises:
One second input transistors, have drain electrode end, source terminal, gate terminal and substrate, the drain electrode end of this second input transistors is coupled to this second output, the source terminal ground connection of this second input transistors, and the gate terminal of this second input transistors receives this second clock signal; And
One second bias transistor, have drain electrode end, source terminal and gate terminal, the drain electrode end of this second bias transistor is coupled to this second output, the source terminal of this second bias transistor is coupled to the substrate of this second input transistors, the gate terminal of this second bias transistor be coupled to this second clock signal and this first clock signal one of them.
10, rank, position according to claim 9 transducer, this second input transistors and this second bias transistor that it is characterized in that wherein said transistor seconds group are the N type metal oxide semiconductor, and the gate terminal of this second bias transistor is to be coupled to this second clock signal.
11, rank, position according to claim 9 transducer, this second input transistors that it is characterized in that wherein said transistor seconds group is the N type metal oxide semiconductor, this second bias transistor is a P-type mos, and the gate terminal of this second bias transistor is to be coupled to this first clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101182511A CN100346575C (en) | 2003-12-08 | 2003-12-08 | Bit order converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101182511A CN100346575C (en) | 2003-12-08 | 2003-12-08 | Bit order converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1627643A CN1627643A (en) | 2005-06-15 |
| CN100346575C true CN100346575C (en) | 2007-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101182511A Expired - Fee Related CN100346575C (en) | 2003-12-08 | 2003-12-08 | Bit order converter |
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| CN (1) | CN100346575C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103795397A (en) * | 2012-10-31 | 2014-05-14 | 晨星软件研发(深圳)有限公司 | Level shifter and operational amplifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433076A (en) * | 2002-01-15 | 2003-07-30 | 松下电器产业株式会社 | Level shift circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433076A (en) * | 2002-01-15 | 2003-07-30 | 松下电器产业株式会社 | Level shift circuit |
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| CN1627643A (en) | 2005-06-15 |
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