CN100342418C - Data driven circuit and organic LED displaying device - Google Patents
Data driven circuit and organic LED displaying device Download PDFInfo
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- CN100342418C CN100342418C CNB2004100452448A CN200410045244A CN100342418C CN 100342418 C CN100342418 C CN 100342418C CN B2004100452448 A CNB2004100452448 A CN B2004100452448A CN 200410045244 A CN200410045244 A CN 200410045244A CN 100342418 C CN100342418 C CN 100342418C
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- 238000005070 sampling Methods 0.000 claims abstract description 13
- 239000000872 buffer Substances 0.000 claims description 16
- 241001269238 Data Species 0.000 claims description 10
- 230000004913 activation Effects 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000002401 inhibitory effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 101100015484 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GPA1 gene Proteins 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 101100067427 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FUS3 gene Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
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Abstract
The present invention relates to a data driven circuit. Particularly, a plurality of analog sampling storage circuits are arranged for sharing a digital/analog converter. When a reached corresponding sampling signal is started, a corresponding analog sampling storage circuit can be switched on for storing samples. Therefore, the present invention can avoid difficulty on a circuit layout due to the use of a digital latch when resolution is increased to lead to the increase of a transverse layout area.
Description
Technical field
The present invention is relevant to a kind of data drive circuit, and is relevant to especially a kind of shared D/A conversion circuit, difficulty on the configuration that is caused in the time of can avoiding using the digital phase-locking storage to cause the landscape layout area to increase when the resolution increase passed through.
Background technology
The digital data driver of tradition active matrix organic light-emitting diode (OLED) display uses store buffer (digital phase-locking storage), a signal wire in the cycle as line buffer (linebuffer) in order to the storage data image signal.Figure 1A and 1B show the one 6 figure place font data-driven structures 10 that operate in traditionally under the one time one signal line pattern.Under this structure, retouch in the cycle of sweeping in a level, data image signal is organized in loading in regular turn more, loads the set of number picture signal at first earlier through signal wire R[5]～B[0] by offset buffer SR
nSampled signal control output in the corresponding first order latch 11 (Latch11), then reload next group data image signal through signal wire R[5]～B[0] by buffer SR
N+1Sampled signal control output in the corresponding first order latch 21 (Latch21).Afterwards, control by (linebuffer) " LB " signal, there is the data image signal R[5 in first order latch 11 (Latch11), the latch 21 (Latch21) in all]～B[0] can write in second level latch 12 (Latch12), the latch 22 (Latch22), be put into digital/analog converter DAC-R simultaneously
n, DAC-G
n, DAC-B
nIn.
Because resolution increases, data bits can and then increase, thus account for very much the store buffer of layout area, and the number of digital/analog converter also can be along with increase.Yet under the conventional arrangement mode, numeric type driver layout in the horizontal is more limited.Therefore, when the resolution increase causes the number of store buffer and digital/analog converter to increase, will increase the degree of difficulty on the configuration.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of data drive circuit, by being set, a plurality of analog sample memory circuits replace the conventional digital latch, and share a digital/analog converter, in the time of can avoiding owing to the resolution increase, because needed landscape layout area increases, the degree of difficulty on the configuration that is caused.
For realizing above-mentioned advantage, reach according to purpose of the present invention, the invention provides a kind of data drive circuit, include a plurality of offset buffers, each offset buffer is exported a sampled signal in regular turn in a corresponding cycle; Many data signal lines, these many data signal lines transmit many group second numerical datas in the many groups of period 1 transmission first numerical data when a second round; One digital/analog converter receives these many group first numerical datas and converts the first corresponding analog-converted data to, and receives these second numerical datas and convert the second corresponding analog-converted data to; A plurality of analog sample memory circuits, each analog sample memory circuit are when this period 1, by the sampling activation signal of a correspondence wherein and conducting and one first signal enabling are stored this first analog-converted data; When this second round, start correspondence first simulated data of reading these first analog-converted data by a secondary signal, and receive this sampling activation signal and conducting and these second analog-converted data of this secondary signal startup storage; And when a period 3, read correspondence second simulated data of these second analog-converted data by this first signal enabling; And a plurality of pixels, each pixel receives its pairing first simulated data and the second corresponding simulated data respectively.
The present invention also proposes an Organic Light Emitting Diode (OLED) display, comprising: a plurality of pixels, arrange with the array pattern; Scan driving circuit drives the one-row pixels in these a plurality of pixels in regular turn; One data drive circuit comprises: a plurality of offset buffers, and each offset buffer is exported a sampled signal in regular turn in a corresponding cycle; Many data signal lines, these many data signal lines transmit many group second numerical datas in the many groups of period 1 transmission first numerical data when second round; One digital/analog converter receives and should organize first numerical datas more and convert one first analog-converted data to, and receives these second numerical datas and convert one second analog-converted data to; And a plurality of analog sample memory circuits, each analog sample memory circuit when this period 1, the first corresponding analog-converted data of conducting and one first signal enabling storage by the sampling activation signal of a correspondence wherein; When this second round, start correspondence first simulated data read these first analog-converted data by a secondary signal, and conducting and this secondary signal start these second analog-converted data of storage by this sampling activation signal; And when a period 3, read correspondence second simulated data of these second analog-converted data in respective pixel by this first signal enabling.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
Figure 1A and 1B show conventional digital type data-driven structure;
It shown in Fig. 2 an Organic Light Emitting Diode (OLED) display that is suitable for data drive circuit of the present invention;
It shown in Fig. 3 the block schematic diagram of data drive circuit;
Fig. 4 is the detailed circuit diagram of data drive circuit;
Fig. 5 is the time sequential routine figure of data drive circuit;
The related symbol explanation:
Digital data drives structure～10; Offset buffer～SR
nData image signal～R[5]～B[0]; First order latch 11～Latch11; Second level latch 12～Latch12; Digital/analog converter～DAC-R
n, DAC-G
n, DAC-B
nOffset buffer～SR
N+1First order latch 21～Latch21; Second level latch 22～Latch22; Digital/analog converter～DAC-R
N+1, DAC-G
N+1, DAC-B
N+1Organic Light Emitting Diode (OLED) display～200; Active matrix zone～201; Scan drive circuit～202; Data drive circuit～203; Many data drive signal line～DL1～DLm; Digital/analog converter～3; A plurality of analog sample memory circuit～4_1～4_m; Pixel～6_1～6_m; Switch～SW1～SW12; Transistor MP1～MP3; Voltage source～Vdd; Memory capacitance～C1, C2; Node～N1; First signal～ENB; Secondary signal～XENB; Analog-converted data～I_DAC1, I_DAC2; Sampled signal～SR_n+1, SR_n+2～SR_n+m; Simulated data～I_DATA2, I_DATA2
Embodiment
As shown in Figure 2, for being suitable for an Organic Light Emitting Diode (OLED) display 200 of data drive circuit of the present invention.As shown in Figure 2, Organic Light Emitting Diode (OLED) display 200 has active matrix zone 201, scan driving circuit 202 and a data drive circuit 203 of being lined up by a plurality of pixel at least.Scan drive circuit 202 is in order to drive the one-row pixels in the active matrix zone 201 in order.Data drive circuit 203 arrives respective pixel in order to outputting data signals.
Figure 3 shows that the block schematic diagram of data drive circuit 203 among Fig. 2, data drive circuit 203 comprises many data drive signal line DL1～DLm, a digital/analog converter 3, a plurality of analog sample memory circuit 4_1～4_m, reaches a plurality of pixel 6_1～6_m.
Many data signal line DL1～DLm are in order to transmission of digital data; Digital/analog converter 3 connects this many data signal line DL1～DLm, with numerical data and convert the corresponding simulating translation data to, and Dui Ying current data for example; A plurality of analog sample memory circuit 4_1～4_m, be connected to digital/analog converter 3, can start and conducting by the sampled signal SR_n+1～SR_n+m of correspondence, and in one-period, store the analog-converted data that receive by the control of one first a signal ENB or a secondary signal XENB, and the corresponding simulated data of the analog-converted data in last cycle is read in the control of a secondary signal XENB or one first signal ENB; A plurality of pixel 6_1～6_m are connected to the simulated data that corresponding simulating sampling storage sample circuit 4_1～4_m reads with reception.
Fig. 4 embodiment that passes the imperial examinations at the provincial level, many data signal line DL1～DL6 in this data drive circuit 203 transmit in one 6 the digital/analog converter 3 of 6 of data D0～D65 to, and data drive circuit 203 comprises two analog sample storage sample circuit 4_1 and 4_2.
Analog sample memory circuit 4_1 includes one in order to be used as the transistor MP2 of current source, is arranged between a constant voltage source VDD and the digital/analog converter 3.Be provided with a switch SW 6 (the 6th switch) between the grid of transistor MP2 and drain electrode, and be provided with switch SW 5 (the 5th switch) in drain electrode and 3 of digital/analog converters, switch SW 5 and switch SW 6 can the conductings by the startup of sampled signal SR_n+1.Two memory capacitance C1 and C2, in parallel is arranged between a voltage source V DD and a first node N1, between memory capacitance C1 and first node N1, be provided with a switch SW 1 (first switch), be provided with a switch SW 3 (the 3rd switch) between memory capacitance C2 and first node N1, switch SW 1 can be the state of conducting or shutoff by the control of one first signal ENB; 3 states that are conducting or shutoff by the control of a secondary signal XENB of switch SW.One is used as the transistor MP1 of current source, be arranged between a voltage source V DD and the pixel 6_1, the grid of transistor MP1 is connected respectively to memory capacitance C1 and memory capacitance C2 via switch SW 2 (second switch) and switch SW 4 (the 4th switch), and wherein switch SW 2 can be the state of conducting or shutoff by the control of secondary signal XENB; 4 states that are conducting or shutoff by the control of one first signal ENB of switch SW.
Analog sample memory circuit 4_2 has in order to be used as transistor MP3, the MP4 of current source, two memory capacitance C3 and C4, and switch SW 7～SW10 and SW11, SW12.Its circuit structure is identical with analog sample memory circuit 4_1, does not repeat them here.
During practical operation, because analog sample memory circuit 4_1 is identical with the operation of analog sample memory circuit 4_2,4_1 is an example with the analog sample memory circuit, sees also Fig. 4,5, and wherein Fig. 5 is the time sequential routine figure of data drive circuit 203.At first, at cycle A when (period 1), a plurality of signal wire DL1～DL6 can transmit set of number data D0～D5 (first numerical data) in digital simulation/converter 3 to convert corresponding simulating translation data I_DAC1 (the first analog-converted data) to, for example be a current data.Simultaneously, a for example sampled signal SR_n+1 gauge tap SW5 and a SW6 conducting, the first signal ENB starts and actuating switch SW1 and SW4, and analog-converted data I _ DAC1 promptly stores among the memory capacitance C1 through switch SW 5, SW6 and SW1.
Then enter cycle B (second round), the first signal ENB forbids and stopcock SW1 and SW4, secondary signal XENB starts and actuating switch SW3 and switch SW 2, therefore the analog-converted data I _ DAC1 among the memory capacitance C1 promptly flows to the grid of transistor MP1, transmits corresponding simulating data I _ DATA1 in pixel 6_1 with oxide-semiconductor control transistors MP1.Simultaneously, another group digital data D0～D5 (second numerical data) converts corresponding simulating translation data I_DAC2 (the second analog-converted data) in digital simulation/converter 3, when sampled signal SR_n+1 gauge tap SW5 and SW6 conducting, analog-converted data I _ DAC2 (the second analog-converted data) promptly stores among the memory capacitance C2 through switch SW 5, SW6 and SW3.
Enter cycle C when (period 3), the first signal ENB starts and conducting SW1, SW4, makes analog-converted data among the memory capacitance C2 be connected to the grid of transistor MP1, with oxide-semiconductor control transistors MP1 transmission corresponding simulating data I _ DATA2 in pixel 6_1.
Analog sample memory circuit 4_2 is identical with the principle of operation of analog storage sample circuit 4_1, does not repeat them here, and different is, and it just understands actuating switch SW11 and SW12 during by the SR_n+2 sampling activation signal in the same corresponding cycle.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.
Claims (8)
1. data drive circuit comprises:
A plurality of offset buffers, each offset buffer is exported a sampled signal in regular turn in a corresponding cycle;
Many data signal lines, these many data signal lines transmit many group second numerical datas in the many groups of period 1 transmission first numerical data when a second round;
One digital/analog converter receives and should organize first numerical datas more and convert one first analog-converted data to, and receives described second numerical data and convert one second analog-converted data to;
A plurality of analog sample memory circuits, each analog sample memory circuit when this period 1, the conducting by the sampling activation signal of a correspondence wherein, and these corresponding first analog-converted data of one first signal enabling storage; When this second round, start by a secondary signal and to read pairing one first simulated data of these first analog-converted data, and conducting and this secondary signal start these second analog-converted data of storage by this sampling activation signal; When a period 3, read pairing one second simulated data of these second analog-converted data by this first signal enabling; And
A plurality of pixels, each pixel receive its pairing this first simulated data and this corresponding second simulated data respectively.
2. data drive circuit as claimed in claim 1, wherein this each analog sample memory circuit comprises:
One current source connects between this digital/analog converter and the constant voltage source, and the conducting by this sampled signal control of correspondence;
One first memory capacitance is arranged between this constant voltage source and the first node;
One second memory capacitance is arranged between this constant voltage source and this first node;
One the first transistor has an input end and connects this constant voltage source, and a control end connects this first memory capacitance and this second memory capacitance, and an output terminal;
One first switch is arranged between this first memory capacitance and this first node, in the conducting by this first signal enabling of this period 1, is turn-offed by this first signal-inhibiting in this second round;
One second switch is arranged between this first memory capacitance and this first transistor control end, is forbidden by this secondary signal and turn-offs in this period 1, is started and conducting by this secondary signal in this second round;
One the 3rd switch is arranged between this second memory capacitance and this first node, is forbidden by this secondary signal and turn-offs in this period 1, is started and conducting by this secondary signal in this second round; And
One the 4th switch is arranged between this second memory capacitance and this first transistor control end, in the conducting by this first signal enabling of this period 1, is turn-offed by this first signal-inhibiting in this second round.
3. data drive circuit as claimed in claim 2, this current source comprises a transistor, and this transistor has an input end and connects this constant voltage source, and a control end connects this first node, and an output terminal connects on this digital/analog converter;
One the 6th switch is arranged between this first node and this transistorized output terminal, and controls conducting by this sampled signal of correspondence; And
One the 5th switch is arranged between this transistorized output terminal and the digital/analog converter, and controls conducting by this sampled signal of this correspondence.
4. data drive circuit as claimed in claim 3, wherein this first to the 6th switch is a switching transistor or a transmission gating element.
5. an organic light emitting diode display comprises:
A plurality of pixels are with array format;
Scan driving circuit drives the one-row pixels in these a plurality of pixels in regular turn;
A kind of data drive circuit comprises:
A plurality of offset buffers, each offset buffer is exported a sampled signal in regular turn in the corresponding cycle;
Many data signal lines, these many data signal lines transmit many group second numerical datas in the many groups of period 1 transmission first numerical data when a second round;
One digital/analog converter receives and should organize first numerical datas more and convert one first analog-converted data to, and receives described second numerical data and convert one second analog-converted data to; And
A plurality of analog sample memory circuits, each analog sample memory circuit when this period 1, the conducting by the sampling activation signal of a correspondence wherein, and these corresponding first analog-converted data of one first signal enabling storage; When this second round, start by a secondary signal and to read pairing one first simulated data of these first analog-converted data, and conducting and this secondary signal start these second analog-converted data of storage by this sampling activation signal; When a period 3, read pairing one second simulated data of these second analog-converted data in respective pixel by this first signal enabling.
6. organic light emitting diode display as claimed in claim 5, wherein each analog sample memory circuit comprises:
One current source connects between this digital/analog converter and the constant voltage source, and the conducting by this sampled signal control of correspondence;
One first memory capacitance is arranged between this constant voltage source and the first node;
One second memory capacitance is arranged between this constant voltage source and this first node;
One the first transistor has an input end and connects this constant voltage source, and a control end connects this first memory capacitance and this second memory capacitance, and an output terminal;
One first switch is arranged between this first memory capacitance and this first node, in the conducting by this first signal enabling of this period 1, is turn-offed by this first signal-inhibiting in this second round;
One second switch is arranged between this first memory capacitance and this first transistor control end, is forbidden by this secondary signal and turn-offs in this period 1, is started and conducting by this secondary signal in this second round;
One the 3rd switch is arranged between this second memory capacitance and this first node, is forbidden by this secondary signal and turn-offs in this period 1, is started and conducting by this secondary signal in this second round; And
One the 4th switch is arranged between this second memory capacitance and this first transistor control end, in the conducting by this first signal enabling of this period 1, is turn-offed by this first signal-inhibiting in this second round.
7. organic light emitting diode display as claimed in claim 6, this current source comprises a transistor, and this transistor has an input end and connects this constant voltage source, and a control end connects this first node, and an output terminal connects on this digital/analog converter;
One the 6th switch is arranged between this first node and this transistorized output terminal, and controls conducting by this sampled signal of a correspondence; And
One the 5th switch is arranged between this transistorized output terminal and the digital/analog converter, and controls conducting by this sampled signal of this correspondence.
8. organic light emitting diode display as claimed in claim 7, wherein this first to the 6th switch is a switching transistor or a transmission gating element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100452448A CN100342418C (en) | 2004-06-04 | 2004-06-04 | Data driven circuit and organic LED displaying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100452448A CN100342418C (en) | 2004-06-04 | 2004-06-04 | Data driven circuit and organic LED displaying device |
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| Publication Number | Publication Date |
|---|---|
| CN1584964A CN1584964A (en) | 2005-02-23 |
| CN100342418C true CN100342418C (en) | 2007-10-10 |
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| CNB2004100452448A Expired - Fee Related CN100342418C (en) | 2004-06-04 | 2004-06-04 | Data driven circuit and organic LED displaying device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01174185A (en) * | 1987-12-28 | 1989-07-10 | Sharp Corp | Liquid crystal display device |
| JPH06266314A (en) * | 1993-03-17 | 1994-09-22 | Fujitsu Ltd | Driving circuit of display device |
| US5708452A (en) * | 1995-03-30 | 1998-01-13 | Kabushiki Kaisha Toshiba | Led display device and method for controlling the same |
| US6498596B1 (en) * | 1999-02-19 | 2002-12-24 | Kabushiki Kaisha Toshiba | Driving circuit for display device and liquid crystal display device |
| CN1459085A (en) * | 2001-03-20 | 2003-11-26 | 皇家菲利浦电子有限公司 | Column driving circuit and method for driving pixels in a column row matrix |
-
2004
- 2004-06-04 CN CNB2004100452448A patent/CN100342418C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01174185A (en) * | 1987-12-28 | 1989-07-10 | Sharp Corp | Liquid crystal display device |
| JPH06266314A (en) * | 1993-03-17 | 1994-09-22 | Fujitsu Ltd | Driving circuit of display device |
| US5708452A (en) * | 1995-03-30 | 1998-01-13 | Kabushiki Kaisha Toshiba | Led display device and method for controlling the same |
| US6498596B1 (en) * | 1999-02-19 | 2002-12-24 | Kabushiki Kaisha Toshiba | Driving circuit for display device and liquid crystal display device |
| CN1459085A (en) * | 2001-03-20 | 2003-11-26 | 皇家菲利浦电子有限公司 | Column driving circuit and method for driving pixels in a column row matrix |
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| CN1584964A (en) | 2005-02-23 |
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