Embodiment
The present invention discloses a kind of solenoid valve protective circuit, can effectively prevent solenoid valve because misoperation or short circuit and be in the state of startup for a long time.This solenoid valve protective circuit mainly comprises a logic gate component and a feedback adjusting circuit.Wherein, logic gate can according to the control signal position imported accurate with reference voltage position standard, and export the logical signal of a correspondence, start described solenoid valve.The feedback adjusting circuit then can be according to the logical signal position standard of feedback; progressive adjustment reference voltage position standard, and by logic gate component change logical signal position standard, and reach the effect of closing solenoid valve; with effective protection solenoid valve and peripheral element thereof, avoid causing overheated problem of burning.Relevant of the present invention be described in detail as follows described.
First embodiment:
Please refer to Fig. 2 A, this figure has shown logic gate component in the first embodiment of the invention, feedback adjusting circuit and relevant electromagnetic valve structure.As mentioned above, a transistor Q1 is linked between solenoid valve 10 and the operating voltage source Vcc ', when transistor Q1 conducting, can directly apply operating voltage and start solenoid valve 10 and move.20 of logic gates have first input end x, the second input end y and an output terminal z respectively, and wherein first input end x is linked to a control end, in order to receive a control signal Vx; The second input end y then is linked to a reference voltage source Vcc, in order to receive a reference voltage signal; Output terminal z is linked to the grid of transistor Q1, to export the switch motion of a logical signal Vo with oxide-semiconductor control transistors Q1.
Described feedback adjusting circuit 30 mainly comprises transistor Q2 coupled to each other, capacitor C and three resistor R, Rc and Rb.Wherein, capacitor C is serially connected with between the second input end y and the grounding end, and is accurate in order to the position of adjusting this reference signal.As shown in FIG., first end of this capacitor C is the second input end y that directly is linked to logic gate 20, then is linked to grounding end as for second end of capacitor C.It should be noted that first end of this capacitor C and be connected in above-mentioned reference voltage source Vcc via a resistor R.In addition, two electrode tips of transistor Q2, be to be connected to second input end y and the grounding end respectively, its control electrode end then is linked to the output terminal z of transistor Q1 via the resistor R b of polyphone, and carry out switch according to the position standard of logical signal, whether to determine conducting second input end y and the grounding end.In addition, between the transistor Q2 and the second input end y, and the described resistor R c that contacted.
Still please refer to Fig. 2 A; in this embodiment; employed logic gate 20 is to be an inclusive OR gate (orgate); transistor Q1 then can select to be made of the PMOS transistor; in the selection as for transistor Q2; in order to effectively reduce the cost of whole group protective circuit, then can adopt a NPN transistor to constitute.
In conjunction with above-mentioned inclusive OR gate, PMOS transistor and NPN transistor, when constituting the protective circuit of solenoid valve 10, can obtain the voltage oscillogram shown in Fig. 2 B.Wherein, when the control signal Vx of its first input end of inclusive OR gate x keeps on the throne accurate 1 the time, no matter the reference signal position standard of the second input end y why, the logical signal Vo of output terminal z can keep under accurate 1 the state on the throne, and transistor Q1 is in by section, and allow solenoid valve 10 be in the situation of closing.At this moment, because control signal Vx meeting turn-on transistor Q2, and make the second input end y, and be connected to grounding end via resistor R c, therefore the reference signal position standard of the second input end y can be in relative low potential VL basically, and can be considered the state of position accurate 0.
In case when wanting opens solenoid valve 10 to move, then control signal Vx can be adjusted to position accurate 0 by position standard 1, this moment since the reference signal of the second input end y still at low potential VL (position accurate 0) relatively, be that can to become the position by position standard 1 with the logical signal Vo of output accurate 0, and turn-on transistor Q1 and start solenoid valve 10.Simultaneously, the logical signal Vo of position accurate 0, and can close transistor Q2 via resistor R b, make to begin the electric current that flows into by reference voltage source Vcc capacitor C is charged.
It should be noted that as above-mentioned, when signal source breaks down or during short circuit, by the control signal Vx of first input end x input, under accurate 0 the situation of may being held in place always.At this moment, protective circuit provided by the present invention, the just starting state of switching solenoid valve that can be in good time avoiding under its situation that maintains startup always, and then burns the situation of fusion.Still please refer to Fig. 2 B, when logical signal Vo conducting transistor Q1 and when having closed transistor Q2, capacitor C can begin charging, and make the reference signal current potential of the second input end y, rise gradually and arrive at relative high petential V by low potential VL
HBecause control signal Vx keeps on the throne accurate 0 always, be to rise to high petential V with current potential as the second input end y
HWhen (can be considered position accurate 1), logical signal Vo can be transformed into position standard 1 by position standard 0 at once, and closes transistor Q1 and turn-on transistor Q2.
In case after the transistor Q2 conducting, capacitor C can begin to discharge, and makes the current potential of the second input end y, by relative high petential V
HDescend gradually, up to being reduced to relative low potential V
LThe time, the position that just can change logical signal Vo once again is accurate, simultaneously once more turn-on transistor Q1, close transistor Q2.
Like this, along with the charge and discharge process of capacitor C, the current potential of the may command second input end y is at high low potential V
HWith V
LBetween vibrate periodically repeatedly.And then the logical signal Vo of control output end z, on the throne accurate 0 and position accurate 1 between periodically switch.In such cases, when logical signal Vo was in the state of position accurate 0, the transistor Q1 of conducting just can start solenoid valve 10; Otherwise to switch to the position accurate 1 the time as logical signal Vo, and the transistor Q1 that ends just can close solenoid valve 10.In other words, though control signal Vx owing to reasons such as fault or short circuits, and when continuing to sink into the state of position accurate 0, solenoid valve 10 will can not maintain the state of unlatching always, and can be along with the charge and discharge time of capacitor C, the action that starts or close.
Wanting ben is, by the parameter value of adjusting above-mentioned resistor R and Rc, capacitor C, and can effectively determine the time that solenoid valve 10 starts or cuts out.Wherein, keep the time T ON that solenoid valve 10 starts, that is capacitor C is by low potential V
LCharge to high petential V
HThe required time, can determine by following formula:
T
ON=RC?ln[(Vcc-V
L)/(Vcc-V
H)]
The time T that electromagnetism 10 is closed
OFF, that is capacitor C is by high petential V
HBe discharged to low potential V
LThe required time, then can determine by following formula:
T
OFF=RcC?ln(V
H/V
L)
Like this, the control electromagnetic valve time length of opening or closing accurately, and can guarantee that solenoid valve operates in the operating range of safety.
In addition, in discharge process, the potential drop that can effectively make the second input end y is to relative low level V in order to ensure capacitor C
LTo such an extent as to, when selecting the parameter value of described resistor R and Rc, reference voltage source Vcc transistor Q2, should satisfy following formula:
(Vcc-V
CEsat)*[Rc/(R+Rc)]+V
CEsat<V
L
Wherein, V
CEsatBe its collection of transistor Q2-emitter-base bandgap grading saturated voltage.
Second embodiment:
In above-mentioned first embodiment, shown in Fig. 2 A, use inclusive OR gate, PMOS transistor AND gate NPN transistor to constitute outside the solenoid valve protective circuit, also can select the logic gate of other kind and different transistor units to produce identical protection effect.Please refer to Fig. 3 A, according to a second embodiment of the present invention, logic gate be by one " with " door (AND gate) 22 constitutes, then is made of a nmos pass transistor and a NPN transistor respectively as for transistor Q1, Q2.
Its operation waveform diagram is shown in Fig. 3 B.When " with " door 22 control signal Vx keeps on the throne accurate 0 the time, no matter the reference signal position standard of the second input end y why, the logical signal Vo of output terminal z can keep accurate 0 state on the throne, and nmos pass transistor Q1 is in by section, and allows solenoid valve 10 be in the situation of closing.Simultaneously, NPN transistor Q2 also is in by section, and makes capacitor C carry out charging procedure, and makes the reference signal current potential of the second input end y, maintains relative high petential V
H
When control signal Vx switches to position standard 1 by position standard 0, because the second input end y is still at relative high petential V
H(position accurate 1) is that can to become the position by position standard 0 with logical signal Vo accurate 1, and conducting nmos pass transistor Q1 and start solenoid valve, conducting NPN transistor Q2 makes capacitor C carry out discharge procedures via resistor R b simultaneously.At this moment, even control signal Vx keeps accurate 1 state on the throne always, Only wants capacitor C continuous discharge and makes the potential drop of the second input end y be low to moderate V
L, then logical signal Vo can be transformed into position standard 0 by position standard 1 at once, and closes transistor Q1 and transistor Q2, and makes solenoid valve enter closed condition.After closing NPN transistor Q2, capacitor C can carry out charging procedure once again, and increases by the current potential of the second input end y gradually.When being promoted to high petential V once more
H(position accurate 1) just can restart solenoid valve.That is along with the charge and discharge process of capacitor C, the current potential of the may command second input end y is at current potential V
HWith V
LBetween periodically vibration, and then make between logical signal Vo on the throne accurate 0 and 1 periodically switching, so that periodically start or close solenoid valve.
The 3rd embodiment:
In the third embodiment of the present invention, please refer to shown in Fig. 4 A, then logic gate can be selected to be made of a zero match gate (NOR gate) 24, then is made of a nmos pass transistor and a PNP transistor respectively as for transistor Q1, Q2.Its oscillogram is shown in Fig. 4 B, and when the control signal Vx of zero match gate 24 keeps on the throne accurately 1 the time, logical signal Vo can keep accurate 0 state on the throne, and nmos pass transistor Q1 is in by section, and allows solenoid valve 10 be in the situation of closing.Simultaneously, PNP transistor Q2 then can be on state, and makes capacitor C carry out discharge procedures, and makes the second input end y maintain relative low potential V
L
When control signal Vx switches to position standard 0 by position standard 1, because the second input end y is still at relative low potential V
L(position accurate 0) is that can to become the position by position standard 0 with logical signal Vo accurate 1, and conducting nmos pass transistor Q1 and start solenoid valve closes PNP transistor Q2 via resistor R b simultaneously, makes capacitor C begin to carry out charging procedure.When capacitor C continues charging and makes the current potential of the second input end y be increased to V
HThe time, then logical signal Vo can be at once to be transformed into the position by position standard 1 accurate 0, make solenoid valve enter closed condition and close transistor Q1, simultaneously turn-on transistor Q2 and make capacitor C enter discharge procedures once again.Along with the charge and discharge process of capacitor C, the current potential of the second input end y can be at current potential V
HWith V
LBetween periodically vibration, and periodically start or close solenoid valve.
The 4th embodiment:
In the fourth embodiment of the present invention, please refer to shown in Fig. 5 A, logic gate is to be made of a NOT AND gate (NAND gate) 26, then is made of PMOS transistor AND gate one PNP transistor respectively as for transistor Q1, Q2.Its oscillogram is shown in Fig. 5 B, when the control signal Vx of NOT AND gate 22 keeps on the throne accurate 0 the time, no matter the reference signal position standard of the second input end y why, the logical signal Vo of output terminal z ' can keep accurate 1 state on the throne, and PMOS transistor Q1 is in by section, and allow solenoid valve 10 be in the situation of closing.Simultaneously, PNP transistor Q2 also is in cut-off state, and makes capacitor C carry out charging procedure, and makes the reference signal current potential of the second input end y, maintains relative high petential V
H
When control signal Vx switches to position standard 1 by position standard 0, because the second input end y is still at relative high petential V
H(position accurate 1) is that can to become the position by position standard 1 with logical signal Vo accurate 0, and conducting PMOS transistor Q1 and start solenoid valve, conducting PNP transistor Q2 makes capacitor C carry out discharge procedures via resistor R b simultaneously.At this moment, even control signal Vx keeps accurate 0 state on the throne always, as long as capacitor C continuous discharge and make the potential drop of the second input end y be low to moderate V
L, then logical signal Vo can be transformed into position standard 1 by position standard 0 at once, and closes transistor Q1 and Q2, and makes solenoid valve enter closed condition.After closing PNP transistor Q2, capacitor C can carry out charging procedure once again, and increases by the current potential of the second input end y gradually.When being promoted to high petential V once more
H(position accurate 1) just can restart solenoid valve.That is along with the charge and discharge process of capacitor C, the current potential of the may command second input end y is at current potential V
HWith V
LBetween periodically vibration, and periodically start or close solenoid valve.
Understand the compute mode of above-mentioned each logic gate for convenience, and enclose the truth table of interrelated logic door herein.Please refer to Fig. 6 A, this figure has shown the relation of inclusive OR gate and its input of zero match gate and output value.Wherein, x and y have represented two input ends of logic gate respectively, have then represented the output value of inclusive OR gate as for z, and z ' has then represented the output value of zero match gate.As for Fig. 6 B, then shown " with " input and the output relation of door and NOT AND gate.Wherein, x and y have represented two input ends of logic gate equally, as for z then represented " with " the corresponding output value of door, z ' has then represented the corresponding output value of NOT AND gate.
Protective circuit provided by the present invention has considerable advantage.At first, because the output signal of logic gate only can be that the position standard is 0 or 1 duality signal, the action meeting of so conducting/close transistor Q1 and startup/stop solenoid valve is more clear and definite.Can effectively solve in the conventional art like this, because control signal Vx current potential is indeterminate, institute causes the also indefinite problem of solenoid valve action.Secondly; even control end breaks down or short circuit, and make control signal Vx maintain the accurate state in position of startup solenoid valve, protective circuit of the present invention also can be via the feedback signal of transistor Q2 always; make capacitor carry out charge and discharge actions, and the startup of control electromagnetic valve or close.And,, further the startup or the shut-in time of control electromagnetic valve, burn to prevent its long-time conducting by the charge and discharge time of adjusting capacitor.In other words,, can promote the stability and the reliability of Related product operation, and reach the effect that prolongs life of product by solenoid valve protective circuit of the present invention.
Though the present invention illustrates as above with preferred embodiments, yet it is not that the present invention only limits to described embodiment in order to qualification spirit of the present invention and invention scope.For example, in above-mentioned each embodiment, though be to constitute required transistor Q1, and come transistor formed Q2, be familiar with the present technique personnel and can understand and utilize other element or mode to produce identical effect easily with PNP or NPN transistor with PMOS or nmos pass transistor.For example, also can utilize MOS transistor to constitute above-mentioned transistor Q2 etc.Therefore, equivalent modifications of being done in not breaking away from spirit of the present invention and scope or equivalence are replaced, and all should be included in the following claim institute restricted portion.