CN100338758C - Method for mfg. selective local self-aligned silicide - Google Patents
Method for mfg. selective local self-aligned silicide Download PDFInfo
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- CN100338758C CN100338758C CNB021031657A CN02103165A CN100338758C CN 100338758 C CN100338758 C CN 100338758C CN B021031657 A CNB021031657 A CN B021031657A CN 02103165 A CN02103165 A CN 02103165A CN 100338758 C CN100338758 C CN 100338758C
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Abstract
The present invention provides a method for manufacturing the selective local self-aligning silicide. Firstly, one layer of conformal blocking layer is covered on a storage unit with the narrow gap. Secondly, the other blocking layer is formed on a substrate to cover the storage unit area and a logic circuit area. Thirdly, the back etching step is carried out to expose a polycrystalline silicon grid and a silicon substrate to be formed into the self-aligning silicide. The blocking layer between the grid of the storage unit area, and a blocking layer on an isolated area are kept. The local self-aligning silicide is selectively formed.
Description
Technical field
The invention relates to the manufacture method of a kind of self-aligned silicide (Self Align Silicide, abbreviation Salicide), and particularly relevant for the manufacture method of local (Partial) self-aligned silicide of a kind of selectivity (Selectivity).
Background technology
In the integrated circuit technique of deep-sub-micrometer, because in live width, contact area and connect under all diminishing situation such as the face degree of depth, in order to improve the work quality of element effectively, reduce resistance and reduce the signal propagation delay (RC Delay) that resistance and electric capacity cause, therefore when making grid, on the polycrystalline series grid, form layer of metal silicide (Silicide).
Owing to do not need in the technology of metal silicide to develop, so the metal silicide of being made by this class technology is called self-aligned metal silicate again.Figure 1A to Fig. 1 C is the manufacturing process profile that known selective local forms self-aligned silicide.
Please refer to Figure 1A, memory cell areas 102 and logic circuit area 104 in substrate 100, have been formed with, between memory cell areas 102 and logic circuit area 104, make electrical isolation, and the grid 106a gap of memory cell areas 102 is narrower than the grid 106b gap of logic circuit area 104 with isolated area 103.In addition, grid 106a and 106b sidewall also comprise clearance wall 108.
Please continue with reference to Figure 1A, in substrate 100, cover layer of oxide layer 110, utilize then and develop and etch process, in substrate 100, form patterning photoresist layer 112, to expose the position that desire forms self-aligned silicide.Yet becoming because the grid 106a gap of memory cell areas 102 dwindles with component size is rather narrow, so misalignment (Misalign) phenomenon shown in Figure 1A takes place easily.
Then, please refer to Figure 1B, with the predetermined zone that does not form self-aligned silicide in the memory cell areas 102, for example the oxide layer 110a that is covered on flush type drain region (not illustrating) stays, with as the self-aligned silicide barrier layer, the then removal of oxide layer 110 that other zone covered.Then, remove patterning photoresist layer 112.Because out-of-alignment situation has taken place in photoresist layer 112 before, thus formerly should cover the substrate 100 that exposes between grid 106a, and the oxide layer 110a that stays is present on the part of grid pole 106a, and make the substrate 100 of part expose out.
Then, please refer to Fig. 1 C, in the substrate 100 and the last formation of grid 106a, the 106b self-aligned silicide 114 that expose.Owing to form easily self-aligned silicide 114 in the substrate 100 of memory cell areas 102, institute and increases the difficulty of manufacture process so that its process margin significantly reduces.And after live width was dwindled gradually, the misalignment that said method caused was with even more serious.
Summary of the invention
Therefore, purpose of the present invention just provides a kind of manufacture method of selective local self-aligned silicide, to prevent out-of-alignment generation.
A further object of the present invention provides a kind of manufacture method of selective local self-aligned silicide, can have bigger process margin than known method.
According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method of selective local self-aligned silicide, and the mode of mainly utilizing for two stages formed the barrier layer forms the barrier layer of self-aligned silicide, to carry out local self-aligned silicide technology.Its technology at first covers the conformal barrier layer of one deck earlier on the narrower memory cell areas in the gap between grid, then, form another layer barrier layer again in substrate, to cover memory cell areas and logic circuit area.Then, carry out the etch-back step again, the grid and the silicon base that make desire form self-aligned silicide come out, and only stay the barrier layer between its grid of memory cell areas, that is to say the barrier layer of top, flush type drain region, optionally to form local self-aligned silicide.
The present invention proposes a kind of manufacture method of selective local self-aligned silicide again, provide the substrate that comprises first element region and second element region, wherein first element region has first projection and first depression, second element region has second projection and second depression, and the width of first depression is less than the width of second depression.In substrate, form first barrier layer then, with first projection and first depression that covers first element region.Then, in substrate, form second barrier layer,, wherein be covered in the thickness of the thickness on first first barrier layer of caving in and second barrier layer greater than first barrier layer that is covered in first projection and second barrier layer to cover first element region and second element region.Then, carry out etch-back,, in substrate, form a metal level again, to cover first element region and second element region so that the surface exposure of first raised surface, second projection and second depression comes out.Then, carry out a heat treatment, make metal level carry out silicification reaction, and on the surface of first projection, second projection and second depression, form a self-aligned metal silicate.Remove the part that metal level has neither part nor lot in reaction at last.
Described according to embodiments of the invention, earlier utilizing isolated area to be divided into several polysilicon gates of formation in the substrate of memory cell areas and logic circuit area, and the gap between the grid of memory cell areas is significantly less than the gap of logic circuit area.On the narrower memory cell areas in gap, cover the first conformal barrier layer of one deck then earlier, gap width between its grid of memory cell areas is dwindled, increase the difference of the gap pass width of key (SpaceCD) between memory cell areas and logic circuit area two regional grids.Then, in substrate, form second barrier layer again, to cover memory cell areas and logic circuit area.Then, carry out the etch-back step again, the polysilicon gate and the silicon base that make desire form self-aligned silicide are exposed, and only stay first barrier layer on the gap between the grid of memory cell areas, with first barrier layer of isolated area top, optionally to form local self-aligned silicide.
Because first barrier layer of the present invention is to cover the whole memory unit district, and on the isolated area of electrical isolation memory cell areas and logic circuit area, therefore, when misalignment takes place, can't make the substrate between the memory cell areas grid expose out, such as the flush type drain region.
The mode that the present invention utilized for two stages formed the barrier layer forms the self-aligned silicide barrier layer, and to carry out local self-aligned silicide technology, comparable known method has bigger process margin.
Description of drawings
Figure 1A to Fig. 1 C is the manufacturing process profile that known selective local forms self-aligned silicide; And
Fig. 2 A to Fig. 2 F is the manufacturing process profile according to the selective local self-aligned silicide of one embodiment of the invention.
Description of reference numerals:
100,200: substrate
102,202: memory cell areas
103,203: isolated area
104,204: logic circuit area
106a, 106b, 206a, 206b: grid
108,208: clearance wall
110: oxide layer
112,212: photoresist layer
114: self-aligned silicide
210,214: the barrier layer
216: the selective local self-aligned silicide
Embodiment
Fig. 2 A to Fig. 2 F is the manufacturing process profile according to the selective local self-aligned silicide of one embodiment of the invention.
Please refer to Fig. 2 A, at first provide one to utilize isolated area 203 to be divided into the substrate 200 of memory cell areas 202 and logic circuit area 204.Then, in substrate 200, form several grids 206a, 260b, and the gap between the grid 206a of memory cell areas 202 is narrower than the grid 206b gap of logic circuit area 204.In addition, also comprise formation clearance wall 208 in grid 206a and 206b sidewall.
Then, please refer to Fig. 2 B, in substrate 200, form the first conformal barrier layer 210 of one deck; for example photoresist is protected oxide layer (Resist Protect Oxide; be called for short PRO), its material is silica for example, to cover memory cell areas 202 and logic circuit area 204.First barrier layer 210 on memory cell areas 202 can make the gap width between grid 206a dwindle, and increases the difference of the gap pass width of key (Space CD) between memory cell areas 202 and logic circuit area 204 liang of regional grid 206a, 206b.
Then, please refer to Fig. 2 C, form a photoresist layer 212 on memory cell areas 202, and expose first barrier layer 210 of logic circuit area 204, wherein photoresist layer 212 for example is a photoresist layer.Subsequently, be etching mask with photoresist layer 212, remove first barrier layer 210 of logic circuit area 204.
Then, please refer to Fig. 2 D, remove photoresist layer 212, form second barrier layer 214 again in substrate 200, to cover memory cell areas 202 and logic circuit area 204, wherein the material on second barrier layer 214 for example is a silica.And the thickness that is covered in first barrier layer 210 in the gap between grid 206a and second barrier layer 214 is greater than first barrier layer 210 that is covered in grid 206a and the thickness on second barrier layer 214.
Subsequently, please refer to Fig. 2 E, etch-back is removed second barrier layer 214 of logic circuit area 204, grid 206a, the 206b and the substrate 200 that make desire form self-aligned silicide are exposed, and only stay the barrier layer 210a in the gap between the grid 206a of memory cell areas 202 and the barrier layer 210a of isolated area 203 tops.
At last, please refer to Fig. 2 F, form optionally local self-aligned silicide 216 in the substrate 200 of and logic circuit area 204 last in grid 206a, 206b, its technology for example is, in substrate 200, form the layer of metal layer, its material is titanium for example, to cover memory cell areas 202 and logic circuit area 204.Heat-treat then and make metal level carry out silicification reaction, to form a self-aligned metal silicate on grid 206a, the 206b with in the substrate 200 of logic circuit area 204, remove the part that metal level has neither part nor lot in reaction subsequently, can obtain local self-aligned silicide 216.
In sum, the invention is characterized in:
1. the present invention utilizes first barrier layer to cover the whole memory unit district, and on the isolated area of electrical isolation memory cell areas and logic circuit area, therefore, when misalignment takes place, can't make the substrate between the memory cell areas grid expose out, such as the flush type drain region.
2. the present invention is that the mode of utilizing for two stages formed the barrier layer forms the self-aligned silicide barrier layer, and to carry out local self-aligned silicide technology, comparable known method has bigger process margin.
Though the present invention with embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claims.
Claims (9)
1. the manufacture method of a selective local self-aligned silicide, it is characterized by: its step comprises:
One substrate is provided, comprise a memory cell areas and a logic circuit area in this substrate, wherein this memory cell areas has a first grid and one first gap, and this logic circuit area has a second grid and one second gap, and the width in this first gap is less than the width in this second gap;
In this substrate, form one first barrier layer, with this first grid and this first gap that covers this memory cell areas;
In this substrate, form one second barrier layer, to cover this memory cell areas and this logic circuit area, the thickness that wherein is covered in this first barrier layer in this first gap and this second barrier layer is greater than this first barrier layer that is covered in this first grid and the thickness on this second barrier layer;
Carry out etch-back, so that the surface exposure in the surface of this first grid, this second grid and this second gap comes out;
In this substrate, form a metal level, to cover this memory cell areas and this logic circuit area;
Carry out a heat treatment, make this metal level carry out a silicification reaction, on the surface in this first grid, this second grid and this second gap, to form a self-aligned metal silicate; And
Remove the part that this metal level has neither part nor lot in this silicification reaction.
2. the manufacture method of selective local self-aligned silicide as claimed in claim 1 is characterized by: the step that wherein forms this first barrier layer in this substrate comprises:
In this substrate, form a barrier material layer, to cover this memory cell areas and this logic circuit area;
In this substrate, form a photoresist layer, to cover this memory cell areas;
With this photoresist layer is mask, removes not this barrier material layer by this photoresist layer covered; And
Remove this photoresist layer.
3. the manufacture method of selective local self-aligned silicide as claimed in claim 1 is characterized by: wherein the material on this first and second barrier layer comprises silica.
4. the manufacture method of selective local self-aligned silicide as claimed in claim 1 is characterized by: wherein the material of this metal level comprises titanium.
5. the manufacture method of a selective local self-aligned silicide, it is characterized by: its step comprises:
One substrate is provided, and this substrate has an isolated area, this isolated area electrical isolation one memory cell areas and a logic circuit area;
In this substrate, form a plurality of grids, and in the gap between those grids of this memory cell areas less than the gap between those grids of this logic circuit area;
On this memory cell areas, form one first barrier layer, to cover this memory cell areas;
In this substrate, form one second barrier layer, to cover this memory cell areas and this logic circuit area, the thickness that wherein is covered in this first barrier layer in the gap between those grids of this memory cell areas and this second barrier layer is greater than this first barrier layer on those grids that are covered in this memory cell areas and the thickness on this second barrier layer;
Carry out etch-back, this substrate of those grids and this logic circuit area is come out; And
This substrate surface in those grids that expose and this logic circuit area forms a self-aligned metal silicate.
6. the manufacture method of selective local self-aligned silicide as claimed in claim 5 is characterized by: this step that wherein forms this first barrier layer on this memory cell areas comprises:
In this substrate, form a barrier material layer, to cover this memory cell areas and this logic circuit area;
In this substrate, form a photoresist layer, to cover this memory cell areas;
With this photoresist layer is mask, removes not this barrier material layer by this photoresist layer covered; And
Remove this photoresist layer.
7. the manufacture method of selective local self-aligned silicide as claimed in claim 5 is characterized by: wherein the material on this first and second barrier layer comprises silica.
8. the manufacture method of selective local self-aligned silicide as claimed in claim 5 is characterized by: wherein, form this step of this self-aligned metal silicate in this substrate surface of those grids that expose and this logic circuit area, comprising:
In this substrate, form a metal level, to cover this memory cell areas and this logic circuit area;
Carry out a heat treatment, make this metal level carry out silicification reaction, form a self-aligned metal silicate with surface in this substrate of those grids that expose and this logic circuit area; And
Remove the part that this metal level has neither part nor lot in reaction.
9. the manufacture method of selective local self-aligned silicide as claimed in claim 8 is characterized by: wherein the material of this metal level comprises titanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB021031657A CN100338758C (en) | 2002-02-01 | 2002-02-01 | Method for mfg. selective local self-aligned silicide |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021031657A CN100338758C (en) | 2002-02-01 | 2002-02-01 | Method for mfg. selective local self-aligned silicide |
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| CN1435875A CN1435875A (en) | 2003-08-13 |
| CN100338758C true CN100338758C (en) | 2007-09-19 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005167116A (en) * | 2003-12-05 | 2005-06-23 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| CN100390964C (en) * | 2004-11-03 | 2008-05-28 | 力晶半导体股份有限公司 | Nonvolatile memory and manufacturing method thereof |
| CN100452324C (en) * | 2005-11-08 | 2009-01-14 | 上海华虹Nec电子有限公司 | A method to etch barrier layer of self-alignment refractory metal silicide |
| CN101202247A (en) | 2006-12-14 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | MOS device structure and method of manufacture |
| CN101826524B (en) * | 2009-03-06 | 2012-05-23 | 宜扬科技股份有限公司 | NOR type flash memory structure with highly doped drain region and manufacturing method thereof |
| CN101826525B (en) * | 2009-03-06 | 2011-10-05 | 宜扬科技股份有限公司 | NOR type flash memory structure with double ion implantation and manufacturing method thereof |
| CN102446734A (en) * | 2010-10-14 | 2012-05-09 | 上海华虹Nec电子有限公司 | Grid electrode structure and method |
| CN104465519B (en) * | 2013-09-23 | 2017-07-28 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of embedded source/drain MOS transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705417A (en) * | 1996-06-19 | 1998-01-06 | Vanguard International Semiconductor Corporation | Method for forming self-aligned silicide structure |
| US6180477B1 (en) * | 1999-03-02 | 2001-01-30 | United Silicon Incorporated | Method of fabricating field effect transistor with silicide sidewall spacers |
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2002
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705417A (en) * | 1996-06-19 | 1998-01-06 | Vanguard International Semiconductor Corporation | Method for forming self-aligned silicide structure |
| US6180477B1 (en) * | 1999-03-02 | 2001-01-30 | United Silicon Incorporated | Method of fabricating field effect transistor with silicide sidewall spacers |
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