CN100336208C - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN100336208C
CN100336208C CNB2004100452293A CN200410045229A CN100336208C CN 100336208 C CN100336208 C CN 100336208C CN B2004100452293 A CNB2004100452293 A CN B2004100452293A CN 200410045229 A CN200410045229 A CN 200410045229A CN 100336208 C CN100336208 C CN 100336208C
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CN
China
Prior art keywords
support substrate
semiconductor device
backplate
substrate
semiconductor element
Prior art date
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Expired - Fee Related
Application number
CNB2004100452293A
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Chinese (zh)
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CN1574303A (en
Inventor
三田清志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1574303A publication Critical patent/CN1574303A/en
Application granted granted Critical
Publication of CN100336208C publication Critical patent/CN100336208C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

This invention provides a semiconductor device which prevents damage caused by a thermal stress. The semiconductor device 10A is composed of a supporting substrate 11, a front side electrode 13 and a back side electrode 14 respectively formed on a front side surface and a back side surface of the supporting substrate and connected by a via hole 15, a semiconductor element 16 fixedly mounted on the front side surface of the supporting substrate 11 and electrically connected to the front side electrode 13, and a sealing resin 18 which seals the semiconductor element 16. The back side surface of the supporting substrate 11 is provided with slots 12. With this arrangement, cracks caused by a thermal stress are prevented from occurring at the junctions of via holes 15 and the front side electrodes 14, or the junctions of the via holes 15 and the back side electrodes.

Description

Semiconductor device
Technical field
The present invention relates to have the semiconductor device of support substrate.
Background technology
With reference to Fig. 5 existing substrate and the semiconductor device installed is described.Fig. 5 (A) is the profile of semiconductor device 100, and Fig. 5 (B) is its back view (with reference to a patent documentation 1).
With reference to Fig. 5 (A), the electrode 104 that formation is made of Copper Foil etc. on the support substrate 101 of formations such as glass epoxy resin.Be formed with backplate 105 at the back side of support substrate 101, utilize metallisation interlayer hole 106 to be connected with electrode 104.Electrode 104 and backplate 105 are covered by plated film.
Semiconductor element 102 is fixed on the support substrate 101, utilizes metal fine 103 to be connected with electrode 104.In addition, lining semiconductor element 102 forms sealing resin 107.
With reference to Fig. 5 (B),, be provided with two row backplates 105 with the arrangement of peripheral part parallel lines at the back side of support substrate 101.
Patent documentation 1: the spy opens flat 11-233688 communique (with reference to Fig. 7).
Above-mentioned semiconductor device 100 is to be installed in by the solder flux that is formed at backplate 105 to install on the substrate.But, because thermal expansion coefficient difference is very big between semiconductor element of adorning in the semiconductor device 100 102 and the installation substrate, so can produce thermal stress because of variations in temperature.At present, be to relax this thermal stress by support substrate 101 and solder flux.But in order to promote the mitigation of 101 pairs of thermal stress of support substrate, must make support substrate 101 form thicklyer, this has hindered the slimming of semiconductor device.In addition, because the effect of thermal stress, also existence comprises the ruined problem of connection line of the connecting portion of metallisation interlayer hole 106 and electrode 104.
Summary of the invention
The present invention develops in view of the above problems, and main purpose of the present invention is to provide a kind of semiconductor device that prevents the destruction that thermal stress causes.
Semiconductor device of the present invention comprises: support substrate; Be formed at the surface and the back side of described support substrate, by the surface electrode and the backplate of breakthrough part connection; Be fixed on the surface of described support substrate the semiconductor element that is electrically connected with described surface electrode; Seal the sealing resin of described semiconductor element, the back side of described support substrate is provided with groove.
In addition, in the present invention, the rectangular back side that is formed at described support substrate of described backplate, described groove is clathrate and is arranged between the described backplate.
Among the present invention, described groove is formed at the pars intermedia between the described backplate.
Semiconductor device of the present invention is by installing solder flux on the substrate attached to being installed on the described backplate.
Description of drawings
Fig. 1 is the profile (A) of explanation semiconductor device of the present invention, back view (B);
Fig. 2 is the profile (A) of explanation semiconductor device of the present invention, profile (B);
Fig. 3 is the profile of explanation semiconductor device of the present invention;
Fig. 4 is the profile (A)～(D) of the manufacture method of explanation semiconductor device of the present invention;
Fig. 5 is the profile (A) of the existing semiconductor device of explanation, back view (B).
Embodiment
The structure of semiconductor device 10 of the present invention is described with reference to Fig. 1.Fig. 1 (A) is the profile of semiconductor device 10, and Fig. 1 (B) is its back view.
With reference to Fig. 1 (A), semiconductor device 10A of the present invention comprises: support substrate 11; Be formed at the surface and the back side of support substrate, by the surface electrode 13 and the backplate 14 of breakthrough part 15 connections; Be fixed on the surface of support substrate 11 semiconductor element 16 that is electrically connected with surface electrode 13; The sealing resin 18 of sealing semiconductor element 16 is provided with groove at the back side of support substrate 11.The following describes the detailed content of these key elements.
Support substrate 11 has the effect of each structural element of supporting semiconductor device 10, for example is made of glass epoxy substrate.The material of support substrate 11 also can be the substrate beyond the glass epoxy substrate, also can be with other organic material as its material.At this, support substrate 11 has the individual layer distribution structure, but the support substrate 11 of formation multi-layer wiring structure also can.
Surface electrode 13 is made of conductive material, is formed on the surface of support substrate 11.Surface electrode 13 forms the welding disk that connects metal fine 17, also constitutes the wiring part that is looped around semiconductor element 16 belows.
Backplate 14 is formed at the back side of support substrate 11, is electrically connected with surface electrode 13 by the breakthrough part 15 that connects support substrate 11.
Semiconductor element 16 is LSI (large scale integrated circuit (Large Scale Integration)) chips, by bonding agent 19, is fixed on the surface of support substrate 11 with the bonding method that faces up.The extraction electrode of semiconductor element 16 and surface electrode 13 are electrically connected by metal fine 17.Also can will be loaded on semiconductor device 10 in the element beyond the semiconductor element.
Sealing resin 18 is overlayed on the surface of semiconductor element 16, metal fine 17 and support substrate 11.Sealing resin 18 can adopt the light-proofness resin of having sneaked into inorganic filler in order to improve mechanical strength and moisture-proof.The resin that is used for sealing resin 18 can wholely adopt thermoplastic resin or thermosetting resin.
Groove 12 forms by half scribing is carried out at support substrate 11 back sides, is arranged near the pars intermedia between the backplate 14.With reference to Fig. 1 (B), backplate 14 forms rectangular, can realize BGA (welded ball array (Ball Grid Array)) or LGA (pad array (Land Grid Array)) structure.Groove 12 is clathrate and is formed between backplate 14 that each is gone and each is listed as.
The mounting structure of above-mentioned semiconductor element 14 is described with reference to Fig. 2.With reference to Fig. 2 (A), the surface that substrate 20 is installed is formed with conductive path 21.By solder flux 22 attached to backplate 14 back sides, the conductive path 21 of connection substrate 20 and semiconductor device 10.At this, solder flux 22 can adopt scolding tin etc.
In be loaded on the semiconductor element 16 of semiconductor device 10 and substrate 20 thermal coefficient of expansions be installed and differ greatly.Specifically, the thermal coefficient of expansion of semiconductor element 16 is about 2ppm, substrate 20 is installed under situation about being formed from a resin, and its thermal coefficient of expansion is about 20ppm.Therefore, because the variations in temperature under the behaviour in service when semiconductor device 10 is heated with installation substrate 20, is installed substrate 20 and compared with semiconductor element 16, swell increment is very big.Therefore, place conductive path 21, solder flux 22, backplate 14, breakthrough part 15, support substrate 11 and surface electrode 13 between semiconductor element 16 and the installation substrate 20 can produce thermal stress.In the present invention, by groove 12 is set, reduced this thermal stress on support substrate 11.
The details of groove 12 is described with reference to Fig. 2 (B).As mentioned above, the thermal coefficient of expansion of semiconductor element 16 is for installing about 1/10th of substrate.Therefore, after semiconductor element 16 and installation substrate 20 both temperature all rose, installation substrate 20 was compared with semiconductor element 16 and is had very big expansion, so can produce big thermal stress on support substrate 11 or breakthrough part 15.Specifically, can on support substrate 11 or breakthrough part 15, act on big shearing force.In the present invention,, make near the support substrate the position that forms backplate 14 movable, reduced the thermal stress that acts on support substrate 11 or breakthrough part 15 by on support substrate 11, groove being set.With reference to last figure, the support substrate 11 that is provided with the position of groove 12 is out of shape to the right.Like this, do the time spent, make the support substrate 11 at the position that is provided with backplate 14 laterally movable, and formed groove 12 in order to make in thermal stress.By making support substrate 11 local movable, can prevent that the connecting portion of breakthrough part 15 and surface electrode 13 or the connecting portion of breakthrough part 15 and backplate 14 from peeling off.
Even at semiconductor device 10 with when the thermal stress that effect is big between the substrate 20 is installed, also can absorb this thermal stress by making near the support substrate the backplate 14 laterally movable.In addition, in existing semiconductor device,, make support substrate form very thickly in order to absorb above-mentioned thermal stress, but according to structure of the present invention, but attenuate support substrate 11.In the above description, the degree of depth of groove 12 be set to until the thickness of support substrate 11 midway till, but also groove 12 can be formed the degree of depth that support substrate 11 is wanted separated degree.
With reference to Fig. 3, the structure of the semiconductor device 10B of alternate manner is described.The basic structure of semiconductor device 10B is with identical with reference to the semiconductor device of Fig. 1 explanation, and difference is that semiconductor element 16 is in the mode of facing down, and installs with flip-chip.Even under the situation of the semiconductor device 10B with this structure, also can realize the effect that the formation of above-mentioned groove 12 brings.
The manufacture method of semiconductor device 10B is described with reference to Fig. 4.With reference to Fig. 4 (A), form surface electrode 13 and backplate 14 at the surface and the back side of support substrate 11.Surface electrode 13 and backplate 14 are by connecting breakthrough part 15 electrical connections that support substrate 11 forms.
With reference to Fig. 4 (B), carry out the fixed installation of semiconductor element 16 by bonding agent 19, by metal fine 17 electrode of semiconductor element 16 and surface electrode 14 are electrically connected.
With reference to Fig. 4 (C), form sealing resin 18 in the mode of lining semiconductor element 16 and metal fine 17.The formation method of sealing resin 18 can consider to transmit that mould is molded, injection mould is molded and potting etc.
With reference to Fig. 4 (D),, form groove 12 by half scribing being carried out at the back side of support substrate 11 with cutter.The thickness of the depth ratio support substrate 11 of groove 12 is shallow.Then, cut apart sealing resin 18 and support substrate 11 along the line of demarcation of each semiconductor device, for example finish semiconductor device 10 as shown in Figure 1.At this, the formation of groove 12 can be undertaken by the operation shown in Fig. 4 (A), also can form groove 12 by the method beyond the cutting.Specifically, can form groove 12 by the method for removing such as etching or laser.
Effect shown in the present invention can be achieved as follows.
Because the back side in support substrate 11 forms groove 12, even so because semiconductor element 16 and difference that the thermal coefficient of expansion of substrate 20 is installed when having thermal stress to act on the support substrate 11, also can be by making the support substrate 11 local thermal stress that movably reduce generation.Therefore, can prevent to crack at the connecting portion of breakthrough part 15 and surface electrode 14 or the connecting portion of breakthrough part 15 and backplate 14 because of thermal stress.
In addition owing to utilize the support substrate 11 be provided with groove 12 to absorb thermal stress, so but abirritation in the stress of the solder flux 22 that connects semiconductor device 10 and installation substrate 20.
By groove 12 is set, can prevent solder flux 22 mutual short circuits when semiconductor device 10 is installed on support substrate 11.Therefore, do not form the short circuit that anti-scolder agent also can prevent solder flux 22.

Claims (4)

1, a kind of semiconductor device is characterized in that, it comprises: support substrate; Be formed at the surface and the back side of described support substrate, by the surface electrode and the backplate of breakthrough part connection; Be fixed on the surface of described support substrate the semiconductor element that is electrically connected with described surface electrode; Seal the sealing resin of described semiconductor element, the back side of described support substrate is provided with groove.
2, semiconductor device as claimed in claim 1 is characterized in that, the rectangular back side that is formed at described support substrate of described backplate, and described groove is clathrate and is arranged between the described backplate.
3, semiconductor device as claimed in claim 1 is characterized in that, described groove is formed at the pars intermedia between the described backplate.
4, semiconductor device as claimed in claim 1 is characterized in that, by solder flux is installed on the substrate attached to being installed on the described backplate.
CNB2004100452293A 2003-06-05 2004-06-04 Semiconductor device Expired - Fee Related CN100336208C (en)

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JP160892/2003 2003-06-05
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JP2003160892A JP2004363379A (en) 2003-06-05 2003-06-05 Semiconductor device

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CN100336208C true CN100336208C (en) 2007-09-05

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JP4614818B2 (en) * 2005-05-09 2011-01-19 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP4678241B2 (en) * 2005-05-31 2011-04-27 富士フイルム株式会社 Resin wiring board
US8227840B2 (en) * 2010-11-24 2012-07-24 Nanya Technology Corp. Integrated circuit device and method of forming the same
KR20140050387A (en) * 2012-10-19 2014-04-29 삼성테크윈 주식회사 Leadframe for semiconductor package and the fabrication method thereof
JP2015177116A (en) * 2014-03-17 2015-10-05 株式会社東芝 semiconductor device
CN110312363B (en) * 2019-06-24 2020-10-16 维沃移动通信有限公司 Printed circuit board assembly and terminal
CN110957277B (en) * 2019-08-20 2021-02-12 中腾微网(深圳)科技有限公司 Inverter power system and manufacturing method thereof
FR3117303B1 (en) * 2020-12-09 2023-01-06 Safran Electronics & Defense Reduction of stress zones in the soldered joints of an electronic board
CN116569335A (en) * 2020-12-16 2023-08-08 株式会社村田制作所 High-frequency module and communication device

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Publication number Priority date Publication date Assignee Title
JP2000252391A (en) * 1999-02-26 2000-09-14 Kyocera Corp Wiring board for mounting semiconductor device and its mounting structure
JP2003037344A (en) * 2001-07-25 2003-02-07 Sanyo Electric Co Ltd Circuit device and its manufacturing method
EP1317000A2 (en) * 2001-11-30 2003-06-04 Kabushiki Kaisha Toshiba Semiconductor device having leadless package structure

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