CH557091A - Semiconductor devices with a protective layer of rubber - of silicone resin over the p-n junctions - Google Patents
Semiconductor devices with a protective layer of rubber - of silicone resin over the p-n junctionsInfo
- Publication number
- CH557091A CH557091A CH232572A CH232572A CH557091A CH 557091 A CH557091 A CH 557091A CH 232572 A CH232572 A CH 232572A CH 232572 A CH232572 A CH 232572A CH 557091 A CH557091 A CH 557091A
- Authority
- CH
- Switzerland
- Prior art keywords
- semiconductor devices
- junctions
- diodes
- channels
- rubber
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000011241 protective layer Substances 0.000 title abstract 2
- 229920002050 silicone resin Polymers 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000012528 membrane Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 2
- 210000004379 membrane Anatomy 0.000 claims 4
- 229920003051 synthetic elastomer Polymers 0.000 claims 1
- 239000005061 synthetic rubber Substances 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract 2
- 239000011253 protective coating Substances 0.000 abstract 1
- 239000007788 liquid Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
Semiconductor devices are produced by (a) forming a plate having at least one p-zone and at least one n-zone, (b) dividing the plate, which is placed on a support, into several parts each forming one device, so that channels are formed between the devices, and pn-transitions are released in the channels, (C) pouring a hardenable compound in the channels to protect the pn-transitions, and (d) hardening the compound to form a protective layer of the pn-junctions. The method is useful for the production of diode elements which can be divided into separate diodes. The diodes are effectively protected during use and handling by the protective coating of rubber or silicone resin over the pn-junctions. In addition to diodes, the process can be used for the prodn. of transistors, thyristors and other semi-conductor devices.
Description
Diese Erfindung betrifft ein Verfahren zur Herstellung von Halbleitervorrichtungen, in dem ein Grundkörper mit mindestens einem Bereich des p-Typs und mindestens einem Bereich des n-Typs gebildet wird, dass der Grundkörper auf einer Stütze angeordnet und in eine Vielzahl von Teilstükken unterteilt wird, wobei jedes Teilstück eine Halbleitervorrichtung darstellt, und zwischen den Vorrichtungen Kanäle ausgeführt werden und die p-n-Übergänge in den Kanälen entblösst werden.
Das erfindungsgemässe Verfahren ist dadurch gekennzeichnet, dass zwecks Erleichterung der Handhabung der Halbleitervorrichtungen ein härtbarer Werkstoff in den Kanä len eingegossen wird und dass der Werkstoff so ausgehärtet wird, dass eine die Halbleitervorrichtungen verbindende Membran entsteht.
Im folgenden wird der Erfindungsgegenstand anhand der Zeichnung rein beispielsweise näher erläutert. Es zeigen:
Fig. 1 bis 6 in schematischer Darstellung 6 verschiedene Verfahrensschritte bei der Herstellung von Dioden und,
Fig. 7 ausschnittsweise eine Draufsicht auf ein Halbfabrikat gemäss Fig. 3.
Der in den Figuren dargestellte Silizium-Grundkörper 10, der vom p-Typ oder vom n-Typ sein kann, wird mit Hilfe bekannter Diffusionsverfahren so behandelt, dass ein p-n-Übergang entsteht (Fig. 2). Nachdem der letztere entstanden ist, werden geeignete, nichtdargestellte Metallschichten auf den Oberflächen des Grundkörpers angebracht, die die Herstellung elektrischer Anschlüsse an die zu erzeugenden Dioden erleichtern.
Der die p-n-Übergänge enthaltende Grundkörper wird dann mittels einer dünnen Wachsschicht 12 auf einer Glasoder Keramikplatte 11 befestigt. Auf die Oberfläche des Grundkörpers wird eine nichtdargestellte Stahlmaske gelegt, die eine Vielzahl von rechteckförmigen Löchern enthält: auf diese Maske wird eine Wachslösung aufgesprüht. Das Wachs tritt durch die Öffnungen der Maske hindurch und bleibt am Grundkörper haften; wenn die Maske entfernt wird, weist die Oberfläche des Grundkörpers eine Vielzahl von rechteckigen Bereichen 13 auf, welche mit Wachs bedeckt sind (Fig. 3).
Die den Grundkörper 10 tragende Platte 11 wird dann in ein Ätzbad getaucht, das die Bereiche des Grundkörpers zwischen den maskierten Bereichen 13 entfernt (Fig. 4). Es ist festzustellen, dass das zur Befestigung des Grundkörpers 10 an der Platte 11 benutzte Wachs sowie die Wachsmaske für die Bereiche 13 des Grundkörpers 10 so ausgewählt werden, dass sie durch das Ätzmittel nicht angegriffen werden.
Wenn die freigelegten Bereiche des Grundkörpers 10 wegge ätzt worden sind, wird die Platte 11 aus dem Ätzmittel entfernt, gespült und getrocknet. In diesem Stadium des Verfahrens trägt die Platte 11 eine Vielzahl von kleinen rechteckförmigen p-n-Dioden 15; diese sind voneinander getrennt und auf beiden Seiten mit Wachs überzogen; nur die geätzten Kanten 16 der Dioden 15 sind freigelegt. Selbstverständlich können auch anstatt des Wachses andere Maskierungsmittel benutzt werden, die von dem Ätzmittel nicht angegriffen wer den.
Auf die Platte 11 wird dann ein synthetischer, vernetzbarer Kautschuk auf Silikonbasis in flüssiger Form gegossen; dieser fliesst in die Zwischenräume 14 zwischen den Dioden (Fig. 5). Wenn die Zwischenräume 14 mit dem flüssigen Werk stoff ausgefüllt sind, wird die Oberfläche des geätzten Grund- körpers abgewischt, um überschüssigen Kautschuk zu entfernen; es bleibt ein Gitterwerk 17 aus flüssigem Kautschuk in den Zwischenräumen 14 zurück. Der flüssige Kautschuk wird dann ausgehärtet, worauf die Platte 11 in ein Flüssigkeitsbad eingelegt wird, in dem sich das Wachs auflöst.
Dabei löst sich das die Dioden 15 überdeckende Wachs und auch das die Dioden 15 mit der Platte 12 verbindende Wachs auf; die Dioden sind dann nur noch miteinander durch eine Kautschukmembran 17 verbunden (Fig. 6), die die Handhabung der Halbleitervorrichtung während der weiteren Bearbeitung sehr erleichtert. In einigen Fällen liefert die Membran 17 auch einen Schutz für die p-n-Übergänge der Halbleitervorrichtungen.
Wenn es erwünscht ist, eine der Dioden 15 zu benutzen, wird der Abschnitt der Membran, der die Platte mit den übrigen Dioden verbindet, durchgetrennt; es bleibt dabei eine einzelne Diode zurück, deren Kanten durch die abgetrennten Abschnitte der Membran umgeben sind.
Wenn die Diode Anschlussleiter aufweist, die durch Löten bei erhöhter Temperatur hergestellt worden sind, dann kann die Löttemperatur so gewählt werden, dass der die Kanten der Dioden umgebende Kautschuk zersetzt wird; dabei bleiben die Kanten der Dioden sauber und sind auf diese Weise bereit zum Eingiessen.
Der Kautschuk kann jedoch auch während der ganzen Betriebsdauer der Diode an seinem Ort verbleiben. In diesem Falle ist es notwendig, dass die Löttemperatur so niedrig ist, dass die Membran aus dem betreffenden Werkstoff nicht zerstört wird.
Es ist nicht unbedingt erforderlich, dass der Membranwerkstoff flexibel ist. Es können nämlich auch Werkstoffe benutzt werden, die eine spröde Membran erzeugen; in diesem Falle werden die Dioden durch Brechen voneinander getrennt und nicht durch Durchtrennen der Membran.
Obwohl sich die obige Beschreibung auf die Herstellung von Dioden beschränkt, ist leicht einzusehen, dass das beschriebene Verfahren auch bei der Herstellung von Transistoren, Thyristoren und anderen Halbleitervorrichtungen verwendbar ist.
This invention relates to a method for manufacturing semiconductor devices in which a base body having at least one p-type region and at least one n-type region is formed, that the base body is arranged on a support and divided into a plurality of parts, wherein each section represents a semiconductor device, and channels are made between the devices and the pn junctions in the channels are exposed.
The method according to the invention is characterized in that a hardenable material is poured into the channels in order to facilitate the handling of the semiconductor devices and that the material is hardened in such a way that a membrane connecting the semiconductor devices is created.
In the following, the subject matter of the invention is explained in more detail purely by way of example with reference to the drawing. Show it:
Fig. 1 to 6 in a schematic representation of 6 different process steps in the production of diodes and,
FIG. 7 shows a detail of a plan view of a semifinished product according to FIG. 3.
The silicon base body 10 shown in the figures, which can be of the p-type or of the n-type, is treated with the aid of known diffusion processes in such a way that a p-n junction is produced (FIG. 2). After the latter has been created, suitable metal layers (not shown) are applied to the surfaces of the base body, which facilitate the production of electrical connections to the diodes to be produced.
The base body containing the p-n junctions is then attached to a glass or ceramic plate 11 by means of a thin layer of wax 12. A steel mask, not shown, which contains a large number of rectangular holes, is placed on the surface of the base body: a wax solution is sprayed onto this mask. The wax passes through the openings in the mask and sticks to the base body; when the mask is removed, the surface of the base body has a plurality of rectangular areas 13 which are covered with wax (FIG. 3).
The plate 11 carrying the base body 10 is then immersed in an etching bath which removes the areas of the base body between the masked areas 13 (FIG. 4). It should be noted that the wax used to attach the base body 10 to the plate 11 and the wax mask for the areas 13 of the base body 10 are selected so that they are not attacked by the etchant.
When the exposed areas of the base body 10 have been etched away, the plate 11 is removed from the etchant, rinsed and dried. At this stage of the process, the plate 11 carries a plurality of small rectangular p-n diodes 15; these are separated from each other and coated with wax on both sides; only the etched edges 16 of the diodes 15 are exposed. Of course, other masking agents that are not attacked by the etchant can also be used instead of the wax.
A synthetic, crosslinkable silicone-based rubber is then poured in liquid form onto the plate 11; this flows into the spaces 14 between the diodes (FIG. 5). When the spaces 14 have been filled with the liquid material, the surface of the etched base body is wiped off in order to remove excess rubber; a latticework 17 made of liquid rubber remains in the spaces 14. The liquid rubber is then cured, whereupon the plate 11 is placed in a liquid bath in which the wax dissolves.
The wax covering the diodes 15 and also the wax connecting the diodes 15 to the plate 12 dissolves in the process; the diodes are then only connected to one another by a rubber membrane 17 (FIG. 6), which greatly facilitates the handling of the semiconductor device during further processing. In some cases, the membrane 17 also provides protection for the p-n junctions of the semiconductor devices.
When it is desired to use one of the diodes 15, the portion of the membrane connecting the plate to the remaining diodes is severed; what remains is a single diode, the edges of which are surrounded by the separated sections of the membrane.
If the diode has connection conductors which have been produced by soldering at an elevated temperature, then the soldering temperature can be selected so that the rubber surrounding the edges of the diodes is decomposed; the edges of the diodes remain clean and are ready for pouring.
However, the rubber can also remain in place during the entire service life of the diode. In this case it is necessary that the soldering temperature is so low that the membrane made of the material in question is not destroyed.
It is not absolutely necessary for the membrane material to be flexible. In fact, materials can also be used which produce a brittle membrane; in this case the diodes are separated from one another by breaking and not by severing the membrane.
Although the above description is limited to the manufacture of diodes, it is easy to see that the method described can also be used in the manufacture of transistors, thyristors and other semiconductor devices.
Claims (1)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB5103568 | 1968-10-28 | ||
| GB24991/69A GB1285708A (en) | 1968-10-28 | 1968-10-28 | Semi-conductor devices |
| CH1540669A CH522955A (en) | 1968-10-28 | 1969-10-14 | Method for manufacturing a semiconductor device and semiconductor device manufactured by the method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH557091A true CH557091A (en) | 1974-12-13 |
Family
ID=27177337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH232572A CH557091A (en) | 1968-10-28 | 1969-10-14 | Semiconductor devices with a protective layer of rubber - of silicone resin over the p-n junctions |
Country Status (1)
| Country | Link |
|---|---|
| CH (1) | CH557091A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0209767A1 (en) * | 1985-07-06 | 1987-01-28 | SEMIKRON Elektronik GmbH | Method of making semiconductor devices |
| WO1991011820A1 (en) * | 1990-01-30 | 1991-08-08 | Massachusetts Institute Of Technology | Optical surface polishing method |
| US5174072A (en) * | 1990-01-30 | 1992-12-29 | Massachusetts Institute Of Technology | Optical surface polishing method |
| WO2005018874A1 (en) * | 2003-08-18 | 2005-03-03 | Schott Ag | Method for the production of components |
-
1969
- 1969-10-14 CH CH232572A patent/CH557091A/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0209767A1 (en) * | 1985-07-06 | 1987-01-28 | SEMIKRON Elektronik GmbH | Method of making semiconductor devices |
| WO1991011820A1 (en) * | 1990-01-30 | 1991-08-08 | Massachusetts Institute Of Technology | Optical surface polishing method |
| US5095664A (en) * | 1990-01-30 | 1992-03-17 | Massachusetts Institute Of Technology | Optical surface polishing method |
| US5174072A (en) * | 1990-01-30 | 1992-12-29 | Massachusetts Institute Of Technology | Optical surface polishing method |
| WO2005018874A1 (en) * | 2003-08-18 | 2005-03-03 | Schott Ag | Method for the production of components |
| US7736995B2 (en) | 2003-08-18 | 2010-06-15 | Schott Ag | Process for producing components |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |