CH408223A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor deviceInfo
- Publication number
- CH408223A CH408223A CH554164A CH554164A CH408223A CH 408223 A CH408223 A CH 408223A CH 554164 A CH554164 A CH 554164A CH 554164 A CH554164 A CH 554164A CH 408223 A CH408223 A CH 408223A
- Authority
- CH
- Switzerland
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
- C23C14/042—Coating on selected surface areas, e.g. using masks using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Vapour Deposition (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DES0086952 | 1963-08-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
CH408223A true CH408223A (en) | 1966-02-28 |
Family
ID=7513395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH554164A CH408223A (en) | 1963-08-28 | 1964-04-28 | Method for manufacturing a semiconductor device |
Country Status (5)
Country | Link |
---|---|
CH (1) | CH408223A (en) |
DE (1) | DE1439280A1 (en) |
FR (1) | FR1405134A (en) |
GB (1) | GB1010984A (en) |
NL (1) | NL6407702A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4536419A (en) * | 1983-03-10 | 1985-08-20 | Hitachi, Ltd. | Method for forming tapered films |
DE3374790D1 (en) * | 1983-03-11 | 1988-01-14 | Hitachi Ltd | Method for forming thin films |
DE102006024175B3 (en) * | 2006-05-23 | 2007-09-27 | Touchtek Corporation, Chunan | Light emitting diode primary multi-layer electrodes manufacturing method for e.g. backlight, involves masking epitaxial substrate with magnetizable mask that is hold by magnet, where magnetizable mask has contact windows |
-
1963
- 1963-08-28 DE DE19631439280 patent/DE1439280A1/en active Pending
-
1964
- 1964-04-28 CH CH554164A patent/CH408223A/en unknown
- 1964-07-07 NL NL6407702A patent/NL6407702A/xx unknown
- 1964-08-27 GB GB35080/64A patent/GB1010984A/en not_active Expired
- 1964-08-27 FR FR986384A patent/FR1405134A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1405134A (en) | 1965-07-02 |
GB1010984A (en) | 1965-11-24 |
DE1439280A1 (en) | 1968-11-14 |
NL6407702A (en) | 1965-03-01 |
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