CA3039845A1 - Processor with variable n-bits architecture - Google Patents

Abstract

A processor controls all the hardware and software of a computer system or an embedded system. A
processor includes an ALU (Arithmetic Logic Unit), two internal LIFO (Last In/First Out) stacks for Instructions and Data, different registers, peripheral wishbone buses and compatible with the standard programmer's model.

Description

SOLLEC
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www.sollec.com Processor With Variable n-bits Architecture Background of the Invention 11.1. Field of the Invention The present invention relates to a microprocessor. In particular, the present invention discloses a processor with a variable n-bits architecture designed to asynchronously execute binary instructions, one instruction per clock cycle and compatible with the standard programmer's model.
11.2. Description of Prior Art A processor (or CPU Central Processing Unit ) is the logic circuitry that executes instructions stored in different memories. FIG.3.
The functional architecture of a processor is to connect different devices and memories thru an internal or an external communication bus. The fundamental role of a processor is to execute instructions. FIG.4.
The processor architecture defines the internal operation of the processor viewed by the programmer. Two categories are defined:
= Von Neumann Architecture also known as registers computer architecture.
= Stack Architecture.
All well known processor architectures are based on Von Newman Architecture because of its simplicity and its stability over the years since the invention of the transistor, and the fact it requires one memory space to store data and code.
Since the Von Neumann Architecture is widely used, the programming model also known as the programmer's model (FIG. 5) is well known and taught as a standard model for programming for all high-level languages (like C/C++, Pascal,.. ) .
As for the stack architecture, it is used only in limited applications like satellites; the programming language associated to stack architecture is FORTH and a different programming model less known by programmers.
The main advantages of the stack architecture over the Von Neumann Architecture are the reduced execution cycles and the reduced compiled code. Mainly Stack Architecture requires one clock cycle per instruction (EXECUTE) versus four clock cycles (FETCH, DECODE, EXECUTE, WRITEBACK) per instruction for standard Von Neumann Architecture.
To add performance to Von Neumann Architecture, the use of pipeline is required to process the four cycles in one. The pipeline acts like (First In/First Out) FIFO Stack, it stores and process the four

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........0m execution cycles in parallel. In the case of a routine call or a general conditional branch, the pipeline is flushed and the next instruction will take a full 4 cycles to complete.
The pipeline addition to the simple Von Newman Architecture requires more logic elements and more resources. This makes the simple architecture limited in performances and the more complex architecture very large to fit limited space and resources; witch created a performance gap between simple processors and high performance processors.
The aim of this invention is to fill the gap between simple processors and performance processors by using the architecture disclosed in this invention. This invention is a mix between stack architecture and registers architecture. The programmer's model of this invention is compatible with standard programming model; the code program can be written and compiled by high-level compiler such as C/C++.
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www.soliec.com HI. Summary of the Invention It is therefore a primary objective of the present invention to provide a processor with n-bits architecture. This core is intended to be implemented in CPLD, FPGA, ASIC or as a standalone processor.
The mix of architectures (registers and stack) makes the architecture presented is this invention very simple to use with high-level compilers such as C/C++ compiler witch makes the high level programs codes portables between processors.
The variable architecture is designed to fit FPGA and adapted for computing application. This core is designed to combine simplicity and performance for processors, with low utilisation for resources and logic elements.
As a summary, the advantages of this architecture are enumerated as follow:
= Low utilisation of logic elements and resources = Reduced instruction set = Reduced size of compiled code = Faster performance = Compatibility with high-level compilers and standard programmer's model = Simple implementation in low cost CPLD/FPGA
Briefly summarized, the present invention discloses a stack processor, comprising all the elements needed to build this architecture. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
=
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www.sollec.com V. Description Of The Preferred Embodiment V.1. The architecture Please refer to FIG.1. FIG.1 is a complete schematic diagram of the architecture of the present invention.
The core architecture consists of:
= ALU : arithmetic logic unit (10) with predetermined operators and variable width inputs = Data Stack DS : Stack memory used to store data and instructions with variable width and depth (9) with two registers of the same width TOS "Top Of Stack" (7) and NOS
"Next Of Stack" (8). TOS and NOS are input registers for the ALU
= Return Stack RS : Stack Memory used to store return addresses from functions and interrupts calls with variable width and depth (14) with one register as the top of the stack of the same width R "Return Address" (13) = F: instruction pointer (12) = A: address register (11) = AML: external address register (6) = I : instruction register (5) = Wishbone GLL : "Wishbone Glue Logic Layer" (4) interface module between internal and external buses including interrupt handling. This module permits direct memory access without CPU intervention FIG.2. This module creates the same virtual memory for all memories and devices connected to the different buses.
= Wishbone IBUS : "Wishbone Instruction Memory BUS" (1) the communication bus to connect external memory for instructions "User Compiled Binary Code and Constants Memory". Code memory can be any type, width or depth depending on user requirements.
= Wishbone DBUS : "Wishbone Data Memory BUS" (2) the communication bus to connect external memory for data "User Data and Compiled Binary Code Memory". Data memory is RAM "Random Access Memory" of any type, width or depth.
= Wishbone VBUS : "Wishbone Device BUS" (3) the communication bus to connect external devices. The external devices may be any type, have registers, interrupt(s) with different data width.
= OVRD : "Overflow Data" (15) register to monitor the Data stack and issue an interrupt to insert "rearrange and wait data instruction" to prevent overflow.
= OVRR : "Overflow Return" (16) register to monitor the Return Stack and issue an interrupt to insert "rearrange and wait return instruction" to prevent overflow.
= INT : "Interrupt Register" (17) register to monitor all interrupts, external and internal, calculates the branch address.
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www.sollec.com V.2. The architecture parameters V.2.1. Number of Data bits "n-bits Data"
The number n-bits Data is a power of 2 number. Minimum 4. The number n-bits is the width of all data registers (7,8,9) and affects the ALU complexity (10) V.2.2. Number of Address bits "n-bits Address"
The number n-bits Data is a power of 2 number. Minimum 8. The number n-bits is the width of all data registers (5,6,11,12,13,14) . To calculate the addresses if the number of bits is higher than the data bits, the calculations is done with multiple operations.
V.2.3. Data Stack Depth The data stack depth is function of user preferences, a power of 2 number, the more complex operations the more the depth should be greater to avoid processor special instructions which are time consuming.
V.2.4. Return Stack Depth The return stack depth is function of user preferences, a power of 2 number, the more complex operations the more the depth should be greater to avoid processor special instructions which are time consuming.
V.2.5. Wishbone DBUS
= Width of bus for data DBUS
= Width of bus for address DBUS
V.2.6. Wishbone IBUS
= Width of bus for data IBUS
= Width of bus for address IBUS
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www.sollec.com V.2.7. Wishbone VBUS
= Width of bus for data VBUS
= Width of bus for address VBUS
V.2.8. Wishbone Buses multiplexing The wishbone buses !BUS, DBUS and VBUS can be multiplexed into one, two or three buses depending on the desired complexity and the available resources.
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IV. Brief Description Of Drawings Fig. 1 Processor n-bits Architecture .......................................

Fig. 2 Wishbone Buses Communication ........................................

Fig. 3 Processor Architecture ..............................................

Fig. 4 Processor Communications ............................................

Fig. 5 Standard Programmer's Model .........................................

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Claims (5)

VI. The Embodiments Of The Invention In Which An Exclusive Property Or Privilege Is Claimed Are Defined As Follows:
Compared with the prior art, the present invention provides the stack processor with n-bits architecture compatible with standard programmer's model, and thereby enhance the System.
Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
What is claimed is:

1. A processor comprising:
1.a. An ALU processing data according to an instruction set 1.b. A stack memory for data 1.c. A stack memory for instruction 1.d. GLL wishbone for interface with wishbone Buses 1.e. An interrupt handler and/or register to stack architecture 1.f. Failsafe registers and/or process for overflow stack

2. The processor of claim 1 wherein the processor process and execute one instruction in one cycle

3. The processor of claim 1 wherein the processor have a reduced 5 bits instruction set.

4. The processor of claim 1 wherein the processor is totally configurable for n-bits architecture explained in V.2. The architecture parameters.

5. The processor of claim 1 wherein the processor is compatible with standard programmer's model.