CA2494264A1 - Switched capacitor system, method, and use - Google Patents
Switched capacitor system, method, and use Download PDFInfo
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- CA2494264A1 CA2494264A1 CA002494264A CA2494264A CA2494264A1 CA 2494264 A1 CA2494264 A1 CA 2494264A1 CA 002494264 A CA002494264 A CA 002494264A CA 2494264 A CA2494264 A CA 2494264A CA 2494264 A1 CA2494264 A1 CA 2494264A1
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- 239000003990 capacitor Substances 0.000 title claims abstract 43
- 238000000034 method Methods 0.000 title claims abstract 19
- 238000005070 sampling Methods 0.000 claims 11
- 230000008878 coupling Effects 0.000 claims 9
- 238000010168 coupling process Methods 0.000 claims 9
- 238000005859 coupling reaction Methods 0.000 claims 9
- 230000003213 activating effect Effects 0.000 claims 5
- 238000006243 chemical reaction Methods 0.000 claims 4
- 230000007704 transition Effects 0.000 claims 3
- 230000000295 complement effect Effects 0.000 claims 2
- 238000002360 preparation method Methods 0.000 claims 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
An apparatus and method for adding input voltage signals. First 206 and second 208 input voltage signals are respectively sampled onto first 218 and second 228 capacitors during a first clock phase 202. In response to a second clock phase 204, the first sampled input voltage 206 that is held on the first capacitor 218 is coupled to the negative input terminal 236 of an amplifier 230, and the second sampled voltage 208 held on the second capacitor 228 is coupled to the positive terminal 240 of the amplifier 230. A feedback voltage is provided from the amplifier output 216 to the negative amplifier input 236 via the first capacitor 218 during the second clock phase 204. The first 206 and second 208 input voltage signals are added at the amplifier 230 during the second clock phase 204 to output 216 the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.
Claims (30)
1. A circuit for adding a plurality of input signals, comprising:
an amplifier having inverting and non-inverting input terminals and an output terminal;
a first sampling circuit coupled between a first input signal and a first reference signal to store a first voltage across a first capacitor in response to a first clock phase;
a second sampling circuit coupled between a second input signal and a second reference signal to store a second voltage across a second capacitor in response to the first clock phase; and a switching circuit coupled to the amplifier and the first and second sampling circuits, wherein, in response to a second clock phase, the switching circuit switches the first capacitor storing the first voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the second capacitor storing the second voltage between the non-inverting input terminal and a third input signal.
an amplifier having inverting and non-inverting input terminals and an output terminal;
a first sampling circuit coupled between a first input signal and a first reference signal to store a first voltage across a first capacitor in response to a first clock phase;
a second sampling circuit coupled between a second input signal and a second reference signal to store a second voltage across a second capacitor in response to the first clock phase; and a switching circuit coupled to the amplifier and the first and second sampling circuits, wherein, in response to a second clock phase, the switching circuit switches the first capacitor storing the first voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the second capacitor storing the second voltage between the non-inverting input terminal and a third input signal.
2. The circuit of Claim 1, further comprising an N-phase clock signal comprising the first and second clock phases and remaining clock phases of the N-phase clock signal, and wherein the switching circuit switches the first capacitor between the inverting input terminal and the output terminal of the amplifier, and switches the second capacitor between the non-inverting input terminal and a third input signal, in response to selected ones of the second and remaining clock phases of the N-phase clock signal.
3. The circuit of Claim 1, wherein the first reference signal comprises a DC reference voltage or a time-varying signal.
4. The circuit of Claim 1, wherein the first and second reference signals comprises a common DC reference voltage.
5. The circuit of Claim 1:
(a) further comprising:
(i) a third sampling circuit coupled between the first input signal and the first reference signal to store a third voltage across a third capacitor in response to the second clock phase;
(ii) a fourth sampling circuit coupled between the second input signal and the second reference signal to store a fourth voltage across a fourth capacitor in response to the second clock phase;
and (b) wherein the switching circuit is further coupled to the third and fourth sampling circuits, wherein, in response to the first clock phase, the switching circuit switches the third capacitor storing the third voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the fourth capacitor storing the fourth voltage between the non-inverting input terminal and the third input signal.
(a) further comprising:
(i) a third sampling circuit coupled between the first input signal and the first reference signal to store a third voltage across a third capacitor in response to the second clock phase;
(ii) a fourth sampling circuit coupled between the second input signal and the second reference signal to store a fourth voltage across a fourth capacitor in response to the second clock phase;
and (b) wherein the switching circuit is further coupled to the third and fourth sampling circuits, wherein, in response to the first clock phase, the switching circuit switches the third capacitor storing the third voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the fourth capacitor storing the fourth voltage between the non-inverting input terminal and the third input signal.
6. A method for adding at least two input voltage signals, comprising:
sampling first and second input voltage signals onto first and second capacitor circuits respectively during a first clock phase;
coupling the first sampled input voltage held on the first capacitor circuit to a negative input terminal of an amplifier, and coupling the second sampled input voltage held on the second capacitor circuit to a positive input terminal of the amplifier, during a second clock phase;
providing a feedback voltage from an output of the amplifier to the negative input of the amplifier via the first capacitor circuit during the second clock phase; and outputting a sum of the first and second input voltage signals in response to the feedback voltage and the first and second sampled input voltages during the second clock phase.
sampling first and second input voltage signals onto first and second capacitor circuits respectively during a first clock phase;
coupling the first sampled input voltage held on the first capacitor circuit to a negative input terminal of an amplifier, and coupling the second sampled input voltage held on the second capacitor circuit to a positive input terminal of the amplifier, during a second clock phase;
providing a feedback voltage from an output of the amplifier to the negative input of the amplifier via the first capacitor circuit during the second clock phase; and outputting a sum of the first and second input voltage signals in response to the feedback voltage and the first and second sampled input voltages during the second clock phase.
7. The method of Claim 6, further comprising shifting the voltage level at the output during the second clock phase by applying a shift level voltage to the second capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.
8. The method of Claim 6, further comprising activating at least one switch to create an electrical connection between the second capacitor circuit and the shift level voltage in response to the second clock phase.
9. The method of Claim 6, further comprising:
sampling the first and second input voltage signals onto third and fourth capacitor circuits respectively during the second clock phase;
coupling the first sampled input voltage held on the third capacitor circuit to the negative input terminal of the amplifier, and coupling the second sampled input voltage held on the fourth capacitor circuit to the positive input terminal of the amplifier, during the first clock phase;
providing a second feedback voltage from the output of the amplifier to the negative input of the amplifier via the third capacitor circuit during the first clock phase;
and outputting a sum of the first and second input voltage signals in response to the second feedback voltage and the first and second sampled input voltages during the first clock phase.
sampling the first and second input voltage signals onto third and fourth capacitor circuits respectively during the second clock phase;
coupling the first sampled input voltage held on the third capacitor circuit to the negative input terminal of the amplifier, and coupling the second sampled input voltage held on the fourth capacitor circuit to the positive input terminal of the amplifier, during the first clock phase;
providing a second feedback voltage from the output of the amplifier to the negative input of the amplifier via the third capacitor circuit during the first clock phase;
and outputting a sum of the first and second input voltage signals in response to the second feedback voltage and the first and second sampled input voltages during the first clock phase.
10. The method of Claim 9, further comprising shifting the voltage level at the output during the second clock phase by applying a shift level voltage to the second capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.
11. The method of Claim 9, further comprising shifting the voltage level at the output during the first clock phase by applying a shift level voltage to the fourth capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.
12. The method of Claim 6, wherein coupling the first sampled input voltage held on the first capacitor circuit to the negative input terminal of the amplifier comprises activating at least one switch in response to the second clock phase to create an electrical connection between the first capacitor circuit and the negative input terminal of the amplifier.
13. The method of Claim 6, wherein coupling the second sampled input voltage held on the second capacitor circuit to the positive input terminal of the amplifier comprises activating at least one switch in response to the second clock phase to create an electrical connection between the second capacitor circuit and the positive input terminal of the amplifier.
14. An analog-to-digital converter (ADC) stage for use in ADCs, comprising:
an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal;
first and second capacitances coupled to sample an input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;
a level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of reference voltages in response to a second clock signal;
a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to the second clock phase; and a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the second capacitance to the selected reference voltage in response to the second clock phase; and wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected reference voltage to create the analog ADC residue signal for use in a subsequent ADC
stage.
an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal;
first and second capacitances coupled to sample an input voltage signal and a complemented input voltage signal respectively in response to a first clock phase;
a level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of reference voltages in response to a second clock signal;
a first switch circuit coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to the second clock phase; and a second switch circuit coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the second capacitance to the selected reference voltage in response to the second clock phase; and wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected reference voltage to create the analog ADC residue signal for use in a subsequent ADC
stage.
15. The ADC stage as in Claim 14, wherein the level shifting circuit comprises:
a sub-ADC coupled to receive the input voltage signal, and to provide a digital code based on a voltage of the input voltage signal;
a decoder circuit coupled to the sub-ADC to receive the digital code and to assert one of a plurality of switch signals in response thereto; and a plurality of switches, each coupled to a different one of the plurality of reference voltages; and wherein the asserted one of the switch signals closes a corresponding one of the plurality of switches to couple a corresponding one of the plurality of reference voltages to the second capacitance to add to the inverted version of the sampled complemented input voltage.
a sub-ADC coupled to receive the input voltage signal, and to provide a digital code based on a voltage of the input voltage signal;
a decoder circuit coupled to the sub-ADC to receive the digital code and to assert one of a plurality of switch signals in response thereto; and a plurality of switches, each coupled to a different one of the plurality of reference voltages; and wherein the asserted one of the switch signals closes a corresponding one of the plurality of switches to couple a corresponding one of the plurality of reference voltages to the second capacitance to add to the inverted version of the sampled complemented input voltage.
16. The ADC stage as in Claim 15, wherein the digital code is an n-bit binary code having 2n possible values, and wherein each of the 2n possible values enables a different one of the plurality of switch signals to be asserted by the decoder circuit.
17. The ADC stage as in Claim 15, wherein the digital code is a 1.5-bit binary code having three possible values, and wherein each of the three possible values enables a different one of the plurality of switch signals to be asserted by the decoder circuit.
18. The ADC stage as in Claim 14, wherein:
the first capacitance comprises at least one capacitor having a top plate and a bottom plate;
the top plate of the capacitor is coupled to a first reference voltage via the first switch circuit during the first clock phase, and to the first input terminal of the amplifier via the first switch circuit during the second clock phase; and the bottom plate of the capacitor is coupled to the input voltage signal through the first switch circuit during the first clock phase, and to the output terminal of the amplifier via the first switch circuit during the second clock phase.
the first capacitance comprises at least one capacitor having a top plate and a bottom plate;
the top plate of the capacitor is coupled to a first reference voltage via the first switch circuit during the first clock phase, and to the first input terminal of the amplifier via the first switch circuit during the second clock phase; and the bottom plate of the capacitor is coupled to the input voltage signal through the first switch circuit during the first clock phase, and to the output terminal of the amplifier via the first switch circuit during the second clock phase.
19. The ADC stage as in Claim 14, wherein:
the second capacitance comprises at least one capacitor having a top plate and a bottom plate;
the top plate of the capacitor is coupled to a second reference voltage via the second switch circuit during the first clock phase, and to the second input terminal of the amplifier via the second switch circuit during the second clock phase; and the bottom plate of the capacitor is coupled to the complemented input voltage signal through the second switch circuit during the first clock phase, and to the reference voltage selected by the level shifting circuit via the second switch circuit during the second clock phase.
the second capacitance comprises at least one capacitor having a top plate and a bottom plate;
the top plate of the capacitor is coupled to a second reference voltage via the second switch circuit during the first clock phase, and to the second input terminal of the amplifier via the second switch circuit during the second clock phase; and the bottom plate of the capacitor is coupled to the complemented input voltage signal through the second switch circuit during the first clock phase, and to the reference voltage selected by the level shifting circuit via the second switch circuit during the second clock phase.
20. The ADC stage as in Claim 14, further comprising a reset circuit coupled to the amplifier to discharge residual charge present at one or more of the first and second input terminals and output terminal of the amplifier to clear a current analog ADC residue signal in preparation for output of a subsequent analog ADC residue signal.
21. The ADC stage as in Claim 14, wherein the input voltage signal and complemented input voltage signal comprise complementary input voltage signals of a differential input voltage signal.
22. The ADC stage as in Claim 14, further comprising:
third and fourth capacitances coupled to sample the input voltage signal and the complemented input voltage signal respectively in response to the second clock phase;
a second level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of second reference voltages in response to the first clock phase;
a third switch circuit coupled to the third capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the third capacitance via a second feedback loop, in response to the first clock phase; and a fourth switch circuit coupled to the fourth capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the fourth capacitance to the selected second reference voltage in response to the first clock phase; and wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected second reference voltage to create a second analog ADC residue signal for use in a subsequent ADC stage.
third and fourth capacitances coupled to sample the input voltage signal and the complemented input voltage signal respectively in response to the second clock phase;
a second level shifting circuit coupled to receive the input voltage signal, and to select one of a plurality of second reference voltages in response to the first clock phase;
a third switch circuit coupled to the third capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the third capacitance via a second feedback loop, in response to the first clock phase; and a fourth switch circuit coupled to the fourth capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier and to reference the fourth capacitance to the selected second reference voltage in response to the first clock phase; and wherein the amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the selected second reference voltage to create a second analog ADC residue signal for use in a subsequent ADC stage.
23. A method for converting an analog input signal to a digital signal using an amplifier, the method comprising:
(a) sampling the analog input signal onto a first capacitor and a complement of the analog input signal onto a second capacitor;
(b) providing the sampled analog input signal at a first input terminal of the amplifier by controllably coupling the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration;
(c) providing the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected one of the reference voltages and the second input terminal of the amplifier; and (d) adding the sampled analog input signal to an inverted version of the sampled complemented analog input signal and subtracting the selected one of the reference voltages to provide a residue signal available for use in subsequent conversion stages.
(a) sampling the analog input signal onto a first capacitor and a complement of the analog input signal onto a second capacitor;
(b) providing the sampled analog input signal at a first input terminal of the amplifier by controllably coupling the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration;
(c) providing the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected one of the reference voltages and the second input terminal of the amplifier; and (d) adding the sampled analog input signal to an inverted version of the sampled complemented analog input signal and subtracting the selected one of the reference voltages to provide a residue signal available for use in subsequent conversion stages.
24. The method of Claim 23, further comprising repeating steps (a)-(d) for each of the first M-1 stages of an M-stage analog-to-digital conversion having an N-bit resolution.
25. The method of Claim 24, further comprising resolving least significant bits of the digital signal in an M-th flash stage of the analog to digital conversion, by comparing the residue signal from the M-1 stage to a set of predetermined reference voltages.
26. The method of Claim 25, wherein the set of predetermined reference voltages comprises 2n-1 reference voltages, wherein n corresponds to a resolution of the M-th stage.
27. The method of Claim 26, further comprising resolving N-M bits at the M-th stage of the analog-to-digital conversion having the N-bit resolution.
28. The method of Claim 16, further comprising providing a multi-phase clock signal including a first clock phase and a second clock phase, and wherein step (a) is performed during the first clock phase and steps (b), (c), and (d) are performed during the second clock phase.
29. The method of Claim 28, wherein controllably coupling the first capacitor between the amplifier output and the first input terminal comprises activating one or more switches coupled between the amplifier output and the first input terminal to complete a circuit path therebetween in response to a transition of the second clock phase.
30. The method of Claim 29, further comprising activating one or more sampling switches coupled between the analog input signal and a reference voltage in response to a first transition of the first clock phase, and deactivating the sampling switches in response to a second transition of the first clock phase.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/232,113 US6727749B1 (en) | 2002-08-29 | 2002-08-29 | Switched capacitor summing system and method |
| US10/232,113 | 2002-08-29 | ||
| US10/231,541 | 2002-08-29 | ||
| US10/231,541 US6784824B1 (en) | 2002-08-29 | 2002-08-29 | Analog-to-digital converter which is substantially independent of capacitor mismatch |
| PCT/US2003/026198 WO2004021251A2 (en) | 2002-08-29 | 2003-08-20 | Switched capacitor system, method, and use |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2494264A1 true CA2494264A1 (en) | 2004-03-11 |
| CA2494264C CA2494264C (en) | 2011-07-26 |
Family
ID=31980956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2494264A Expired - Lifetime CA2494264C (en) | 2002-08-29 | 2003-08-20 | Switched capacitor system, method, and use |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1540565B1 (en) |
| JP (1) | JP4454498B2 (en) |
| CA (1) | CA2494264C (en) |
| WO (1) | WO2004021251A2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4654998B2 (en) * | 2005-11-08 | 2011-03-23 | 株式会社デンソー | Sample hold circuit and multiple D / A converter |
| JP5155103B2 (en) * | 2008-11-05 | 2013-02-27 | 旭化成エレクトロニクス株式会社 | Switched capacitor circuit and pipelined A / D converter |
| US8648779B2 (en) | 2009-10-20 | 2014-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | LCD driver |
| US8339302B2 (en) | 2010-07-29 | 2012-12-25 | Freescale Semiconductor, Inc. | Analog-to-digital converter having a comparator for a multi-stage sampling circuit and method therefor |
| CN102654987B (en) * | 2012-02-03 | 2014-10-15 | 京东方科技集团股份有限公司 | Thin film transistor liquid crystal display (TFT-LCD) substrate pixel point charging method, device and source driver |
| KR101876605B1 (en) * | 2014-10-30 | 2018-07-11 | 한국과학기술원 | Optical spectroscopy system using pipeline matched filter and dual slope analog digital converter and control method thereof |
| US10714185B2 (en) * | 2018-10-24 | 2020-07-14 | Micron Technology, Inc. | Event counters for memory operations |
| US11061100B2 (en) | 2019-06-12 | 2021-07-13 | Texas Instruments Incorporated | System for continuous calibration of hall sensors |
| US11867773B2 (en) * | 2019-06-18 | 2024-01-09 | Texas Instruments Incorporated | Switched capacitor integrator circuit with reference, offset cancellation and differential to single-ended conversion |
| TWI768976B (en) * | 2021-06-21 | 2022-06-21 | 瑞昱半導體股份有限公司 | Switched capacitor amplifier apparatus having gain adjustment mechanism |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137321A (en) * | 1999-01-12 | 2000-10-24 | Qualcomm Incorporated | Linear sampling switch |
| US6362770B1 (en) * | 2000-09-12 | 2002-03-26 | Motorola, Inc. | Dual input switched capacitor gain stage |
-
2003
- 2003-08-20 EP EP03791719A patent/EP1540565B1/en not_active Expired - Lifetime
- 2003-08-20 JP JP2004532939A patent/JP4454498B2/en not_active Expired - Lifetime
- 2003-08-20 CA CA2494264A patent/CA2494264C/en not_active Expired - Lifetime
- 2003-08-20 WO PCT/US2003/026198 patent/WO2004021251A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004021251A2 (en) | 2004-03-11 |
| CA2494264C (en) | 2011-07-26 |
| EP1540565A2 (en) | 2005-06-15 |
| WO2004021251A3 (en) | 2004-06-17 |
| EP1540565B1 (en) | 2012-01-18 |
| JP2005537749A (en) | 2005-12-08 |
| JP4454498B2 (en) | 2010-04-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20230821 |