CA2458137A1 - Zero voltage switched full bridge dc/dc converter - Google Patents
Zero voltage switched full bridge dc/dc converter Download PDFInfo
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- CA2458137A1 CA2458137A1 CA002458137A CA2458137A CA2458137A1 CA 2458137 A1 CA2458137 A1 CA 2458137A1 CA 002458137 A CA002458137 A CA 002458137A CA 2458137 A CA2458137 A CA 2458137A CA 2458137 A1 CA2458137 A1 CA 2458137A1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
A buck derived Full Bridge Zero Voltage Switching (ZVS) galvanicaly isolated DC to DC Converter which includes an inductance placed effectively in parallel to the primary winding of the transformer and a second winding added to the output inductor with a second winding connected to an extra output diode to reduce the transformer load current to zero during the freewheeling interval and a third winding connected to a series capacitor to provide a path for AC current from the second winding. Additionally included is a means of recovering the stored energy in the series inductor caused by the reverse recovery current of the output diodes using one or more extra winding(s) in the transformer, which are connected via a series capacitor, and a rectifying circuit back to the source voltage, as well as a method, which allows control of the energy stored in the parallel inductance to optimize ZVS for different output voltages.
Description
TITLE OF INVENTION
ZERO VOLTAGE SWITCHED FULL BRIDGE DC/DC CONVERTER
s TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to isolated DC to DC
io converters and more particularly to buck derived Full Bridge converters, which feature zero voltage switching of the four controlled power switches.
BACKGROUND OF THE INVENTION
is High frequency switching DC to DC converters are frequently used to convert DC voltage, provide galvanic isolation of the output from the input and to regulate the output voltage and current. DC to DC converters are frequently used as a portion of AC to DC power supplies. For example, such power supplies are employed in Telecommunication or Cell Site Power 2o Systems to provide isolated and regulated +24Volt or -48Volt power to system batteries and the paralleled load. DC to DC converters are also frequently used to provide a second isolated DC voltage from another. For example, +24Volt Cell Site Transmitter power is converted to -48Volts for co-located telecommunications equipment by using DC to DC converters.
2s Of the many topologies that can be used for DC to DC converters, those that are buck derived are often preferred for medium (+24V, -48V) or low voltage (+5V, +3V) outputs. This is due to the non-pulsating output current and ease of control as the output is directly proportional to the duty 3o cycle of the controlled switching devices. It is also preferred to use i topologies that achieve zero voltage switching (ZVS) of the primary controlled switches and zero current switching (ZCS) of the secondary (usually) non controlled switches to maximize converter efficiency and to minimize Electro-Magnetic Interference (EMI) generation. For low to s medium output power it is desired to use such a ZVS converter employing two controlled switches, such as the inventor has previously disclosed in US
Patent 6208529. For high output power (above 2.5kW) a full bridge converter employing four controlled switches is more desirable as current in the switching circuit is reduced.
io A commonly used full bridge ZVS buck derived converter is the Phase Shifted Bridge (PSB) Zero Voltage Transition (ZVT) Converter such as disclosed in US patent 4864479 by Robert Steigerwald. A similar converter is described in Unitrode (Now part of Texas Instruments) is application note U-136A 'Phase Shifted, Zero Voltage Transition design considerations and the UC3875 PWM controller' published in May 1997.
Such a PSB Converter can achieve ZVS of the primary switches at full load but has difficulty achieving ZVS at partial loads. This converter also has a loss of output voltage due to the commutation time of the load current an Zo effect, which is worsened if the series commutation inductor value is increased to extend the ZVS load range. Also during the freewheeling time, when one of the diagonally opposite switches are off, there is excess current (which does not contribute to load current) flowing in the primary of the power transformer and two of the primary switches causing extra power Zs loss. The rate of turn off (dl/dT) of the output non-controlled switches (rectifier diodes) is limited by the series commutation inductance but with typically used inductor values the dl/dT is still very high causing high reverse recovery current in the diodes which can generate high EMI.
Another method of modulating the ZVS Full bridge converter, disclosed by 3o Barry Blair et al. in US Patent 6483724, involves alternately modulating the top two switches on at nearly 50% duty cycle each and alternately Pulse width modulating the bottom two switches on anywhere from zero to nearly 50% duty cycle, achieves essentially the same result as Phase Shift Modulation for Full Bridge Buck derived converters.
s As a result of the limitations of the commonly used 'Traditional' PSB
Converter many researchers have proposed variations to this converter topology to improve it's performance. These variations either consist of adding extra components to the primary side or to the secondary side of the io PSB Converter.
Of those that add extra components to the primary side, Dong-Yun Lee, in the publication "An improved Full-Bridge Zero-Voltage-Transition PWM DC/DC Converter with Zero-Voltage/Zero-Current Switching of the is Auxiliary Switches", adds an extra leg of controlled switches whose center point is connected to the center point of one of the original controlled switch legs through series connected inductors. Xinbo Ruan et al., in "An Improved Phase-Shifted Zero-Voltage and Zero-Current Switching PWM
Converter" adds diodes in series with the controlled switches of one of the Zo bridge legs. Praveen Jain et al. disclose in US Patent 6016258 using two large valued inductors connecting between each original bridge leg center point respectively and a center point of a leg of large valued capacitors.
Rajapandian Ayyanar et al. in US Patent 6310785 disclose adding a second transformer between one of the original bridge leg center points and a Zs center point of a leg of large valued capacitors. Both Yungtaek Jang et al.
in "A New ZVS-PWM Full Bridge Converter" and lonel Dan Jitaru in "High Efficiency Converter Using Current Shaping and Synchronous Rectification", use a coupled inductor connected in series with the transformer primary.
ZERO VOLTAGE SWITCHED FULL BRIDGE DC/DC CONVERTER
s TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to isolated DC to DC
io converters and more particularly to buck derived Full Bridge converters, which feature zero voltage switching of the four controlled power switches.
BACKGROUND OF THE INVENTION
is High frequency switching DC to DC converters are frequently used to convert DC voltage, provide galvanic isolation of the output from the input and to regulate the output voltage and current. DC to DC converters are frequently used as a portion of AC to DC power supplies. For example, such power supplies are employed in Telecommunication or Cell Site Power 2o Systems to provide isolated and regulated +24Volt or -48Volt power to system batteries and the paralleled load. DC to DC converters are also frequently used to provide a second isolated DC voltage from another. For example, +24Volt Cell Site Transmitter power is converted to -48Volts for co-located telecommunications equipment by using DC to DC converters.
2s Of the many topologies that can be used for DC to DC converters, those that are buck derived are often preferred for medium (+24V, -48V) or low voltage (+5V, +3V) outputs. This is due to the non-pulsating output current and ease of control as the output is directly proportional to the duty 3o cycle of the controlled switching devices. It is also preferred to use i topologies that achieve zero voltage switching (ZVS) of the primary controlled switches and zero current switching (ZCS) of the secondary (usually) non controlled switches to maximize converter efficiency and to minimize Electro-Magnetic Interference (EMI) generation. For low to s medium output power it is desired to use such a ZVS converter employing two controlled switches, such as the inventor has previously disclosed in US
Patent 6208529. For high output power (above 2.5kW) a full bridge converter employing four controlled switches is more desirable as current in the switching circuit is reduced.
io A commonly used full bridge ZVS buck derived converter is the Phase Shifted Bridge (PSB) Zero Voltage Transition (ZVT) Converter such as disclosed in US patent 4864479 by Robert Steigerwald. A similar converter is described in Unitrode (Now part of Texas Instruments) is application note U-136A 'Phase Shifted, Zero Voltage Transition design considerations and the UC3875 PWM controller' published in May 1997.
Such a PSB Converter can achieve ZVS of the primary switches at full load but has difficulty achieving ZVS at partial loads. This converter also has a loss of output voltage due to the commutation time of the load current an Zo effect, which is worsened if the series commutation inductor value is increased to extend the ZVS load range. Also during the freewheeling time, when one of the diagonally opposite switches are off, there is excess current (which does not contribute to load current) flowing in the primary of the power transformer and two of the primary switches causing extra power Zs loss. The rate of turn off (dl/dT) of the output non-controlled switches (rectifier diodes) is limited by the series commutation inductance but with typically used inductor values the dl/dT is still very high causing high reverse recovery current in the diodes which can generate high EMI.
Another method of modulating the ZVS Full bridge converter, disclosed by 3o Barry Blair et al. in US Patent 6483724, involves alternately modulating the top two switches on at nearly 50% duty cycle each and alternately Pulse width modulating the bottom two switches on anywhere from zero to nearly 50% duty cycle, achieves essentially the same result as Phase Shift Modulation for Full Bridge Buck derived converters.
s As a result of the limitations of the commonly used 'Traditional' PSB
Converter many researchers have proposed variations to this converter topology to improve it's performance. These variations either consist of adding extra components to the primary side or to the secondary side of the io PSB Converter.
Of those that add extra components to the primary side, Dong-Yun Lee, in the publication "An improved Full-Bridge Zero-Voltage-Transition PWM DC/DC Converter with Zero-Voltage/Zero-Current Switching of the is Auxiliary Switches", adds an extra leg of controlled switches whose center point is connected to the center point of one of the original controlled switch legs through series connected inductors. Xinbo Ruan et al., in "An Improved Phase-Shifted Zero-Voltage and Zero-Current Switching PWM
Converter" adds diodes in series with the controlled switches of one of the Zo bridge legs. Praveen Jain et al. disclose in US Patent 6016258 using two large valued inductors connecting between each original bridge leg center point respectively and a center point of a leg of large valued capacitors.
Rajapandian Ayyanar et al. in US Patent 6310785 disclose adding a second transformer between one of the original bridge leg center points and a Zs center point of a leg of large valued capacitors. Both Yungtaek Jang et al.
in "A New ZVS-PWM Full Bridge Converter" and lonel Dan Jitaru in "High Efficiency Converter Using Current Shaping and Synchronous Rectification", use a coupled inductor connected in series with the transformer primary.
Of those that add extra components to the secondary side, Christopher Henze in US Patent 4953068 discloses changing the output rectification circuit to a full bridge of controlled switches. Michael Waiters in US Patent 5157592 discloses adding controlled saturable reactors in series s with the transformer secondaries. Both Ju Won Baek et al in US Patent 5886884 and Byeong-Ho Choo et al. in "A Novel Secondary Clamping Circuit Topology for Soft Switching Full-Bridge PWM DC/DC Converter"
disclose adding two extra diodes, a capacitor and inductor to the output circuit.
to All of these previously disclosed circuits either add extra magnetic elements, or non controlled switches in series with the primary or secondary current paths or extra controlled switches to the original ZVS Full Bridge Converter. This significantly increases the size, cost and / or reduces the is efficiency of the resulting converter from that of the original ZVT Fulf Bridge Converter.
The output diodes in a ZVT Full bridge Converter typically have significant reverse recovery time, which results in energy being stored in the Zo series commutation inductor. This energy causes large voltage spikes to be present across these diodes as they turn off and can generate substantial EMI. William McLyman discloses in US Patent 4245288 a way to reduce these diode recovery spikes in a Buck Converter by adding a tap-up winding to the output inductor and connecting a commutation diode to the end of the Zs tap, however with the tap-up ratio necessary to achieve acceptably fast current commutation the output current of the Buck Converter will become pulsating. Also it is desirable to recover the energy stored in the series commutation inductor as a result of the reverse recovery current in the output diodes and return it to the source or the Load. For the Traditional PSB Converter, Richard Redl discloses in US Patent 5198969 a way to return the stored energy to the source by adding two diodes.
It is accordingly an object of the invention to provide a new and s improved isolated Full Bridge Zero Voltage Transition DC to DC Converter suitable for High output Power and medium and low output Voltages.
An object of the invention is to provide a Full Bridge DC to DC
Converter that can achieve Zero Voltage Switching of the primary side io controlled switches over a very wide load range, has minimal loss of output voltage due to the commutation time of the load current, reduces the excess current flowing in the transformer and primary controlled switches to zero during the freewheel interval, minimizes the rate of turn off (dl/dT) of the output diodes and provides a non-pulsating output current to the load. It is is an object of the invention to achieve the above performance improvements without adding extra magnetic components, any extra controlled switching devices, or any additional non-controlled switches in series with the current paths.
Zo An additional object of the invention is to provide a means to recover all the stored energy in the commutation inductor as a result of the reverse recovery current in the output diodes and some of the stored energy in the leakage inductance of the transformer and return this energy to the source.
Zs An additional object of the invention is to provide a method to control the energy stored in the inductor which is connected effectively in parallel to the transformer primary, to constant so that it can be just sufficient to achieve Zero Voltage Switching of the controlled switches for different output voltage adjustment of the DC/DC converter.
S
SUMMMARY OF THE INVENTION
In one of it's aspects the invention consists of a switch mode DC to DC converter comprising of a full bridge arrangement of controlled switches at the input stage, a commutation inductance connected in series with transformer primary winding and an inductance placed effectively in parallel io with the primary winding, and a output stage including a center tapped secondary winding of the transformer, an output diode connected to each end of the center tapped winding, the other pole of the output diodes are connected together and to a first pole of the output capacitor, first output inductor winding connected between the secondary winding center tap and is the other pole of the output capacitor, second output inductor winding connected between the transformer center tap and a third output diode whose other pole is connected to the common point of the other two output diodes, third output inductor winding connected between the transformer center tap and a output filter capacitor whose other pole is connected to the Zo first pole of the output filter capacitor, and output terminals connected to each end of the output capacitor to which the load can be connected.
The primary stage is realized by a full bridge arrangement of controlled switches. Two controlled switches are connected in series with Zs another and in parallel with the input terminals and with a further two controlled switches, which are also connected in series with each other.
Anti-parallel diode means are associated with each switch and are poled to allow current to flow in a direction opposite to the normal direction of current flow in each switch. Capacitance means is also effectively connected in 3o parallel with each switch. An inductance means and optionally also a DC
blocking capacitor means is connected in series with the transformer primary winding, the series combination of the inductance means, primary winding and optional DC blocking capacitor is connected between the common point of the first two controlled switches on the one hand and the s common point of the further two controlled switches on the other hand.
In another aspect of the invention one or more additional windings are added to the transformer, the windings if more than one are connected in parallel with each other, a small valued capacitor is connected in series with io these windings. The series combination of windings) and capacitor is connected to a half bridge or full bridge diode rectification circuit connected in parallel with the input terminals of the converter.
Another aspect of the invention is a method and apparatus to control is the peak current in the inductance connected effectively in parallel with the primary of the transformer. The output voltage of the converter is measured directly or indirectly by means of an additional winding in the transformer, whose voltage is rectified and averaged to provide a representation of the output voltage. The operating frequency of the converter is then varied, by a ao suitable circuit, to be inversely proportional to this measured voltage.
This keeps the volt seconds integral across the inductance constant, thus the peak current constant despite the output voltage being varied due to adjustment or if the DC to DC converter enters into current limit condition.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of one embodiment of the invention s FIG. 2 is a circuit diagram of the invention with the primary DC
blocking capacitor.
FIG. 3 is a circuit diagram of the invention with a half bridge energy recovery circuit.
io FIG. 4 is a circuit diagram of the invention with a full bridge energy recovery circuit.
FIG. 5 is a circuit diagram of the invention with a output voltage is simulation winding and with a full bridge energy recovery circuit.
FIG. 6 is a circuit diagram of a control circuit for the invention including the invented method of controlling the peak current in the parallel inductance Lp to be constant despite the output voltage on the converter ao being changed.
FIG. 7 is a set of voltage waveforms for the embodiment of the invention of FIG. 5.
is FIG. 8 is a set of current waveforms of the embodiment of the invention of FIG. 5.
s DETAILED DESCRIPTION OF THE PREFERRED
AND OTHER EMBODIMENTS
The basic schematic of one embodiment of the invention is shown in s FIG. 1. The converter is connected to a voltage source Vs by input terminals. Two sets of half bridges of controlled switches are connected to the input terminals and thus are connected in parallel with the voltage source Vs. The first half bridge consists of a series combination of controlled switches S1 and S2, which are typically MOSFET's. These io switches have diodes Ds1 and Ds2 placed across them in such a direction that allows current to flow in the opposite direction to the switches. If MOSFET's are used for S1 and S2 then integral diodes inherent in them can be utilized as Ds1 and Ds2. Capacitors Cs1 and Cs2 are placed across S1 and S2 respectively and similarly can be partly or completely realized by is the MOSFET capacitance. The second half bridge similarly consists of controlled switches S3 and S4, diodes Ds3 and Ds4 and capacitors Cs3 and Cs4. The switches S1, S2, S3, and S4 are turned on and off by drive signals Drive A, Drive B, Drive C, and Drive D respectively. The drive waveforms are organized so that only one switch of a series combination is Zo on at any one time and a short dead time delay is imposed between one switch turning off and the other turning on.
The series combination of a small valued inductor Lc and primary winding, with turns Np, of transformer T1 is connected between the Zs common point of the switches S1 and S2 and the common point of switches S3 and S4. In this and the second embodiment described herein, inductor Lr can be partly or mainly realized by the leakage inductance of the transformer. A large valued inductor Lp is placed across the primary winding of the transformer. Typically this inductance is realized by gapping 3o the core of the transformer to reduce the transformer primary magnetizing inductance to the desired value, though it could also be realized as a separate inductor.
The secondary of transformer T1 consists of two windings, of identical s number of turns Ns, which are connected in series and phased as shown in the figure. The two opposite ends of the windings are connected to the anode poles of first and second diodes D1 and D2 respectively. The common point of the secondary windings of T1 is connected to one end of each of the three windings of inductor Lo, of N1, N2 and N3 turns, which are io phased as shown in the figure. The other end of the second inductor winding with N2 turns is connected to the anode pole of third diode D3. The cathode poles of the diodes D1 D2 and D3 are connected together and to one end of output capacitor Co and to one output terminal. The other end of the main (first) winding of inductor Lo, of turns N1, is connected to a is inductance LI. The other end of inductance LI is connected to the other end of output capacitor Co and a second output terminal. The other end of the third inductor winding of N3 turns is connected to one pole of capacitor Cf, which can be of a value much smaller than Co. The other pole of Cf is connected to the cathodes of D1 D2 and D3. The inductance LI can be Zo realized by the leakage inductance between the main and third windings or by a discrete inductance. This leakage inductance could be increased by adding a second core to the inductor encompassing only the main winding, however even a small value of inductance achieved by normal separation of the windings works very well as long as the windings N2 and N3 are closely Zs coupled. Typically the turns of the third winding (N3) are equal to the turns of the main winding (N1 ). The turns of the winding connected to third diode D3 are typically half that of the other two windings.
The embodiment of FIG. 2 is identical to the first embodiment except 3o that a DC blocking capacitor Cb is added in series with the inductor Lc and io the parallel combination of the primary winding of T1 and the inductance Lp.
This series combination can be in any order. The capacitor Cb is useful to block any residual DC voltage or DC current, which can otherwise result from imbalances in the drive times, from being impressed across the s primary of transformer T1 or the inductance Lp.
In the embodiment of FIG. 3 a forth winding of turns Nr is added to the transformer T1 to allow clamping of the peak voltage across of D1, D2 or D3 when they turn off. A relatively small valued capacitor Cr is io connected in series with this winding, the other end of which is connected to one of the input terminals. The other end of the winding is connected to diodes Dr1 and Dr2 whose other poles are connected to the input terminals in such a polarity to block the applied voltage Vs. This additional circuit returns the energy stored in the commutation inductance Lc, due to the is reverse recovery current of diodes D1, D2 and D3, back to the source improving the converter efficiency and minimizing the excess voltage spikes on diodes D1, D2 and D3 when they turn off. In this embodiment it is preferred that the majority of the inductance Lc be realized by a discrete inductor and that the leakage inductance of T1 is minimized. This can be Zo achieved by realizing the primary or secondary windings) of the transformer as two portions, connected in series or parallel, sandwiching the other windings in between the two portions. The relatively small value of Cr prevents flow of excess current during transient conditions and aids in reducing the spike voltage on D1, D2 and D3 due to the unclamped leakage Zs inductance of T1. This forth winding can be realized by two windings connected in parallel if the transformer primary or secondary windings) is actually in two portions to create a sandwich structure. In this embodiment the number of turns Nr will typically be half that of the primary winding, though a slight increase of turns from this value will improve clamping action 3o at the expense of more energy being returned to the source.
n FIG. 3A shows essentially the same embodiment as FIG. 3 except that the function of Capacitor Cr is realized by two Capacitors Cr1 and Cr2 both connected to the first end of the forth transformer winding. The other pole of s the capacitor Cr1 is connected to one input terminals and the other pole of Cr2 is connected to the other input terminal. Capacitors Cr1 and Cr2 each have half the value of Cr of FIG. 3 for the same effective operation. This embodiment would be preferred over that of FIG.3 in that its clamping action at the initial start up time of the converter will be balanced.
to The embodiment of FIG. 4 is similar to the embodiment of FIG. 3 except that the other end of capacitor Cr is connected to the common point of a series connection of diodes Dr3 and Dr4 whose other poles are also connected to the input terminals in such a polarity to block the applied is voltage Vs. In this case the turns of winding Nr will be equal or slightly more than the primary winding turns Np. This embodiment returns the energy stored in the inductor Lc and clamps the spike voltage across D1, D2, and D3 in much the same manner as that of that of FIG. 3.
2o Yet a further aspect of the invention is a method and apparatus to control the peak current in the inductor Lp to a constant value despite the output voltage of the converter being varied by adjustment of the output voltage to different values or by the converter entering into a current limiting control region. This method entails measuring the output voltage of the 2s converter directly, (which is easily done if the control circuit is on the secondary side of the converter) or indirectly using an isolated observer circuit (needed if the control circuit is on the primary side) comparing it to a reference voltage with a error amplifier of fixed gain and generating a signal which reduces the operating frequency of the converter proportional to the 30 output voltage for the normal output voltage range of the converter. Also included in this method is a means to keep the loop gain and operating pulse width or duty cycle of the converter constant despite the frequency being varied. A current source controlled by the same error amplifiers injects a current into the Phase Shift (or PWM) ramp capacitor of the control s circuit to keep the peak ramp voltage constant despite it's ramp time being increased due to lower operating frequency.
In the embodiment of FIG. 5 a fifth winding is added to allow observation of the output voltage of the converter galvanically isolated from to the actual output. Typically this winding only has one turn Nvs. The winding is connected to a half wave rectification circuit (Though a full wave rectification circuit could be used) consisting of Dvs1 and Dvs2 and a voltage averaging circuit consisting of RC time constant Rvs and Cvs much larger than one period of the switching circuit. The output voltage of this is circuit portion Vosim is proportional to the output voltage of the converter Vo except for light loading of the converter whereupon the simulated output voltage is reduced. This does not adversely effect the operation of the converter as the resulting lower operating frequency extends the load range of ZVS of the switches.
FIG. 6 shows a circuit, which can implement the method of keeping the peak current in the inductor Lp to a constant value despite the output voltage of the converter being varied. The circuit is designed to work with a Phase Shift Modulation (PSM) Control IC such as Unitrode UCC2895, but a 2s similar circuit could be devised to work with other PSM or any Pulse Width Modulation Control IC's. The output voltage of the converter is measured directly using a resistive divider or indirectly using a circuit added to the converter as shown in FIG. 5. This input signal Vosim is buffered by an error Operational amplifier configured as a voltage follower. The input 3o signal is then compared to a reference voltage (Pin 8 of UCC2895) by an Operational amplifier with fixed gain determined by input and feedback resistors. A control signal, which varies the operating frequency of the PSM
control IC, is coupled to the frequency determining pin Rt (Pin 8 of UCC2895) by a resistor and diode. A current mirror also controlled by the s error Operational Amplifier injects a current into the ramp capacitor connected to the Ramp pin (Pin 3 of UCC2895).
The circuit operation of the last shown embodiment (FIG 5) being a preferred embodiment of the invention is described following with reference to to FIG. 7 and FIG. 8, representing the voltage and current waveforms of the converter for full load operation. In addition the phase shift control method for the full bridge ZVS converter will be used in the description though other known methods could be used.
is The gate drive voltage waveforms Drive A and Drive B for controlled switches S1 and S2 are shown in FIGS. 7a and 7b respectively. They are non-overlapping complementary rectangular waveforms of zero volts or typically 12 Volts of an equal duty cycle of a little less than 50%. The gate drive waveforms Drive C and Drive D for switches S3 and S4 are shown in ao FIGS. 7c and 7d respectively. These are also non-overlapping complementary waveforms of an equal duty cycle of a little less than 50%.
The two sets of gate drive waveforms are phase shifted with respect to each other by a phase shift angle Phi 1.
Zs FIG. 7e shows the voltage at the common point of controlled switches S1 and S2, Vab. When Drive A is high switch S1 is on causing Vab to be equal to the voltage at the negative input terminal (zero volts). When Drive B is high switch S2 is on causing Vab to be equal to the voltage at the positive input terminal Vin. The gate drive dead time when both Drive A and 3o Drive B are low is selected to be slightly greater that the time for Vab to slew naturally, due to the current in the inductor connected effectively in parallel with the primary of the transformer, from one level to another so that both switches turn on only when the voltage across them is zero volts achieving ZVS. In FIGS. 7 and 8 this time is exaggerated somewhat from s what would typically occur for the sake of clarity.
FIG. 7f shows the voltage waveform at the common point of controlled switches S3 and S4 Vcd, which is identical to Vab except that it is phase shifted by angle Phi 1. FIG. 7g shows the voltage waveform Vab-Vcd to that is applied to the series combination of inductor Lc and the transformer primary Np and paralleled inductor Lp. This is a bipolar pulse waveform with pulse voltage of plus and minus Vs and duty cycle Phi 1/Period. FIG.
7h shows the voltage waveform applied to the primary winding of the transformer. This waveform has the same amplitude as the waveform Vab-is Vcd but has slightly lower duty cycle angle Phi 2 due to the commutation time required to ramp the current up in the inductor Lc. It also has an overshoot after the turn off time of diode D3 (t2-t3 and t9-t10). The clamp winding Nr and associated components clamps this overshoot voltage. The ramp of voltage during the clamp time is caused by the relatively small Zo value of Cr.
The voltage across the secondary windings of the transformer is essentially the same shape as the primary except that it's amplitude will be dependent on the turns ratio of the transformer, Ns/Np. This secondary Zs waveform is rectified by the main secondary rectifier diodes D1 and D2 to produce a uni-polar pulse train voltages. The voltage waveform across diode D1 is shown in FIG. 7i. It is ideally zero volts when diode D1 is conducting and equal to -2Vin*Ns/Np during the phase angle Phi 2. During the other times it is at an intermediate value determined by the windings on 3o the ouput inductor Lo. During normal operation there is a period when both is diodes D1 and D2 are not conducting and then both waveforms are at close to zero volts at the same time. The voltage waveform across diode D2 is shown in FIG. 7j. It is identical to the voltage waveform across D1 except that it is phase shifted 180 degrees. The voltage waveform on the s freewheeling diode D3 is shown in FIG. 7k. It is ideally zero volts when D3 is conducting and is Vin*Ns/Np*(N2+N1 )/N1 when the diode is non-conducting. There is also an overshoot of this voltage waveform when diode D3 stops conducting, the majority of which is clamped by the clamping winding Nr of the transformer and it's associated components.
io The lower initial clamp voltage caused by the relatively small value of Cr reduces a leading edge spike on this overshoot, resulting from the unclamped portion of the transformer leakage inductance.
The output inductor Lo and output capacitor Co average the voltage is waveform across D3 to realize the output voltage of the converter Vo that is present across the output terminals and connected load. The voltage waveform present at the common point of the two secondary windings is shown in FIG. 71. It is similar in shape to the voltage across D3 but is reduced in amplitude by the ratio of the inductor windings N1/(N1+N2). The Zo average of this waveform is also the output voltage Vo and the voltage during the freewheel period is VO*N2/(N1+N2) which is the voltage that reverse polarizes Lc commutating the Diodes D1 and D2 off. The voltage across capacitor Cf is equal to the DC output voltage with a much higher ripple voltage component.
2s The current waveforms for the converter are shown in FIG. 8. The currents flow as a result of the applied load and the voltage waveforms impressed across the various components thus they will be explained in the reverse order. FIG. 8m shows the output current I(RI) that flows through the 30 load is inversely proportional to the applied load resistance. Also shown is is the current in the output inductor main winding I(N1 ) which is equal to the output current plus a small ripple current component that is typically less than 5% of the load current. This ripple current flows through the output capacitor Co. The current in the filter winding I(N3) is also shown in FIG.
s 8m. This is an AC current, of RMS value of typically 10 to 15% of the output current of the converter, which flows through filter capacitor Cf.
FIG. 8i shows the current which flows in output inductor winding of N2 turns and the freewheeling diode D3. This current is of a trapezoidal uni-io polar wave shape which flows when the main output diodes are off or are turning on or ofF. Its peak value is typically two-thirds of the peak value of the current in the main output diodes. Figures 8j and 8k show the waveforms of current in the two main output diodes D1 and D2 respectively.
These currents also flow in the secondary windings Ns1 and Ns2 of the Is transformer respectively. These are two uni-polar trapezoidal waveforms identical except for being phase shifted 180 degrees with respect to each other. These currents start to flow when diagonally opposite switches S1 and S4 or S3 and S2 are on. The currents ramp up at a rate determined by the value of inductor Lc and reach a peak values essentially equal to the Zo output of the converter. The current ramps down at a rate also controlled by the ratio of windings N1 and N2 of the ouput inductor when one of the diagonally opposite switches turns off. A small reverse recovery current of the output diodes is also shown to flow for a short time before the diodes turn off. It is important to note that in normal operation there is a time during Zs which both main output diodes are off and both the transformer secondary currents are zero.
FIG 81 shows the waveform of the current in the primary winding Np of the Transformer. This is an AC current equal to the difference of the two 30 output diode currents times the transformer turns ratio Ns/Np plus small m current pulses which result due to the action of the clamp winding Nr and associated components.
FIG. 8h shows the current in the primary inductor Lp. This AC current s is of a flat topped triangular shape, tamping up or down when diagonally opposite switches are on and remaining at a constant value when one of the switches turns off. This current is used to provide zero voltage switching of the switches and can be controlled, by the method described herein, to be the optimum value to do so despite the output voltage of the converter being io varied.
FIG. 8g shows the current that flows in the clamp winding Nr, through capacitor Cr and the diode bridge consisting of Dr1 to Dr4. This current is a series of small pulses that returns the energy stored in Lc, as a result of is the reverse recovery current of the main output diodes, to the source Vs.
FIG. 8e shows the current that flows through the capacitances Cs1 and Cs2 (half in Cs1 and half in Cs2) during the time that switches S1 and S2 are off. These currents are small pulses start at the value of current in 2o Lc and decay to near zero when the voltage Vab has stewed to the other rail. FIG. 8f shows the current that flows in capacitances Cs3 and Cs4 during the time that both switches S3 and S4 are off . This current is of much larger pulse size decaying only slightly during the stewing time of the Vcd voltage waveform.
FIG's. 8c and 8d show the current waveforms in the parallel combination of S4 and Ds4 and the parallel combination of S3 and Ds3 respectively. These waveforms are identical except they are phase shifted 180 degrees. The current is initially at a large negative value flowing 3o through the diode when the voltage across the switch becomes zero, then is decays to the value of the peak current in Lp as the respective main output diode turns off, then stays at this value until the other diagonally opposite switch is turned off. It then ramps positive as the current ramps up in Lc and becomes equal to the sum of the transformer primary current I(Np) and s the current in Lp as the other main output diode takes over the load. It drops sharply to zero when the respective switch S4 or S3 is turned off.
FIG's. 8a and 8b shows the waveform of the current in the parallel combination of S1 and Ds1 and the parallel combination of S2 and Ds2 to respectively. These waveforms are identical except they are phase shifted 180 degrees. The current is initially at a small negative value when the voltage across the switch reaches zero then ramps positive and becomes equal to the sum of the transformer primary current I(Np) and the current in Lp, as the current ramps up in Lc and the respective main output diode is takes over the load. It ramps down to the value of current in Lp only, as a result of the action of winding N2 of the output inductor when the diagonally opposite switch turns off. It then drops sharply to zero when the respective switch S1 or S2 turns off.
Zo As can be seen by the voltage and current waveforms that the described DC/DC converter achieves zero voltage switching of the primary side controlled switches at full load. As the main output diodes are commutated off before the diagonally opposite switches are both turned off and that the Bridge leg voltages are stewed by the current in Lp (which is Zs independent of the load) it can also achieve zero voltage switching over a very wide load range, typically down to 10% load. The converter has minimal loss of output voltage due to the commutation time of the load current as the current to commutate is reduced as the main output diodes are commutated off already and loss of output voltage only occurs as a 3o result of the time to commutate the diodes on. The output voltage is infact increased, by the action of the winding N2 of the output inductor, over that of the 'Traditional' Phase Shifted Bridge Converter. The converter minimizes the rate of turn off (dl/dT) of the output diodes achieving Zero current switching of all output diodes It provides a non-pulsating current s due to the action of filter winding N3 of the output inductor and capacitor Cf .
ft can be also seen that the converter has no additional controlled switches, and no extra non-controlled switches in series with the current path, extra diode D3 is in parallel with the current path so no loss in efficiency results.
The described converter also has no additional magnetic components, only io two extra windings in the output inductor. Additionally a means is provided, by transformer winding Nr and associated components, to recover the energy stored in the commutation inductance and part of the transformer leakage inductance caused by the reverse recovery of the output diodes and return this energy to the source. This means also clamps the reverse is spike voltage on the main output diodes. Additionally a method is described herein which allows control of the peak current in the parallel inductance Lp to be at a constant value, optimum to achieve ZVS of the controlled switches despite the output voltage of the converter being varied by adjustment.
It will be appreciated by those skilled in the art that modifications to the preferred embodiments described herein, including electrical equivalents, may be made without departing from the principles of the invention or the scope of the claims. For example the polarity of the output 2s diodes and l or controlled switches could be reversed thereby allowing operation of the circuits with negative outputs or inputs. Also additional circuit elements, well known by those skilled in the art, such as RC dampers on certain elements may be desired to achieve optimum operation of the invention. In addition a saturable reactor or ferrite beads may be added in series with the output diodes to reduce their reverse recovery current without departing from the scope of the invention or the claims.
disclose adding two extra diodes, a capacitor and inductor to the output circuit.
to All of these previously disclosed circuits either add extra magnetic elements, or non controlled switches in series with the primary or secondary current paths or extra controlled switches to the original ZVS Full Bridge Converter. This significantly increases the size, cost and / or reduces the is efficiency of the resulting converter from that of the original ZVT Fulf Bridge Converter.
The output diodes in a ZVT Full bridge Converter typically have significant reverse recovery time, which results in energy being stored in the Zo series commutation inductor. This energy causes large voltage spikes to be present across these diodes as they turn off and can generate substantial EMI. William McLyman discloses in US Patent 4245288 a way to reduce these diode recovery spikes in a Buck Converter by adding a tap-up winding to the output inductor and connecting a commutation diode to the end of the Zs tap, however with the tap-up ratio necessary to achieve acceptably fast current commutation the output current of the Buck Converter will become pulsating. Also it is desirable to recover the energy stored in the series commutation inductor as a result of the reverse recovery current in the output diodes and return it to the source or the Load. For the Traditional PSB Converter, Richard Redl discloses in US Patent 5198969 a way to return the stored energy to the source by adding two diodes.
It is accordingly an object of the invention to provide a new and s improved isolated Full Bridge Zero Voltage Transition DC to DC Converter suitable for High output Power and medium and low output Voltages.
An object of the invention is to provide a Full Bridge DC to DC
Converter that can achieve Zero Voltage Switching of the primary side io controlled switches over a very wide load range, has minimal loss of output voltage due to the commutation time of the load current, reduces the excess current flowing in the transformer and primary controlled switches to zero during the freewheel interval, minimizes the rate of turn off (dl/dT) of the output diodes and provides a non-pulsating output current to the load. It is is an object of the invention to achieve the above performance improvements without adding extra magnetic components, any extra controlled switching devices, or any additional non-controlled switches in series with the current paths.
Zo An additional object of the invention is to provide a means to recover all the stored energy in the commutation inductor as a result of the reverse recovery current in the output diodes and some of the stored energy in the leakage inductance of the transformer and return this energy to the source.
Zs An additional object of the invention is to provide a method to control the energy stored in the inductor which is connected effectively in parallel to the transformer primary, to constant so that it can be just sufficient to achieve Zero Voltage Switching of the controlled switches for different output voltage adjustment of the DC/DC converter.
S
SUMMMARY OF THE INVENTION
In one of it's aspects the invention consists of a switch mode DC to DC converter comprising of a full bridge arrangement of controlled switches at the input stage, a commutation inductance connected in series with transformer primary winding and an inductance placed effectively in parallel io with the primary winding, and a output stage including a center tapped secondary winding of the transformer, an output diode connected to each end of the center tapped winding, the other pole of the output diodes are connected together and to a first pole of the output capacitor, first output inductor winding connected between the secondary winding center tap and is the other pole of the output capacitor, second output inductor winding connected between the transformer center tap and a third output diode whose other pole is connected to the common point of the other two output diodes, third output inductor winding connected between the transformer center tap and a output filter capacitor whose other pole is connected to the Zo first pole of the output filter capacitor, and output terminals connected to each end of the output capacitor to which the load can be connected.
The primary stage is realized by a full bridge arrangement of controlled switches. Two controlled switches are connected in series with Zs another and in parallel with the input terminals and with a further two controlled switches, which are also connected in series with each other.
Anti-parallel diode means are associated with each switch and are poled to allow current to flow in a direction opposite to the normal direction of current flow in each switch. Capacitance means is also effectively connected in 3o parallel with each switch. An inductance means and optionally also a DC
blocking capacitor means is connected in series with the transformer primary winding, the series combination of the inductance means, primary winding and optional DC blocking capacitor is connected between the common point of the first two controlled switches on the one hand and the s common point of the further two controlled switches on the other hand.
In another aspect of the invention one or more additional windings are added to the transformer, the windings if more than one are connected in parallel with each other, a small valued capacitor is connected in series with io these windings. The series combination of windings) and capacitor is connected to a half bridge or full bridge diode rectification circuit connected in parallel with the input terminals of the converter.
Another aspect of the invention is a method and apparatus to control is the peak current in the inductance connected effectively in parallel with the primary of the transformer. The output voltage of the converter is measured directly or indirectly by means of an additional winding in the transformer, whose voltage is rectified and averaged to provide a representation of the output voltage. The operating frequency of the converter is then varied, by a ao suitable circuit, to be inversely proportional to this measured voltage.
This keeps the volt seconds integral across the inductance constant, thus the peak current constant despite the output voltage being varied due to adjustment or if the DC to DC converter enters into current limit condition.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of one embodiment of the invention s FIG. 2 is a circuit diagram of the invention with the primary DC
blocking capacitor.
FIG. 3 is a circuit diagram of the invention with a half bridge energy recovery circuit.
io FIG. 4 is a circuit diagram of the invention with a full bridge energy recovery circuit.
FIG. 5 is a circuit diagram of the invention with a output voltage is simulation winding and with a full bridge energy recovery circuit.
FIG. 6 is a circuit diagram of a control circuit for the invention including the invented method of controlling the peak current in the parallel inductance Lp to be constant despite the output voltage on the converter ao being changed.
FIG. 7 is a set of voltage waveforms for the embodiment of the invention of FIG. 5.
is FIG. 8 is a set of current waveforms of the embodiment of the invention of FIG. 5.
s DETAILED DESCRIPTION OF THE PREFERRED
AND OTHER EMBODIMENTS
The basic schematic of one embodiment of the invention is shown in s FIG. 1. The converter is connected to a voltage source Vs by input terminals. Two sets of half bridges of controlled switches are connected to the input terminals and thus are connected in parallel with the voltage source Vs. The first half bridge consists of a series combination of controlled switches S1 and S2, which are typically MOSFET's. These io switches have diodes Ds1 and Ds2 placed across them in such a direction that allows current to flow in the opposite direction to the switches. If MOSFET's are used for S1 and S2 then integral diodes inherent in them can be utilized as Ds1 and Ds2. Capacitors Cs1 and Cs2 are placed across S1 and S2 respectively and similarly can be partly or completely realized by is the MOSFET capacitance. The second half bridge similarly consists of controlled switches S3 and S4, diodes Ds3 and Ds4 and capacitors Cs3 and Cs4. The switches S1, S2, S3, and S4 are turned on and off by drive signals Drive A, Drive B, Drive C, and Drive D respectively. The drive waveforms are organized so that only one switch of a series combination is Zo on at any one time and a short dead time delay is imposed between one switch turning off and the other turning on.
The series combination of a small valued inductor Lc and primary winding, with turns Np, of transformer T1 is connected between the Zs common point of the switches S1 and S2 and the common point of switches S3 and S4. In this and the second embodiment described herein, inductor Lr can be partly or mainly realized by the leakage inductance of the transformer. A large valued inductor Lp is placed across the primary winding of the transformer. Typically this inductance is realized by gapping 3o the core of the transformer to reduce the transformer primary magnetizing inductance to the desired value, though it could also be realized as a separate inductor.
The secondary of transformer T1 consists of two windings, of identical s number of turns Ns, which are connected in series and phased as shown in the figure. The two opposite ends of the windings are connected to the anode poles of first and second diodes D1 and D2 respectively. The common point of the secondary windings of T1 is connected to one end of each of the three windings of inductor Lo, of N1, N2 and N3 turns, which are io phased as shown in the figure. The other end of the second inductor winding with N2 turns is connected to the anode pole of third diode D3. The cathode poles of the diodes D1 D2 and D3 are connected together and to one end of output capacitor Co and to one output terminal. The other end of the main (first) winding of inductor Lo, of turns N1, is connected to a is inductance LI. The other end of inductance LI is connected to the other end of output capacitor Co and a second output terminal. The other end of the third inductor winding of N3 turns is connected to one pole of capacitor Cf, which can be of a value much smaller than Co. The other pole of Cf is connected to the cathodes of D1 D2 and D3. The inductance LI can be Zo realized by the leakage inductance between the main and third windings or by a discrete inductance. This leakage inductance could be increased by adding a second core to the inductor encompassing only the main winding, however even a small value of inductance achieved by normal separation of the windings works very well as long as the windings N2 and N3 are closely Zs coupled. Typically the turns of the third winding (N3) are equal to the turns of the main winding (N1 ). The turns of the winding connected to third diode D3 are typically half that of the other two windings.
The embodiment of FIG. 2 is identical to the first embodiment except 3o that a DC blocking capacitor Cb is added in series with the inductor Lc and io the parallel combination of the primary winding of T1 and the inductance Lp.
This series combination can be in any order. The capacitor Cb is useful to block any residual DC voltage or DC current, which can otherwise result from imbalances in the drive times, from being impressed across the s primary of transformer T1 or the inductance Lp.
In the embodiment of FIG. 3 a forth winding of turns Nr is added to the transformer T1 to allow clamping of the peak voltage across of D1, D2 or D3 when they turn off. A relatively small valued capacitor Cr is io connected in series with this winding, the other end of which is connected to one of the input terminals. The other end of the winding is connected to diodes Dr1 and Dr2 whose other poles are connected to the input terminals in such a polarity to block the applied voltage Vs. This additional circuit returns the energy stored in the commutation inductance Lc, due to the is reverse recovery current of diodes D1, D2 and D3, back to the source improving the converter efficiency and minimizing the excess voltage spikes on diodes D1, D2 and D3 when they turn off. In this embodiment it is preferred that the majority of the inductance Lc be realized by a discrete inductor and that the leakage inductance of T1 is minimized. This can be Zo achieved by realizing the primary or secondary windings) of the transformer as two portions, connected in series or parallel, sandwiching the other windings in between the two portions. The relatively small value of Cr prevents flow of excess current during transient conditions and aids in reducing the spike voltage on D1, D2 and D3 due to the unclamped leakage Zs inductance of T1. This forth winding can be realized by two windings connected in parallel if the transformer primary or secondary windings) is actually in two portions to create a sandwich structure. In this embodiment the number of turns Nr will typically be half that of the primary winding, though a slight increase of turns from this value will improve clamping action 3o at the expense of more energy being returned to the source.
n FIG. 3A shows essentially the same embodiment as FIG. 3 except that the function of Capacitor Cr is realized by two Capacitors Cr1 and Cr2 both connected to the first end of the forth transformer winding. The other pole of s the capacitor Cr1 is connected to one input terminals and the other pole of Cr2 is connected to the other input terminal. Capacitors Cr1 and Cr2 each have half the value of Cr of FIG. 3 for the same effective operation. This embodiment would be preferred over that of FIG.3 in that its clamping action at the initial start up time of the converter will be balanced.
to The embodiment of FIG. 4 is similar to the embodiment of FIG. 3 except that the other end of capacitor Cr is connected to the common point of a series connection of diodes Dr3 and Dr4 whose other poles are also connected to the input terminals in such a polarity to block the applied is voltage Vs. In this case the turns of winding Nr will be equal or slightly more than the primary winding turns Np. This embodiment returns the energy stored in the inductor Lc and clamps the spike voltage across D1, D2, and D3 in much the same manner as that of that of FIG. 3.
2o Yet a further aspect of the invention is a method and apparatus to control the peak current in the inductor Lp to a constant value despite the output voltage of the converter being varied by adjustment of the output voltage to different values or by the converter entering into a current limiting control region. This method entails measuring the output voltage of the 2s converter directly, (which is easily done if the control circuit is on the secondary side of the converter) or indirectly using an isolated observer circuit (needed if the control circuit is on the primary side) comparing it to a reference voltage with a error amplifier of fixed gain and generating a signal which reduces the operating frequency of the converter proportional to the 30 output voltage for the normal output voltage range of the converter. Also included in this method is a means to keep the loop gain and operating pulse width or duty cycle of the converter constant despite the frequency being varied. A current source controlled by the same error amplifiers injects a current into the Phase Shift (or PWM) ramp capacitor of the control s circuit to keep the peak ramp voltage constant despite it's ramp time being increased due to lower operating frequency.
In the embodiment of FIG. 5 a fifth winding is added to allow observation of the output voltage of the converter galvanically isolated from to the actual output. Typically this winding only has one turn Nvs. The winding is connected to a half wave rectification circuit (Though a full wave rectification circuit could be used) consisting of Dvs1 and Dvs2 and a voltage averaging circuit consisting of RC time constant Rvs and Cvs much larger than one period of the switching circuit. The output voltage of this is circuit portion Vosim is proportional to the output voltage of the converter Vo except for light loading of the converter whereupon the simulated output voltage is reduced. This does not adversely effect the operation of the converter as the resulting lower operating frequency extends the load range of ZVS of the switches.
FIG. 6 shows a circuit, which can implement the method of keeping the peak current in the inductor Lp to a constant value despite the output voltage of the converter being varied. The circuit is designed to work with a Phase Shift Modulation (PSM) Control IC such as Unitrode UCC2895, but a 2s similar circuit could be devised to work with other PSM or any Pulse Width Modulation Control IC's. The output voltage of the converter is measured directly using a resistive divider or indirectly using a circuit added to the converter as shown in FIG. 5. This input signal Vosim is buffered by an error Operational amplifier configured as a voltage follower. The input 3o signal is then compared to a reference voltage (Pin 8 of UCC2895) by an Operational amplifier with fixed gain determined by input and feedback resistors. A control signal, which varies the operating frequency of the PSM
control IC, is coupled to the frequency determining pin Rt (Pin 8 of UCC2895) by a resistor and diode. A current mirror also controlled by the s error Operational Amplifier injects a current into the ramp capacitor connected to the Ramp pin (Pin 3 of UCC2895).
The circuit operation of the last shown embodiment (FIG 5) being a preferred embodiment of the invention is described following with reference to to FIG. 7 and FIG. 8, representing the voltage and current waveforms of the converter for full load operation. In addition the phase shift control method for the full bridge ZVS converter will be used in the description though other known methods could be used.
is The gate drive voltage waveforms Drive A and Drive B for controlled switches S1 and S2 are shown in FIGS. 7a and 7b respectively. They are non-overlapping complementary rectangular waveforms of zero volts or typically 12 Volts of an equal duty cycle of a little less than 50%. The gate drive waveforms Drive C and Drive D for switches S3 and S4 are shown in ao FIGS. 7c and 7d respectively. These are also non-overlapping complementary waveforms of an equal duty cycle of a little less than 50%.
The two sets of gate drive waveforms are phase shifted with respect to each other by a phase shift angle Phi 1.
Zs FIG. 7e shows the voltage at the common point of controlled switches S1 and S2, Vab. When Drive A is high switch S1 is on causing Vab to be equal to the voltage at the negative input terminal (zero volts). When Drive B is high switch S2 is on causing Vab to be equal to the voltage at the positive input terminal Vin. The gate drive dead time when both Drive A and 3o Drive B are low is selected to be slightly greater that the time for Vab to slew naturally, due to the current in the inductor connected effectively in parallel with the primary of the transformer, from one level to another so that both switches turn on only when the voltage across them is zero volts achieving ZVS. In FIGS. 7 and 8 this time is exaggerated somewhat from s what would typically occur for the sake of clarity.
FIG. 7f shows the voltage waveform at the common point of controlled switches S3 and S4 Vcd, which is identical to Vab except that it is phase shifted by angle Phi 1. FIG. 7g shows the voltage waveform Vab-Vcd to that is applied to the series combination of inductor Lc and the transformer primary Np and paralleled inductor Lp. This is a bipolar pulse waveform with pulse voltage of plus and minus Vs and duty cycle Phi 1/Period. FIG.
7h shows the voltage waveform applied to the primary winding of the transformer. This waveform has the same amplitude as the waveform Vab-is Vcd but has slightly lower duty cycle angle Phi 2 due to the commutation time required to ramp the current up in the inductor Lc. It also has an overshoot after the turn off time of diode D3 (t2-t3 and t9-t10). The clamp winding Nr and associated components clamps this overshoot voltage. The ramp of voltage during the clamp time is caused by the relatively small Zo value of Cr.
The voltage across the secondary windings of the transformer is essentially the same shape as the primary except that it's amplitude will be dependent on the turns ratio of the transformer, Ns/Np. This secondary Zs waveform is rectified by the main secondary rectifier diodes D1 and D2 to produce a uni-polar pulse train voltages. The voltage waveform across diode D1 is shown in FIG. 7i. It is ideally zero volts when diode D1 is conducting and equal to -2Vin*Ns/Np during the phase angle Phi 2. During the other times it is at an intermediate value determined by the windings on 3o the ouput inductor Lo. During normal operation there is a period when both is diodes D1 and D2 are not conducting and then both waveforms are at close to zero volts at the same time. The voltage waveform across diode D2 is shown in FIG. 7j. It is identical to the voltage waveform across D1 except that it is phase shifted 180 degrees. The voltage waveform on the s freewheeling diode D3 is shown in FIG. 7k. It is ideally zero volts when D3 is conducting and is Vin*Ns/Np*(N2+N1 )/N1 when the diode is non-conducting. There is also an overshoot of this voltage waveform when diode D3 stops conducting, the majority of which is clamped by the clamping winding Nr of the transformer and it's associated components.
io The lower initial clamp voltage caused by the relatively small value of Cr reduces a leading edge spike on this overshoot, resulting from the unclamped portion of the transformer leakage inductance.
The output inductor Lo and output capacitor Co average the voltage is waveform across D3 to realize the output voltage of the converter Vo that is present across the output terminals and connected load. The voltage waveform present at the common point of the two secondary windings is shown in FIG. 71. It is similar in shape to the voltage across D3 but is reduced in amplitude by the ratio of the inductor windings N1/(N1+N2). The Zo average of this waveform is also the output voltage Vo and the voltage during the freewheel period is VO*N2/(N1+N2) which is the voltage that reverse polarizes Lc commutating the Diodes D1 and D2 off. The voltage across capacitor Cf is equal to the DC output voltage with a much higher ripple voltage component.
2s The current waveforms for the converter are shown in FIG. 8. The currents flow as a result of the applied load and the voltage waveforms impressed across the various components thus they will be explained in the reverse order. FIG. 8m shows the output current I(RI) that flows through the 30 load is inversely proportional to the applied load resistance. Also shown is is the current in the output inductor main winding I(N1 ) which is equal to the output current plus a small ripple current component that is typically less than 5% of the load current. This ripple current flows through the output capacitor Co. The current in the filter winding I(N3) is also shown in FIG.
s 8m. This is an AC current, of RMS value of typically 10 to 15% of the output current of the converter, which flows through filter capacitor Cf.
FIG. 8i shows the current which flows in output inductor winding of N2 turns and the freewheeling diode D3. This current is of a trapezoidal uni-io polar wave shape which flows when the main output diodes are off or are turning on or ofF. Its peak value is typically two-thirds of the peak value of the current in the main output diodes. Figures 8j and 8k show the waveforms of current in the two main output diodes D1 and D2 respectively.
These currents also flow in the secondary windings Ns1 and Ns2 of the Is transformer respectively. These are two uni-polar trapezoidal waveforms identical except for being phase shifted 180 degrees with respect to each other. These currents start to flow when diagonally opposite switches S1 and S4 or S3 and S2 are on. The currents ramp up at a rate determined by the value of inductor Lc and reach a peak values essentially equal to the Zo output of the converter. The current ramps down at a rate also controlled by the ratio of windings N1 and N2 of the ouput inductor when one of the diagonally opposite switches turns off. A small reverse recovery current of the output diodes is also shown to flow for a short time before the diodes turn off. It is important to note that in normal operation there is a time during Zs which both main output diodes are off and both the transformer secondary currents are zero.
FIG 81 shows the waveform of the current in the primary winding Np of the Transformer. This is an AC current equal to the difference of the two 30 output diode currents times the transformer turns ratio Ns/Np plus small m current pulses which result due to the action of the clamp winding Nr and associated components.
FIG. 8h shows the current in the primary inductor Lp. This AC current s is of a flat topped triangular shape, tamping up or down when diagonally opposite switches are on and remaining at a constant value when one of the switches turns off. This current is used to provide zero voltage switching of the switches and can be controlled, by the method described herein, to be the optimum value to do so despite the output voltage of the converter being io varied.
FIG. 8g shows the current that flows in the clamp winding Nr, through capacitor Cr and the diode bridge consisting of Dr1 to Dr4. This current is a series of small pulses that returns the energy stored in Lc, as a result of is the reverse recovery current of the main output diodes, to the source Vs.
FIG. 8e shows the current that flows through the capacitances Cs1 and Cs2 (half in Cs1 and half in Cs2) during the time that switches S1 and S2 are off. These currents are small pulses start at the value of current in 2o Lc and decay to near zero when the voltage Vab has stewed to the other rail. FIG. 8f shows the current that flows in capacitances Cs3 and Cs4 during the time that both switches S3 and S4 are off . This current is of much larger pulse size decaying only slightly during the stewing time of the Vcd voltage waveform.
FIG's. 8c and 8d show the current waveforms in the parallel combination of S4 and Ds4 and the parallel combination of S3 and Ds3 respectively. These waveforms are identical except they are phase shifted 180 degrees. The current is initially at a large negative value flowing 3o through the diode when the voltage across the switch becomes zero, then is decays to the value of the peak current in Lp as the respective main output diode turns off, then stays at this value until the other diagonally opposite switch is turned off. It then ramps positive as the current ramps up in Lc and becomes equal to the sum of the transformer primary current I(Np) and s the current in Lp as the other main output diode takes over the load. It drops sharply to zero when the respective switch S4 or S3 is turned off.
FIG's. 8a and 8b shows the waveform of the current in the parallel combination of S1 and Ds1 and the parallel combination of S2 and Ds2 to respectively. These waveforms are identical except they are phase shifted 180 degrees. The current is initially at a small negative value when the voltage across the switch reaches zero then ramps positive and becomes equal to the sum of the transformer primary current I(Np) and the current in Lp, as the current ramps up in Lc and the respective main output diode is takes over the load. It ramps down to the value of current in Lp only, as a result of the action of winding N2 of the output inductor when the diagonally opposite switch turns off. It then drops sharply to zero when the respective switch S1 or S2 turns off.
Zo As can be seen by the voltage and current waveforms that the described DC/DC converter achieves zero voltage switching of the primary side controlled switches at full load. As the main output diodes are commutated off before the diagonally opposite switches are both turned off and that the Bridge leg voltages are stewed by the current in Lp (which is Zs independent of the load) it can also achieve zero voltage switching over a very wide load range, typically down to 10% load. The converter has minimal loss of output voltage due to the commutation time of the load current as the current to commutate is reduced as the main output diodes are commutated off already and loss of output voltage only occurs as a 3o result of the time to commutate the diodes on. The output voltage is infact increased, by the action of the winding N2 of the output inductor, over that of the 'Traditional' Phase Shifted Bridge Converter. The converter minimizes the rate of turn off (dl/dT) of the output diodes achieving Zero current switching of all output diodes It provides a non-pulsating current s due to the action of filter winding N3 of the output inductor and capacitor Cf .
ft can be also seen that the converter has no additional controlled switches, and no extra non-controlled switches in series with the current path, extra diode D3 is in parallel with the current path so no loss in efficiency results.
The described converter also has no additional magnetic components, only io two extra windings in the output inductor. Additionally a means is provided, by transformer winding Nr and associated components, to recover the energy stored in the commutation inductance and part of the transformer leakage inductance caused by the reverse recovery of the output diodes and return this energy to the source. This means also clamps the reverse is spike voltage on the main output diodes. Additionally a method is described herein which allows control of the peak current in the parallel inductance Lp to be at a constant value, optimum to achieve ZVS of the controlled switches despite the output voltage of the converter being varied by adjustment.
It will be appreciated by those skilled in the art that modifications to the preferred embodiments described herein, including electrical equivalents, may be made without departing from the principles of the invention or the scope of the claims. For example the polarity of the output 2s diodes and l or controlled switches could be reversed thereby allowing operation of the circuits with negative outputs or inputs. Also additional circuit elements, well known by those skilled in the art, such as RC dampers on certain elements may be desired to achieve optimum operation of the invention. In addition a saturable reactor or ferrite beads may be added in series with the output diodes to reduce their reverse recovery current without departing from the scope of the invention or the claims.
Claims (17)
1. A switch mode DC to DC converter comprising a full bridge arrangement of controlled switches and a first inductance means connected in series with transformer primary winding and a second inductance means is placed effectively in parallel with the primary winding at the input stage, and a output stage including a center tapped secondary winding of the transformer, an output diode connected to each end of the center tapped winding, the other pole of the output diodes are connected together and to a first pole of the output capacitor, a first output inductor winding is placed effectively in series and with a second inductor means the series combination of which is connected between the secondary winding center tap and to the other pole of the output capacitor, a second output inductor winding connected between the transformer center tap and a third output diode whose other pole is connected to the common point of the other two output diodes, and a third output inductor winding connected between the transformer center tap and a output filter capacitor whose other pole is connected to the first pole of the output filter capacitor, and output terminals connected to each end of the output capacitor to which the load can be connected.
2. A switch mode DC to DC converter as in claim 1 wherein the full bridge arrangement of controlled switches consists of two controlled switches which are connected in series with another and in parallel with the input terminals and a further two controlled switches, which are also connected in series with each other and anti-parallel diode means are associated with each switch and are poled to allow current to flow in a direction opposite to the normal direction of current flow in each switch, and capacitance means is also effectively connected in parallel with each switch, and the first inductance means is connected in series with the transformer primary winding and the series combination of the second inductance means and transformer primary winding is connected between the common point of the first two controlled switches on the one hand and the common point of the further two controlled switches on the other hand.
3. The switch mode DC to DC converter as in claim 1 or 2 wherein a DC blocking capacitance means is added in series with the series combination of inductance means and parallel combination of the transformer primary winding and the paralelled inductance means.
4. The switch mode DC to DC converter as in claim 1, 2 or 3 wherein the inductance means connected in parallel with the transformer is realized by reducing the magnetizing inductance of the transformer primary winding to the desired value by gapping the transformer core with one or more gaps or by using a distributed gap core material.
5. The switch mode converter as in claim 1, 2, 3 or 4 wherein the series inductance means is realized by the leakage inductance of the transformer.
6. The switch mode converter as in claim 1, 2, 3 or 4 wherein the series inductance means is realized by a discrete inductor and the leakage inductance of the transformer.
7. The switch mode DC/DC converter as in claim 6 wherein the leakage inductance of the transformer is minimized by realizing the transformer primary winding as two portions connected in series or parallel with each other and placing the secondary windings of the transformer in between the two primaries in a sandwich structure.
8. The switch mode DC/DC converter as in claims 6 or 7 wherein one or more additional windings are added to the transformer, the windings if more than one are of equal turns and are connected in parallel with each other and a capacitor is connected in series with these windings. The series combination of winding(s) and capacitor means is connected to a half bridge diode rectification circuit connected in parallel with the input terminals of the converter and polarized so as to block the voltage across the input terminals.
9. The switch mode DC/DC converter as in claims 6 or 7 wherein one or more additional windings are added to the transformer, the windings if more than one are of equal turns and are connected in parallel with each other and the winging are connected to two capacitor means the other poles of which is connected to each of the input terminals and the other end of the winding(s) is connected to the center tap of a half bridge diode rectification circuit connected in parallel with the input terminals and polarized so as to block the voltage across the input terminals
10. The switch mode DC/DC converter as in claims 6 or 7 wherein one or more additional windings are added to the transformer, the windings if more than one are of equal turns and are connected in parallel with each other and a capacitor means is connected in series with these windings, the series combination of winding(s) and capacitor is connected to a full bridge diode rectification circuit connected in parallel with the input terminals of the converter and polarized so as to block the voltage across the input terminals.
11. The switch mode DC/DC converter as in claims 1,2,3,4,5,6,7, 8,9 or 10 wherein the main output inductor winding is closely coupled to the second output inductor winding
12. The switch mode DC/DC converter as in claims 1,2,3,4,5,6,7, 8,9, 10 or 11 wherein second inductance means connected in series with the main output inductor winding is realized by the leakage inductance between the main and third output inductor windings.
13. The switch mode DC/DC converter as in claims 1,2,3,4,5,6,7, 8,9, 10 or 11 wherein the second inductance means connected in series with the main output inductor winding is realized by the leakage inductance between the main and third output inductor windings which is increased by adding a second core to the inductor encompassing only the main output inductor winding.
14. The switch mode DC/DC converter as in claims 1,2,3,4,5,6,7, 8,9, 10 or 11 wherein the second inductance means connected in series with the main output inductor winding is realized by the leakage inductance between the main and third windings and by a second discrete inductor connected in series with the output inductor main winding.
15. The switch mode DC/DC converter as in claims 1,2,3,4,5,6,7, 8,9,10,11,12 13 or 14 wherein a fifth winding is added to the transformer, which is connected to a rectification circuit and a voltage averaging circuit to produce a voltage proportional to the output voltage of the converter Vo, to allow observation of the output voltage of the converter galvanically isolated from the actual output.
16. A method to control the peak current in the inductance connected effectively in parallel with the primary of the transformer, in zero voltage transition bridge DC/DC converters that have the bridge center tap voltage(s) commutated from one input voltage to the other, to be constant consisting of measuring the output voltage of the converter indirectly by means of an additional winding in the transformer, whose voltage is rectified and averaged to provide a representation of the output voltage or directly and varying the operating frequency of the converter to be inversely proportional to this measured voltage and to keep the amplitude of the pulse width or phase shift modulation ramp amplitude constant despite the frequency being varied, by a suitable circuit, to keep the volt seconds integral across the inductance constant, thus keeping the peak current constant despite the output voltage being varied due to adjustment or if the DC/DC converter enters into current limit condition.
17. A circuit, which can be used to implement the method of claim 16 with a Phase Shift Modulation (PSM) control circuit or a Pulse Width Modulation (PWM) control circuit consisting of an error operational amplifier configured as a voltage follower which buffers the indirectly or directly the measured output voltage of the DC/DC
converter and an Operational amplifier with fixed gain determined by input and feedback resistors which compares the buffered voltage to a reference voltage to generate a control signal, which can be used to vary the operating frequency of the PSM or PWM control circuit, and a current mirror also controlled by the error operational amplifier which can inject a current into the ramp capacitor to keep it's amplitude constant despite the frequency of the converter being varied.
converter and an Operational amplifier with fixed gain determined by input and feedback resistors which compares the buffered voltage to a reference voltage to generate a control signal, which can be used to vary the operating frequency of the PSM or PWM control circuit, and a current mirror also controlled by the error operational amplifier which can inject a current into the ramp capacitor to keep it's amplitude constant despite the frequency of the converter being varied.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51739803P | 2003-11-06 | 2003-11-06 | |
| US60/517,398 | 2003-11-06 |
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| CA2458137A1 true CA2458137A1 (en) | 2005-05-06 |
| CA2458137C CA2458137C (en) | 2013-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2458137A Expired - Lifetime CA2458137C (en) | 2003-11-06 | 2004-02-17 | Zero voltage switched full bridge dc/dc converter |
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| CA (1) | CA2458137C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8199544B2 (en) | 2007-09-01 | 2012-06-12 | Brusa Elektronik Ag | Zero-voltage switching power converter |
| CN107370385A (en) * | 2017-08-01 | 2017-11-21 | 合肥华耀电子工业有限公司 | A kind of novel liquid cooling DC/DC power supplys |
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| US8199544B2 (en) | 2007-09-01 | 2012-06-12 | Brusa Elektronik Ag | Zero-voltage switching power converter |
| CN107370385A (en) * | 2017-08-01 | 2017-11-21 | 合肥华耀电子工业有限公司 | A kind of novel liquid cooling DC/DC power supplys |
| CN112234666A (en) * | 2020-09-04 | 2021-01-15 | 宁波唯嘉电子科技有限公司 | Lithium battery charging and discharging circuit of tool lamp |
| CN113489362A (en) * | 2021-07-04 | 2021-10-08 | 西北工业大学 | Novel isolated single-stage four-quadrant inverter for capacitor energy storage |
| CN113489362B (en) * | 2021-07-04 | 2024-01-16 | 西北工业大学 | Isolated single-stage four-quadrant inverter with capacity for energy storage |
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| CN114301305B (en) * | 2021-12-24 | 2024-05-14 | 科华数据股份有限公司 | Voltage regulator and power supply equipment |
| CN114513132A (en) * | 2022-02-23 | 2022-05-17 | 合肥工业大学 | Isolated half-bridge converter and modeling and loop parameter design method thereof |
| CN114513132B (en) * | 2022-02-23 | 2024-03-12 | 合肥工业大学 | Isolation half-bridge converter and modeling and loop parameter design method thereof |
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| CN117277822B (en) * | 2023-11-20 | 2024-01-30 | 威胜能源技术股份有限公司 | Multi-output circuit for battery-changing cabinet and automatic current-sharing control method thereof |
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