CA2310257A1 - Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit - Google Patents
Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit Download PDFInfo
- Publication number
- CA2310257A1 CA2310257A1 CA002310257A CA2310257A CA2310257A1 CA 2310257 A1 CA2310257 A1 CA 2310257A1 CA 002310257 A CA002310257 A CA 002310257A CA 2310257 A CA2310257 A CA 2310257A CA 2310257 A1 CA2310257 A1 CA 2310257A1
- Authority
- CA
- Canada
- Prior art keywords
- sub
- row
- driver circuit
- display driver
- peak current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US97044397A | 1997-11-14 | 1997-11-14 | |
US08/970,443 | 1997-11-14 | ||
PCT/US1998/024267 WO1999026223A1 (en) | 1997-11-14 | 1998-11-13 | Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2310257A1 true CA2310257A1 (en) | 1999-05-27 |
CA2310257C CA2310257C (en) | 2008-06-10 |
Family
ID=25516951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002310257A Expired - Fee Related CA2310257C (en) | 1997-11-14 | 1998-11-13 | Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US20020036634A1 (en) |
EP (1) | EP1031130A1 (en) |
JP (1) | JP2001523845A (en) |
CN (1) | CN1178192C (en) |
CA (1) | CA2310257C (en) |
WO (1) | WO1999026223A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6188377B1 (en) | 1997-11-14 | 2001-02-13 | Aurora Systems, Inc. | Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit |
AU2004241602B2 (en) * | 2003-05-20 | 2008-05-08 | Syndiant, Inc. | Digital backplane |
TWI251187B (en) * | 2004-03-03 | 2006-03-11 | Toppoly Optoelectronics Corp | Data driver and driving method thereof |
JP2009204702A (en) * | 2008-02-26 | 2009-09-10 | Seiko Epson Corp | Electro-optic device, method for driving electro-optic device, and electronic equipment |
CN108701077B (en) * | 2016-05-03 | 2023-11-10 | 拉姆伯斯公司 | Memory component with efficient write operation |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6180226A (en) * | 1984-09-28 | 1986-04-23 | Toshiba Corp | Active matrix driving device |
EP0256879B1 (en) * | 1986-08-18 | 1993-07-21 | Canon Kabushiki Kaisha | Display device |
DE69429242T2 (en) * | 1993-09-09 | 2002-08-14 | Kabushiki Kaisha Toshiba, Kawasaki | DISPLAY DEVICE |
EP0797182A1 (en) * | 1996-03-19 | 1997-09-24 | Hitachi, Ltd. | Active matrix LCD with data holding circuit in each pixel |
-
1998
- 1998-11-13 WO PCT/US1998/024267 patent/WO1999026223A1/en active Application Filing
- 1998-11-13 EP EP98960202A patent/EP1031130A1/en not_active Ceased
- 1998-11-13 CA CA002310257A patent/CA2310257C/en not_active Expired - Fee Related
- 1998-11-13 CN CNB988130645A patent/CN1178192C/en not_active Expired - Lifetime
- 1998-11-13 JP JP2000521504A patent/JP2001523845A/en active Pending
-
2001
- 2001-11-26 US US10/001,036 patent/US20020036634A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CA2310257C (en) | 2008-06-10 |
JP2001523845A (en) | 2001-11-27 |
CN1178192C (en) | 2004-12-01 |
CN1285942A (en) | 2001-02-28 |
EP1031130A1 (en) | 2000-08-30 |
WO1999026223A1 (en) | 1999-05-27 |
US20020036634A1 (en) | 2002-03-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |