CA2273223A1 - Boitier de circuit integre de la taille d'une puce utilisant un interposeur de carte de circuit imprime en polyimide - Google Patents

Boitier de circuit integre de la taille d'une puce utilisant un interposeur de carte de circuit imprime en polyimide Download PDF

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Publication number
CA2273223A1
CA2273223A1 CA002273223A CA2273223A CA2273223A1 CA 2273223 A1 CA2273223 A1 CA 2273223A1 CA 002273223 A CA002273223 A CA 002273223A CA 2273223 A CA2273223 A CA 2273223A CA 2273223 A1 CA2273223 A1 CA 2273223A1
Authority
CA
Canada
Prior art keywords
chip
circuit board
printed circuit
size package
bond pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002273223A
Other languages
English (en)
Other versions
CA2273223C (fr
Inventor
Robert W. Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2273223A1 publication Critical patent/CA2273223A1/fr
Application granted granted Critical
Publication of CA2273223C publication Critical patent/CA2273223C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
CA002273223A 1997-09-29 1998-09-29 Boitier de circuit integre de la taille d'une puce utilisant un interposeur de carte de circuit imprime en polyimide Expired - Lifetime CA2273223C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US93983297A 1997-09-29 1997-09-29
US08/939,832 1997-09-29
PCT/US1998/020467 WO1999017364A1 (fr) 1997-09-29 1998-09-29 Boitier de circuit integre de la taille d'une puce utilisant un interposeur de carte de circuit imprime en polyimide

Publications (2)

Publication Number Publication Date
CA2273223A1 true CA2273223A1 (fr) 1999-04-08
CA2273223C CA2273223C (fr) 2003-11-11

Family

ID=25473815

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002273223A Expired - Lifetime CA2273223C (fr) 1997-09-29 1998-09-29 Boitier de circuit integre de la taille d'une puce utilisant un interposeur de carte de circuit imprime en polyimide

Country Status (2)

Country Link
CA (1) CA2273223C (fr)
WO (1) WO1999017364A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531643B2 (en) 1997-09-11 2009-05-12 Chugai Seiyaku Kabushiki Kaisha Monoclonal antibody inducing apoptosis
US7696325B2 (en) 1999-03-10 2010-04-13 Chugai Seiyaku Kabushiki Kaisha Polypeptide inducing apoptosis
DE60133479T2 (de) 2000-10-20 2009-04-16 Chugai Seiyaku K.K. Modifizierter tpo-agonisten antikörper
JP2004279086A (ja) 2003-03-13 2004-10-07 Konica Minolta Holdings Inc 放射線画像変換パネル及び放射線画像変換パネルの製造方法
JP5057967B2 (ja) 2005-03-31 2012-10-24 中外製薬株式会社 ｓｃ（Ｆｖ）２構造異性体
CN101262885B (zh) 2005-06-10 2015-04-01 中外制药株式会社 含有sc(Fv)2的药物组合物
CA2610987C (fr) 2005-06-10 2013-09-10 Chugai Seiyaku Kabushiki Kaisha Stabilisant pour une preparation de proteine contenant de la meglumine et son utilisation
US7659151B2 (en) 2007-04-12 2010-02-09 Micron Technology, Inc. Flip chip with interposer, and methods of making same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3487524B2 (ja) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5633785A (en) * 1994-12-30 1997-05-27 University Of Southern California Integrated circuit component package with integral passive component
US5714800A (en) * 1996-03-21 1998-02-03 Motorola, Inc. Integrated circuit assembly having a stepped interposer and method

Also Published As

Publication number Publication date
WO1999017364A1 (fr) 1999-04-08
CA2273223C (fr) 2003-11-11

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Effective date: 20181001