CA2256763A1 - Conductors for integrated circuits - Google Patents
Conductors for integrated circuits Download PDFInfo
- Publication number
- CA2256763A1 CA2256763A1 CA002256763A CA2256763A CA2256763A1 CA 2256763 A1 CA2256763 A1 CA 2256763A1 CA 002256763 A CA002256763 A CA 002256763A CA 2256763 A CA2256763 A CA 2256763A CA 2256763 A1 CA2256763 A1 CA 2256763A1
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- Prior art keywords
- substrate
- conductor
- inductor
- trenches
- plates
- Prior art date
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- 239000004020 conductor Substances 0.000 title claims description 51
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 23
- 230000001965 increasing effect Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000011960 computer-aided design Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- MBYLVOKEDDQJDY-UHFFFAOYSA-N tris(2-aminoethyl)amine Chemical compound NCCN(CCN)CCN MBYLVOKEDDQJDY-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The quality factor (Q-value) of spiral inductors or coils (305) in IC-circuits is improved by partially removing the semiconducting substrate (301) under the inductor (305) by etching trenches (303), which are refilled with an isolating material. Hence, the losses caused by the substrate (301) are reduced and the quality factor is increased accordingly. The parasitic capacitance to the substrate (301) is also reduced, increasing the resonance frequency of the inductor (305) and extending the useful frequency range of operation of the inductor. Furthermore, by utilizing the uppermost metals of a multi-layer metal structure in the circuit, additional reduction of losses and parasitic capacitance are also achieved. The use of trenches (303) under metal patterns for loss and capacitance reduction is not limited to spiral inductor layouts, and can be used for any metal line, bond pad, etc.
Description
CA 022~6763 1998-11-30 CONDUCTORS FOR INTEGRATED CIRCUITS
TECHNICAL FIELD
The present invention relates to an electrical conductor in an integrated circuit (IC) having a low loss to a substrate and a method of making such a conductor, in particular to a method of fabricating spiral inductors and also to an integrated circuit inductor.
RAr~r7R-ouND OF THE lwv~ ON
Advanced silicon bipolar, CMOS and BiCMOS circuits are today used for high-speed electronic applications in the 1 - 2 GHz frequency range and they replace circuits previously only possible to implement using devices based on materials found in column III-V in the periodic table.
Inductor elements are often nPe~ in high-frequency circuits when forming blocks like resonators and filters. A problem common to all integrated circuit devices is how to achieve integrated circuit inductors having high quality factors, Q, and high operating frequencies, the operating frequency being limited by the resonance frequency.
The quality factor, Q-value, is the ratio of the stored energy to the loss energy and can be computed for an inductor as Q =
TECHNICAL FIELD
The present invention relates to an electrical conductor in an integrated circuit (IC) having a low loss to a substrate and a method of making such a conductor, in particular to a method of fabricating spiral inductors and also to an integrated circuit inductor.
RAr~r7R-ouND OF THE lwv~ ON
Advanced silicon bipolar, CMOS and BiCMOS circuits are today used for high-speed electronic applications in the 1 - 2 GHz frequency range and they replace circuits previously only possible to implement using devices based on materials found in column III-V in the periodic table.
Inductor elements are often nPe~ in high-frequency circuits when forming blocks like resonators and filters. A problem common to all integrated circuit devices is how to achieve integrated circuit inductors having high quality factors, Q, and high operating frequencies, the operating frequency being limited by the resonance frequency.
The quality factor, Q-value, is the ratio of the stored energy to the loss energy and can be computed for an inductor as Q =
2*~*f*L/R, where f is the operation frequency, L the inductance and R is the resistive losses of the metal, not tAki ng any parasitic losses from an underlying substrate into a~ounL.
Because of the conducting properties of the substrate, the Q-value of the inductor is reduced. By selectively removing the silicon under the inductor, higher Q-values and higher resonance frequencies are obtAine~. The Q-value can be increased by a factor of two by such a removal. The removal can be in the form of a silicon etching process, giving air gaps of several hundred micrometers, see J.Y.C. Chang, A.A. Abidi, M. Gaitan, "Large Susp~n~e~ Inductor on Silicon and Their Use in a 2 ~m CMOS RF
Amplifier~, IEEE Transactions on Electron Devices Vol. 40, No.
5, p. 246, May 1993, but such removals are not regarded as feasible in large production volumes or compatible with silicon CA 022~6763 1998-11-30 IC processes.
Recent advances in processing methods for fabricating integrated circuits on silicon have allowed inductor layouts having higher inductance per area unit of the integrated circuit and lower losses because of reduction of circuit sizes and multiple metal layers using thick oxide in order to better isolate the inductor from the substrate. There are still considerable losses because of the resistivity of the metal and losses in a corresponding substrate on which the ICs are formed. It is difficult to obtain inductor elements having Q-values higher than 5 - 10 in the 1 -2 GHz frequency range using existing methods for processing silicon wafers.
Inductor elements are usually laid out as square-spirals metal stripes, see for instance N.M. Nguyen, R.G. Meyer, "Si IC-Compatible Inductor and LC Passive Filter", IEEE Journal of Solid-State Circuits Vol. 25, No. 4, p. 1028, August 1990.
Furthermore, ICs usually comprise multiple metal layers and up to five layers is now common in complex Very Large-Scale Integration (VLSI) circuits. At least two metal layers are required for spiral layouts, one for the very spiral and one for closing the structure, i.e. for forming a conductor path from the centre of the spiral to an output terminal at the edge of the inductor. The uppermost ones of the metal layers usually have a lower resistivity because of larger thicknesses and should therefore be u~ed.
By using instead a circular spiral, a 10% reduction of the resistance value can be obt~ine~ for an equal inductance value, resulting in an increased Q-value of the inductor formed of the same magnitude. The circular layout is not very well suited for common software used for Computer Aided Design (CAD), but can be replaced ~y an octagonal configuration without increasing the resistance value of the inductor, see S. Chaki, S. Aono, N.
Andoh, Y. Sasaki, N. Tanino, "Loss Reduction of a Spiral Inductor", Technical Report of IEICE, p. 61, ED93-166, MW93-123, lCD93-181(1994-01).
CA 022~6763 1998-11-30 W O 97/45873 PC~/SE97/009~4 A better way of reducing the resistance is to make an inductor having parallel spiral paths in adjacent layers, e.g. to connect the uppermost metal layers in parallel. The Q-value of the inductor can in this way be increased 1.5 - 2 times, at the expense of a lower resonance frequency because of the decreased isolation thickness. By increasing the number of turns of the spiral, the inductance value is made larger. The capacitance of the inductor spiral to the substrate will however also increase, 1~A~; ng to a lower resonance frequency limiting the useful frequency range of operation of the inductor.
Thus U.S. patent 5,446,311 describes such a structure having an inductor formed in multiple metal layer levels in order to reduce the inductor resistance.
Furthermore, the Japanese patent application JP A 07-106 514 discloses a structure similar to the structure described in U.S.
patent 5,446,311, in which the loss due to electrostatic capacity is reduced and the Q-value is increased by forming an inductor which has two spiral metallic paths formed in different metallization layers and which are interconnected by a third layer.
~eep trenches are applied in modern IC processes for isolation of devices. The advantages of such trenches are reduced parasitic capacitances and reduced device spacing. A deep, 5 -20 ~m, and narrow, 1 - 2 ~m, trench is obtAin~ by means of dry etching and refilling it with oxide and undoped poly-silicon or a dielectric material. After the refilling process, the surface of the substrate will be coated with a layer of refilling material and thus be substantially flat so that e.g. metal layers can be placed over the trenches without any restrictions.
Also, in U.S. patents 5,336,921 and 5,372,967 a method of form-ing an inductor in a vertical trench is described. The inductor described aims at eliminating some of the problems encountered with conventional, horizontal inductors on integrated circuits by means of providing a method of fabricating vertical inductors in the shape of an inductive coil in a trench.
. ~ ~ .. .
CA 022~6763 1998-11-30 Further, U.S. patent 5,095,3S7 discloses an inductive structure having low parasitic capacitances for direct integration in semiconductor integrated circuits.
SU~L~RY OF THE INV~W110N
It is an object of the present invention to provide a method whereby conductors having low losses can be obtAin~ in a simple way.
It is another object of the present invention to obtain a structure for integrated circuits, which makes it possible to achieve inductors having high Q-values.
These and other objects are obt~ine~ by using trenches filled with an isolating material under the spiral inductor layout, which increase the effective distance from the metal to the semiconducting substrate. The losses in the substrate of the integrated device and the capacitance to the substrate will then decrease. The Q-value and the resonance frequency of the inductors will increase accordingly.
In a case where only two metal layers are available, the filled trenches may be enough to achieve acceptable Q-values and resonant frequencies.
In another case, where more metal layers are available, typically four to five layers, the spiral should be laid out in the uppermost of the metal layers, furthermore lowering the parasitic capacitance to the substrate, already lowered by the filled trenches in the substrate, giving a higher self-resonance frequency. The uppermost layer usually has the lowest sheet resistivity, which also will increase the Q-value.
The reduced substrate capacitance can also be utilized to connect the upper metal layers in parallel, e.g. metal layer three and four from the substrate for the spiral, metal layer two from the substrate for the cross-under, thus increasing the Q-value by another factor of 1.5 - 2.
.. ~ . . , ~, . . . .. .. .. . ..
CA 022~6763 1998-11-30 Trenches can also be used under any metal line or bond pad in order to reduce parasitic capacitance and reduce losses to the substrate.
In addition, no process changes or additional process steps are necessary to achieve this if an advanced Si-IC process is used.
Thus in a method of fabricating an integrated circuit inductor or an integrated circuit comprising an inductor the inductor is produced in or on an electrically semiconducting or semi-isolating substrate and in particular by depositing or coating various layers on a silicon substrate. The inductor can generally comprise a structure of electrical conductor paths exten~ing substantially in one plane or in several, for example substantially parallel planes. Before the conductor paths are produced, in particular before the inductor metal paths are applied to or deposited on the substrate, trenches are etched in the substrate exten~ing from the substrate surface at suitable locations. The locations of the trenches are selected so that the inductor paths will be located above and close to the trenches and generally so that the trenches will intersect the hypothetical electrical current paths inside the material of the substrate, when the inductor is used and there is an electrical current flowing therein and no trenches would have been made in the substrate, this configuration of the trenches then attenuating or hin~ering the currents inside the substrate. The trench~s are filled with an electrically isolating material, in particular a dielectric or semiconducting material, in order that the following process steps when making the conductor paths will experience a substantially flat surface.
The trenches may then advantageously be arranged so that they occupy the largest possible area under the inductor, that is they can be densely spaced. Also, the trenches are preferably arranged in a structure of substantially parallel trenches or a in meshlike structure.
The integrated circuit having an inductor integrated therein thus comprises, in the most general aspect, thin plates of a CA 022~6763 1998-11-30 material thst is a worse or poorer electrical conductor than the substrate, these "plates" being the filled trenches as described above. The plates are arranged in the substrate in some region at the conductor paths, e.g. under the inductor paths, but also configurations having plates between planes of conductor paths and above the inductor paths are conceivable in complex multi-layer structures. The plates may in any case be arranged substantially perpendicularly to the plane or planes of the conductor paths or have any other suitable geometrical configuration in order to make the undesired current paths, when the circuit is used and the desired current flows in the conductor paths, in the substrate from one place at the conductor to another place thereat, long to give these current paths a large resistance, this configuration reducing these currents significantly.
The plates may thus be arranged substantially in parallel to each other, at least in subsets of the total set of all plates.
The plates can then, as viewed in a direction from the conductor paths, for example be arranged in a meshlike structure formed of two subsets of parallel plates. The plates can have a suitable thickness in order to sufficiently cut off the current paths inside the substrate and restricting the current in the substrate to have only long paths inside the substrate. The thickness of the plates may e.g. be substantially equal to the thickness of the conductor paths for typical plate materials.
The width or depth of the plates, as seen from a conductor path, should also be sufficient to restrict the current paths inside the substrate. The plates are then also preferably densely arranged or arranged to have a dense or close spacing, so that the interspace between neighbouring plates is small, this also limiting the current paths and thus the currents inside the substrate material from a place on a conductor to a place thereon located very closely. For example, the spacing could be substantially equal to 2 or a few times, e.g. 5, the thickness of the plates. This may also be worded in the way that the plates or trenches are arranged to occupy the largest possible area as seen from the inductor, the cross-sectional area of each plate however being small as seen in this view.
CA 022~6763 1998-11-30 An integrated circuit can as above, generally, comprise a metal conductor formed on or in an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, the conductor for example being a part of an inductor path.
Also, then, plates or trenches can be arranged in a region or region adjacent the conductor as described above, for reducing losses in the conductor to the substrate. The plates can then as above for example be arranged substantially perpendicularly to the plane of the conductor or the electrical current path therein. The plates may be filled trenches arranged to generally cross the electrical current path in the metallic conductor and preferably to extend in a direction substantially perpendicular to said current path and/or in a longitll~inAl direction of the conductor.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
- Fig. 1 is a highly schematic, rectangular spiral layout as seen from above for an integrated circuit inductor according to state of the art, - Fig. 2a and 2b are schematic cross secti O~A l views of the inductor in fig. l, - Fig. 3 is a schematic cross sectional view of an integrated circuit inductor, - Fig. 4 is a trench pattern to be used on a substrate, - Fig. 5 shows a trench pattern under a metal conductor line.
DESCRIPTION OF A PREFERRED EMBODIMENT
In fig. 1 a state of the art rectangular spiral layout formi ng an inductor is shown. The inductor is in this case formed in a fourth, as counted bottom up, uppermost metal layer 101 by a spiral, electrically conductive path comprising a number of rectangular turns, the number of turns typically being between 5 and 10. A lower metallization layer 103, in this case the third layer, is used for closing the spiral structure by means of a cross-under.
The inductor structure of fig. 1 is also shown in cross section-. ~
CA 022~6763 1998-11-30 al views in figs. 2a and 2b, the sections being taken along lines a - a and b - b in fig. l, respectively. Thus, fig. 2a shows the metal 201 of the fourth metal layer forming the rect-angular turns. Underneath the metal spiral 201, there is an oxide layer 203 applied to a silicon substrate 205. The thick-ness of the metal layer is typically in the range of 1 - 2 ~m and the thickness of the oxide layer is typically 6 ~m and the width of the conductor paths can be about 5 ~m, the distance between neighbouring paths being the same order of magnitude as the width of the paths.
In fig. 2b, which is a cross sectional view along the line b - b in fig. 1, also the third metal layer 207 is shown. The third metal 207 layer constitutes a an electrically conductive cross-under for completing the coil of the inductor. The fourth metal layer 201 and the third metal layer are connected via electri-cally conductive connectors 209. These connectors can be made in a separate step using etching and metallization or, they can be made by first making suitable holes and then filling the holes with the material of the fourth layer.
Fig. 3 shows a cross sectional view of an inductor 305 having an improved isolation, the inductor paths being formed in the top-most, fourth metal layer on a silicon substrate 301. However, before forming the structure on the silicon substrate 301, an etching operation for producing a trench has been performed on the silicon substrate 301 followed by a refilling of the trenches with an isolating material, i.e. a material that has a lower electrical conductivity than that of the substrate. The refilled trenches 303 serve as to increase the effective distance from the metal layer of the inductor to the semi-conducting substrate. The losses in the substrate and the capacitance to the substrate will then decrease. The Q-value and the self-resonance frequency of the inductors will also increase accordingly.
The trenches can be made substantially as in the recited con-ventional methods used in modern IC processes for device isolation. Deep and narrow trenches can thus be produced by dry CA 022~6763 1998-11-30 etching and refilling the etched voids with an isolating material like silicon oxide and undoped poly-silicon or a dielectric material. The surface above the substrate produced in the refilling process will then still be substantially flat. The trench~s can have widths of about 1 - 2 ~m and depths of about 5 - 20 ~m. The width of the substrate material between neigh-bouring trenches may be as small as is practically possible, for instance 2 - 4 ~m. The trenches are arranged in some suitable pattern to cross the overlying conductor paths.
Fig. 4 shows a view of a portion of a substrate 401 from above in which a preferred pattern of trenches 403 has been etched.
The trench pattern is then used under an inductor for reducing the losses to the substrate. The pattern comprises a first set of several straight identical trenches located in parallel to each other and having an equal spacing and also a second set of identical trenches located in parallel to each other and equally spaced, the trenches of the second set being perpendicular to those of the first set. The tren~hes should always be so long and located that they pass beyond the outermost inductor turn into the free material surrolln~ing the inductor. The trench pattern used can however have any meshlike shape, and it is generally desirable to remove as much of the substrate as possible.
Finally, fig. 5 shows how the method as described herein can be used in another application. In this case trenches 501 are etched under a metallization line 503 in order to reduce the parasitic capacitance and reduce losses to the substrate. The trenches may have the same dimensions as discussed above and they are arranged to cross under the electrically conductive path at substantially straight angles. They can be located symmetrically under the conductor path and extend to each side of the path as long as is required or possible, e.g. some 4 - 10 ~m. This trench configuration or preferably the meshlike con-figuration of fig. 3 can be also used for reducing losses of bond pads.
,.. . .
Because of the conducting properties of the substrate, the Q-value of the inductor is reduced. By selectively removing the silicon under the inductor, higher Q-values and higher resonance frequencies are obtAine~. The Q-value can be increased by a factor of two by such a removal. The removal can be in the form of a silicon etching process, giving air gaps of several hundred micrometers, see J.Y.C. Chang, A.A. Abidi, M. Gaitan, "Large Susp~n~e~ Inductor on Silicon and Their Use in a 2 ~m CMOS RF
Amplifier~, IEEE Transactions on Electron Devices Vol. 40, No.
5, p. 246, May 1993, but such removals are not regarded as feasible in large production volumes or compatible with silicon CA 022~6763 1998-11-30 IC processes.
Recent advances in processing methods for fabricating integrated circuits on silicon have allowed inductor layouts having higher inductance per area unit of the integrated circuit and lower losses because of reduction of circuit sizes and multiple metal layers using thick oxide in order to better isolate the inductor from the substrate. There are still considerable losses because of the resistivity of the metal and losses in a corresponding substrate on which the ICs are formed. It is difficult to obtain inductor elements having Q-values higher than 5 - 10 in the 1 -2 GHz frequency range using existing methods for processing silicon wafers.
Inductor elements are usually laid out as square-spirals metal stripes, see for instance N.M. Nguyen, R.G. Meyer, "Si IC-Compatible Inductor and LC Passive Filter", IEEE Journal of Solid-State Circuits Vol. 25, No. 4, p. 1028, August 1990.
Furthermore, ICs usually comprise multiple metal layers and up to five layers is now common in complex Very Large-Scale Integration (VLSI) circuits. At least two metal layers are required for spiral layouts, one for the very spiral and one for closing the structure, i.e. for forming a conductor path from the centre of the spiral to an output terminal at the edge of the inductor. The uppermost ones of the metal layers usually have a lower resistivity because of larger thicknesses and should therefore be u~ed.
By using instead a circular spiral, a 10% reduction of the resistance value can be obt~ine~ for an equal inductance value, resulting in an increased Q-value of the inductor formed of the same magnitude. The circular layout is not very well suited for common software used for Computer Aided Design (CAD), but can be replaced ~y an octagonal configuration without increasing the resistance value of the inductor, see S. Chaki, S. Aono, N.
Andoh, Y. Sasaki, N. Tanino, "Loss Reduction of a Spiral Inductor", Technical Report of IEICE, p. 61, ED93-166, MW93-123, lCD93-181(1994-01).
CA 022~6763 1998-11-30 W O 97/45873 PC~/SE97/009~4 A better way of reducing the resistance is to make an inductor having parallel spiral paths in adjacent layers, e.g. to connect the uppermost metal layers in parallel. The Q-value of the inductor can in this way be increased 1.5 - 2 times, at the expense of a lower resonance frequency because of the decreased isolation thickness. By increasing the number of turns of the spiral, the inductance value is made larger. The capacitance of the inductor spiral to the substrate will however also increase, 1~A~; ng to a lower resonance frequency limiting the useful frequency range of operation of the inductor.
Thus U.S. patent 5,446,311 describes such a structure having an inductor formed in multiple metal layer levels in order to reduce the inductor resistance.
Furthermore, the Japanese patent application JP A 07-106 514 discloses a structure similar to the structure described in U.S.
patent 5,446,311, in which the loss due to electrostatic capacity is reduced and the Q-value is increased by forming an inductor which has two spiral metallic paths formed in different metallization layers and which are interconnected by a third layer.
~eep trenches are applied in modern IC processes for isolation of devices. The advantages of such trenches are reduced parasitic capacitances and reduced device spacing. A deep, 5 -20 ~m, and narrow, 1 - 2 ~m, trench is obtAin~ by means of dry etching and refilling it with oxide and undoped poly-silicon or a dielectric material. After the refilling process, the surface of the substrate will be coated with a layer of refilling material and thus be substantially flat so that e.g. metal layers can be placed over the trenches without any restrictions.
Also, in U.S. patents 5,336,921 and 5,372,967 a method of form-ing an inductor in a vertical trench is described. The inductor described aims at eliminating some of the problems encountered with conventional, horizontal inductors on integrated circuits by means of providing a method of fabricating vertical inductors in the shape of an inductive coil in a trench.
. ~ ~ .. .
CA 022~6763 1998-11-30 Further, U.S. patent 5,095,3S7 discloses an inductive structure having low parasitic capacitances for direct integration in semiconductor integrated circuits.
SU~L~RY OF THE INV~W110N
It is an object of the present invention to provide a method whereby conductors having low losses can be obtAin~ in a simple way.
It is another object of the present invention to obtain a structure for integrated circuits, which makes it possible to achieve inductors having high Q-values.
These and other objects are obt~ine~ by using trenches filled with an isolating material under the spiral inductor layout, which increase the effective distance from the metal to the semiconducting substrate. The losses in the substrate of the integrated device and the capacitance to the substrate will then decrease. The Q-value and the resonance frequency of the inductors will increase accordingly.
In a case where only two metal layers are available, the filled trenches may be enough to achieve acceptable Q-values and resonant frequencies.
In another case, where more metal layers are available, typically four to five layers, the spiral should be laid out in the uppermost of the metal layers, furthermore lowering the parasitic capacitance to the substrate, already lowered by the filled trenches in the substrate, giving a higher self-resonance frequency. The uppermost layer usually has the lowest sheet resistivity, which also will increase the Q-value.
The reduced substrate capacitance can also be utilized to connect the upper metal layers in parallel, e.g. metal layer three and four from the substrate for the spiral, metal layer two from the substrate for the cross-under, thus increasing the Q-value by another factor of 1.5 - 2.
.. ~ . . , ~, . . . .. .. .. . ..
CA 022~6763 1998-11-30 Trenches can also be used under any metal line or bond pad in order to reduce parasitic capacitance and reduce losses to the substrate.
In addition, no process changes or additional process steps are necessary to achieve this if an advanced Si-IC process is used.
Thus in a method of fabricating an integrated circuit inductor or an integrated circuit comprising an inductor the inductor is produced in or on an electrically semiconducting or semi-isolating substrate and in particular by depositing or coating various layers on a silicon substrate. The inductor can generally comprise a structure of electrical conductor paths exten~ing substantially in one plane or in several, for example substantially parallel planes. Before the conductor paths are produced, in particular before the inductor metal paths are applied to or deposited on the substrate, trenches are etched in the substrate exten~ing from the substrate surface at suitable locations. The locations of the trenches are selected so that the inductor paths will be located above and close to the trenches and generally so that the trenches will intersect the hypothetical electrical current paths inside the material of the substrate, when the inductor is used and there is an electrical current flowing therein and no trenches would have been made in the substrate, this configuration of the trenches then attenuating or hin~ering the currents inside the substrate. The trench~s are filled with an electrically isolating material, in particular a dielectric or semiconducting material, in order that the following process steps when making the conductor paths will experience a substantially flat surface.
The trenches may then advantageously be arranged so that they occupy the largest possible area under the inductor, that is they can be densely spaced. Also, the trenches are preferably arranged in a structure of substantially parallel trenches or a in meshlike structure.
The integrated circuit having an inductor integrated therein thus comprises, in the most general aspect, thin plates of a CA 022~6763 1998-11-30 material thst is a worse or poorer electrical conductor than the substrate, these "plates" being the filled trenches as described above. The plates are arranged in the substrate in some region at the conductor paths, e.g. under the inductor paths, but also configurations having plates between planes of conductor paths and above the inductor paths are conceivable in complex multi-layer structures. The plates may in any case be arranged substantially perpendicularly to the plane or planes of the conductor paths or have any other suitable geometrical configuration in order to make the undesired current paths, when the circuit is used and the desired current flows in the conductor paths, in the substrate from one place at the conductor to another place thereat, long to give these current paths a large resistance, this configuration reducing these currents significantly.
The plates may thus be arranged substantially in parallel to each other, at least in subsets of the total set of all plates.
The plates can then, as viewed in a direction from the conductor paths, for example be arranged in a meshlike structure formed of two subsets of parallel plates. The plates can have a suitable thickness in order to sufficiently cut off the current paths inside the substrate and restricting the current in the substrate to have only long paths inside the substrate. The thickness of the plates may e.g. be substantially equal to the thickness of the conductor paths for typical plate materials.
The width or depth of the plates, as seen from a conductor path, should also be sufficient to restrict the current paths inside the substrate. The plates are then also preferably densely arranged or arranged to have a dense or close spacing, so that the interspace between neighbouring plates is small, this also limiting the current paths and thus the currents inside the substrate material from a place on a conductor to a place thereon located very closely. For example, the spacing could be substantially equal to 2 or a few times, e.g. 5, the thickness of the plates. This may also be worded in the way that the plates or trenches are arranged to occupy the largest possible area as seen from the inductor, the cross-sectional area of each plate however being small as seen in this view.
CA 022~6763 1998-11-30 An integrated circuit can as above, generally, comprise a metal conductor formed on or in an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, the conductor for example being a part of an inductor path.
Also, then, plates or trenches can be arranged in a region or region adjacent the conductor as described above, for reducing losses in the conductor to the substrate. The plates can then as above for example be arranged substantially perpendicularly to the plane of the conductor or the electrical current path therein. The plates may be filled trenches arranged to generally cross the electrical current path in the metallic conductor and preferably to extend in a direction substantially perpendicular to said current path and/or in a longitll~inAl direction of the conductor.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in greater detail with reference to the accompanying drawings, in which:
- Fig. 1 is a highly schematic, rectangular spiral layout as seen from above for an integrated circuit inductor according to state of the art, - Fig. 2a and 2b are schematic cross secti O~A l views of the inductor in fig. l, - Fig. 3 is a schematic cross sectional view of an integrated circuit inductor, - Fig. 4 is a trench pattern to be used on a substrate, - Fig. 5 shows a trench pattern under a metal conductor line.
DESCRIPTION OF A PREFERRED EMBODIMENT
In fig. 1 a state of the art rectangular spiral layout formi ng an inductor is shown. The inductor is in this case formed in a fourth, as counted bottom up, uppermost metal layer 101 by a spiral, electrically conductive path comprising a number of rectangular turns, the number of turns typically being between 5 and 10. A lower metallization layer 103, in this case the third layer, is used for closing the spiral structure by means of a cross-under.
The inductor structure of fig. 1 is also shown in cross section-. ~
CA 022~6763 1998-11-30 al views in figs. 2a and 2b, the sections being taken along lines a - a and b - b in fig. l, respectively. Thus, fig. 2a shows the metal 201 of the fourth metal layer forming the rect-angular turns. Underneath the metal spiral 201, there is an oxide layer 203 applied to a silicon substrate 205. The thick-ness of the metal layer is typically in the range of 1 - 2 ~m and the thickness of the oxide layer is typically 6 ~m and the width of the conductor paths can be about 5 ~m, the distance between neighbouring paths being the same order of magnitude as the width of the paths.
In fig. 2b, which is a cross sectional view along the line b - b in fig. 1, also the third metal layer 207 is shown. The third metal 207 layer constitutes a an electrically conductive cross-under for completing the coil of the inductor. The fourth metal layer 201 and the third metal layer are connected via electri-cally conductive connectors 209. These connectors can be made in a separate step using etching and metallization or, they can be made by first making suitable holes and then filling the holes with the material of the fourth layer.
Fig. 3 shows a cross sectional view of an inductor 305 having an improved isolation, the inductor paths being formed in the top-most, fourth metal layer on a silicon substrate 301. However, before forming the structure on the silicon substrate 301, an etching operation for producing a trench has been performed on the silicon substrate 301 followed by a refilling of the trenches with an isolating material, i.e. a material that has a lower electrical conductivity than that of the substrate. The refilled trenches 303 serve as to increase the effective distance from the metal layer of the inductor to the semi-conducting substrate. The losses in the substrate and the capacitance to the substrate will then decrease. The Q-value and the self-resonance frequency of the inductors will also increase accordingly.
The trenches can be made substantially as in the recited con-ventional methods used in modern IC processes for device isolation. Deep and narrow trenches can thus be produced by dry CA 022~6763 1998-11-30 etching and refilling the etched voids with an isolating material like silicon oxide and undoped poly-silicon or a dielectric material. The surface above the substrate produced in the refilling process will then still be substantially flat. The trench~s can have widths of about 1 - 2 ~m and depths of about 5 - 20 ~m. The width of the substrate material between neigh-bouring trenches may be as small as is practically possible, for instance 2 - 4 ~m. The trenches are arranged in some suitable pattern to cross the overlying conductor paths.
Fig. 4 shows a view of a portion of a substrate 401 from above in which a preferred pattern of trenches 403 has been etched.
The trench pattern is then used under an inductor for reducing the losses to the substrate. The pattern comprises a first set of several straight identical trenches located in parallel to each other and having an equal spacing and also a second set of identical trenches located in parallel to each other and equally spaced, the trenches of the second set being perpendicular to those of the first set. The tren~hes should always be so long and located that they pass beyond the outermost inductor turn into the free material surrolln~ing the inductor. The trench pattern used can however have any meshlike shape, and it is generally desirable to remove as much of the substrate as possible.
Finally, fig. 5 shows how the method as described herein can be used in another application. In this case trenches 501 are etched under a metallization line 503 in order to reduce the parasitic capacitance and reduce losses to the substrate. The trenches may have the same dimensions as discussed above and they are arranged to cross under the electrically conductive path at substantially straight angles. They can be located symmetrically under the conductor path and extend to each side of the path as long as is required or possible, e.g. some 4 - 10 ~m. This trench configuration or preferably the meshlike con-figuration of fig. 3 can be also used for reducing losses of bond pads.
,.. . .
Claims (14)
1. An integrated circuit comprising a metal conductor formed on or in an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, characterized by thin plates of a material being a worse or poorer electrical conductor than the substrate, which are arranged in the substrate beneath the active layer(s) thereof in a region at the conductor, the plates in particular being trench s in the substrate located under the conductor and refilled with an electrically isolating material, in particular a dielectric or semiconducting material, the plates being arranged substantially perpendicularly to the plane of the conductor or the electrical current path therein, in particular arranged to generally cross the electrical current path in the conductor and preferably to extend in a direction substantially perpendicular to said current path and/or to a longitudinal direction of the conductor.
2. A circuit according to claim 1, characterized in that the plates are arranged substantially in parallel to each other.
3. A circuit according to any of claims 1 - 2, characterized in that the plates are densely arranged, so that the interspace between neighbouring plates is small, preferably substantially equal to 2 or a few times the thickness of the plates, in particular the trenches being arranged to occupy the largest possible area under the conductor.
4. A circuit according to any of claims 1 - 3, characterized in that the plates are arranged in a meshlike structure.
5. A method of making a conductor in an integrated circuit having low losses to a substrate, comprising - that before applying the metallic conductor on the substrate, trenches are etched in the substrate beneath the active layer(s) thereof, and - that the trenches then are refilled with an electrically isolating material, in particular a dielectric or semiconducting material, or a material being a poorer conductor than the substrate, characterised in that in etching the trenches the longitudinal directions of the trenches are arranged to cross the electrical current path in the metallic conductor, in particular to extend in a direction substantially perpendicular to said path and/or to a longitudinal direction of the conductor.
6. An inductor in an integrated circuit formed on or in an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, and comprising a structure of conductor paths extending in one plane or a plurality of sub stantially parallel planes, characterized by thin plates of a material being a worse or poorer electrical conductor than the substrate, which are arranged in the substrate beneath the active layer(s) thereof in a region at the conductor paths, the plates in particular being trenches in the substrate located under the inductor paths and refilled with an electrically isolating material, in particular a dielectric or semiconducting material.
7. An inductor according to claim 6, characterized in that the plates are arranged substantially perpendicularly to the plane or planes of the conductor paths.
8. An inductor according to any of claims 6 or 7, characterized in that the plates are arranged substantially in parallel to each other.
9. An inductor according to any of claims 6 - 8, characterized in that the width of the plates is substantially equal to the width of the conductor paths.
10. An inductor according to any of claims 6 - 9, characterized in that the plates are densely arranged, so that the interspace between neighbouring trenches is small, preferably substantially equal to 2 or a few times the width of the trenches.
11. An inductor according to any of claims 6 - 10, characterized in that the plates are arranged in a meshlike structure.
12. A method of fabricating an integrated circuit inductor in or on an electrically semiconducting or semi-isolating substrate, in particular on a silicon substrate, the inductor having an increased Q-value and comprising a structure of electrical conductor paths extending in one plane or several substantially parallel planes, characterized in - that before making the conductor paths, in particular before applying the inductor paths on the substrate, trenches are etched in the substrate beneath the active layer(s) thereof at such places, that the inductor paths will be located above the trenches, and - that the trenches are refilled with an electrically isolating material, in particular a dielectric or semiconducting material, or a material being a poorer electrical conductor than the substrate.
13. A method according to claim 12, characterized in that the trenches are arranged to occupy the largest possible area under the inductor.
14. A method according to any of claims 12 or 13, characterized in that the trenches are arranged in a structure of substantially parallel trenches or a meshlike structure.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9602191A SE510443C2 (en) | 1996-05-31 | 1996-05-31 | Inductors for integrated circuits |
| SE9602191-0 | 1996-05-31 | ||
| PCT/SE1997/000954 WO1997045873A1 (en) | 1996-05-31 | 1997-05-30 | Conductors for integrated circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2256763A1 true CA2256763A1 (en) | 1997-12-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002256763A Abandoned CA2256763A1 (en) | 1996-05-31 | 1997-05-30 | Conductors for integrated circuits |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0902974A1 (en) |
| JP (1) | JP2000511350A (en) |
| KR (1) | KR100298480B1 (en) |
| CN (1) | CN1220778A (en) |
| AU (1) | AU3113097A (en) |
| CA (1) | CA2256763A1 (en) |
| SE (1) | SE510443C2 (en) |
| WO (1) | WO1997045873A1 (en) |
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| JP2002509649A (en) | 1997-07-11 | 2002-03-26 | テレフオンアクチーボラゲツト エル エム エリクソン | Process for manufacturing IC components used at high frequencies |
| KR19990055422A (en) * | 1997-12-27 | 1999-07-15 | 정선종 | Inductor device on silicon substrate and manufacturing method thereof |
| JP3942264B2 (en) * | 1998-03-11 | 2007-07-11 | 富士通株式会社 | Inductance element formed on a semiconductor substrate |
| DE19810825A1 (en) * | 1998-03-12 | 1999-09-16 | Siemens Ag | Electronic integrated circuit |
| EP0966040A1 (en) * | 1998-06-19 | 1999-12-22 | International Business Machines Corporation | Passive component above isolation trenches |
| KR20000011585A (en) * | 1998-07-28 | 2000-02-25 | 윤덕용 | Semiconductor device and method for manufacturing the same |
| US6278186B1 (en) * | 1998-08-26 | 2001-08-21 | Intersil Corporation | Parasitic current barriers |
| DE19910983A1 (en) * | 1999-03-12 | 2000-09-21 | Bosch Gmbh Robert | Device and method for determining the lateral undercut of a structured surface layer |
| WO2001004953A1 (en) * | 1999-07-08 | 2001-01-18 | Korea Advanced Institute Of Science And Technology | Method for manufacturing a semiconductor device having a metal layer floating over a substrate |
| DE19944306B4 (en) * | 1999-09-15 | 2005-05-19 | Infineon Technologies Ag | Integrated semiconductor integrated coil circuit and method of making the same |
| SG98398A1 (en) | 2000-05-25 | 2003-09-19 | Inst Of Microelectronics | Integrated circuit inductor |
| FR2810451A1 (en) * | 2000-06-20 | 2001-12-21 | Koninkl Philips Electronics Nv | INTEGRATED CIRCUIT INCLUDING A HIGH QUALITY FACTOR INDUCTIVE ELEMENT AND HAVING HIGH COMPACITY |
| KR20020014225A (en) * | 2000-08-17 | 2002-02-25 | 박종섭 | Integrated device having insulator layer in trench overlapped with fine inductor and method for foming the same |
| DE10041084A1 (en) | 2000-08-22 | 2002-03-14 | Infineon Technologies Ag | Method for forming a dielectric region in a semiconductor substrate |
| DE10041691A1 (en) * | 2000-08-24 | 2002-03-14 | Infineon Technologies Ag | A semiconductor device |
| EP1213762A1 (en) * | 2000-12-05 | 2002-06-12 | Koninklijke Philips Electronics N.V. | Electrical device isolation structure |
| DE10163460B4 (en) * | 2001-12-21 | 2010-05-27 | Austriamicrosystems Ag | Silicon substrate with an insulating layer and arrangement with a silicon substrate with an insulating layer |
| EP1454354B1 (en) | 2001-12-13 | 2015-04-15 | ams AG | Silicon substrate having an insulating layer, silicon substrate, and assembly of a silicon substrate with an insulating layer |
| DE102004022139B4 (en) * | 2004-05-05 | 2007-10-18 | Atmel Germany Gmbh | A method for producing a spiral inductance on a substrate and a device produced by such a method |
| JP3927565B2 (en) * | 2004-06-25 | 2007-06-13 | インターナショナル・ビジネス・マシーンズ・コーポレーション | On-chip inductor with magnetic core |
| CN101149761B (en) * | 2006-09-20 | 2012-02-08 | 爱斯泰克（上海）高频通讯技术有限公司 | Double pi asymmetrical model parameter extraction method for silicon base spiral inductor equivalent circuit |
| CN102208405B (en) * | 2010-08-24 | 2015-11-25 | 华东师范大学 | planar spiral inductor |
| CN102456612A (en) * | 2010-10-27 | 2012-05-16 | 上海华虹Nec电子有限公司 | Manufacturing method and structure of semiconductor integrated inductor |
| JP5699905B2 (en) * | 2011-10-28 | 2015-04-15 | 株式会社デンソー | Semiconductor device |
| CN114823638A (en) * | 2022-04-27 | 2022-07-29 | 电子科技大学 | Integrated inductance structure with low parasitic capacitance |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0377360A (en) * | 1989-08-18 | 1991-04-02 | Mitsubishi Electric Corp | Semiconductor device |
| US5336921A (en) * | 1992-01-27 | 1994-08-09 | Motorola, Inc. | Vertical trench inductor |
| WO1994017558A1 (en) * | 1993-01-29 | 1994-08-04 | The Regents Of The University Of California | Monolithic passive component |
| WO1996002070A2 (en) * | 1994-07-12 | 1996-01-25 | National Semiconductor Corporation | Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit |
| US5446311A (en) * | 1994-09-16 | 1995-08-29 | International Business Machines Corporation | High-Q inductors in silicon technology without expensive metalization |
-
1996
- 1996-05-31 SE SE9602191A patent/SE510443C2/en not_active IP Right Cessation
-
1997
- 1997-05-30 EP EP97926345A patent/EP0902974A1/en not_active Withdrawn
- 1997-05-30 JP JP09542247A patent/JP2000511350A/en not_active Abandoned
- 1997-05-30 CA CA002256763A patent/CA2256763A1/en not_active Abandoned
- 1997-05-30 WO PCT/SE1997/000954 patent/WO1997045873A1/en not_active Application Discontinuation
- 1997-05-30 AU AU31130/97A patent/AU3113097A/en not_active Abandoned
- 1997-05-30 KR KR1019980708627A patent/KR100298480B1/en not_active IP Right Cessation
- 1997-05-30 CN CN97195081A patent/CN1220778A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| SE510443C2 (en) | 1999-05-25 |
| KR100298480B1 (en) | 2001-08-07 |
| KR20000010660A (en) | 2000-02-25 |
| WO1997045873A1 (en) | 1997-12-04 |
| AU3113097A (en) | 1998-01-05 |
| SE9602191L (en) | 1997-12-01 |
| JP2000511350A (en) | 2000-08-29 |
| CN1220778A (en) | 1999-06-23 |
| SE9602191D0 (en) | 1996-05-31 |
| EP0902974A1 (en) | 1999-03-24 |
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