CA2252182C - Device and method for carrying out reed-solomon encoding - Google Patents
Device and method for carrying out reed-solomon encoding Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
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Abstract
In a Reed-Solomon encoding device which produces, for example, a Reed-Solomon code of 4 bytes for a data signal of 16 bytes, the Reed-Solomon encoding device includes a signal separating circuit (100) which separates the input signal into two signals A and B which are successively outputted in a time division fashion. In synchronism with the output of these signals, an octal counter (1) is counted up. In response to the two separated signals outputted from the signal separating circuit (100), coefficients of respective terms of a remainder obtained by dividing the data signal by a generator polynomial are classified into even-number order ones and odd-number order ones to be calculated in parallel.
The even-number order coefficients and the odd-number order coefficients are supplied to selectors (2) and (3) as signals C and D, respectively. The selectors (2) and (3) output the signals from the signal separating circuit (100) when the counter (1) has a count value between 0 and 5 and the signals C and D when the count value is 6 or 7.
The even-number order coefficients and the odd-number order coefficients are supplied to selectors (2) and (3) as signals C and D, respectively. The selectors (2) and (3) output the signals from the signal separating circuit (100) when the counter (1) has a count value between 0 and 5 and the signals C and D when the count value is 6 or 7.
Description
98-10-29:10:38 ;~ BELL ;81~350302~0 ~ 3f 47 DEVICE AND ~ETHOD FOR CARRYING OUT R~ED-SOLO~ON ENCODING
P~c~o--n~ of the In~ention:
~ hi~ in~ention relates to a Reed-Solomon encoding de~ice and method and, in particular, to such device and method adapted to error correction of a deQired numher of blocks not fewe~ than two.
In data communication, a re~n~n~y ~ignal i~
generally appPn~ to data ~information signal) to be trangm itted 50 that a data error occurring in a tr~r~ sion path can be detected and corrected at a receiving end. As the rP~ln~ncy signal to be appended to the information sign~l, a Reed-Solomon cod~ iy widely known.
~ xamples of a de~ice ~or car~ying out Reed-Solomon encoding are disclosed in J~nese U~ex~ined Patent tion (JP-A) Nos. 59-226951 (226951/1984), 60-73752 (73752/1985), and 9-36753 (36753/1997). ~o~e~er, each of these publication~ disclo~es no more than a Reed-Solomon encoding device adapted to error correction of a single block or two hlock~ ~t most.
In contr~t, as a Reed-Solomon encoding circuit adapted to error correction of a desired nu~ber of block~ not fewer than two, a circuit u~ing a polynomlal division circuit i~ diqclosed in ~Essence of Error Correction Encoding Technique~ upervised by Hideki Imai, Japan Indu.qtrial Technology Center, 1986), page 30 (hereinafter called a conventional example 1). In addition, a circuit for successi~ely processing input signals in a systolic array OCT 28 1998 20:39 81~030250 P~GE.03 . , 98-10-29:10:3~ BELL .a1 3so302~0 ~ 4~ 47 .
structure i~ disclosed in "A Con~truction Method for Reed-Solomon Codec Suitable for V~SI Design" (Proceedings o~
Institute of Electronics, Information, Communication Engineers of Japan, Vol. J71-A, pp. 751-759) ~hereinafter called a conventional example 2).
Fig. l is a block diagram sho~ing a ~tructure of the Reed-Solomon ~nco~; ng circuit in the conventional example l.
The Reed-Solomon enCo~; ng circuit of the conventional ~Y~ .~le 1 compri~es a di~ision circuit ~hich is composed of exclu~ive-OR circuits 531 through 53n, Galois ~ield multiplication circuits 541 through 5~n, and D flop-flop~ 55l through 55n and which calculate6 a ~ormula obtained by di~iding a polyno.i~1 correspondi~ to an input signal by a generator polynomial. Note that multipliers of the Galois field multiplication circuits 541 through 54n are det~ i n~
*rom coefficients of the generator polynomial F(x) represented by Equation tl).
F(x) = (x ~ a)(x I a2)(x + a3) . . (x + am) (l) In the abo~e-mentioned R~ed-Solomon encoding circuit, a selector 52 i8 responsive to a count value of a counter 51 and selects either the input in~ormatlon signal or an output signal of the D flo~-flop 55n as a selector output. ~us, the selector ~2 ~uccessi~ely output~ the in~ormation signal and a Reed-Solomon code as a re~ ncy code. Herein, by controlling which one is to be outputted ~rom the -~elector 52 with reference to the count value of the counter 51, it is possible to produce the Reed-Solomon code permitting error correction of a de3ired n ~~r of blocks.
OCT 28 1998 20: 39 81~0~ 0 PRGE. 04 9~-lC-29;10:38 ;~ X~ ELL ;~1~350302~0 $ S~ 47 Fig. 2 is a block diagram showing a structure of the Reed-Solomon encoding circuit in the con~entional example 2.
As illustrated in the figure, the Reed-Solo~on encoding circuit in the con~entional example 2 comprise~ a divi~ion circuit formed by ronn~ting in cascade a plurality of proce~sing elements PE illustrated in Fig. 3, instead of the division circuit composed of the exclusive-OR circuits ~1 through 53n, the Galois ~ield multiplication circuits 541 through 54n, and the D flop-flops 551 through 55n illustrated in ~ig. 1.
Ho~e~er, in each of the circuits in the conven~; ~n~l examples 1 and 2, the information signal is supplied one byte by one byte. E~ery time ~hen the information ~i~nal i.c ~upplied, orders or degrees are lo~ered by one at a time.
After completion o~ input of the information -~ignal, re~n~nCy 9ignalg corre8pO~Ai ng to respective te~m~ of a gr poly~omi~l as a result of calculation are successi~ely outputted. ~herefore, it takes a long time before completion o~ the Reed-Solomon encoding.
S~mm~ry o~ ~h~ Tnven~;on:
It is therefore an object of thi~ in~ention to provide a Reed-Solomon encoding device and method adapted to error correction of a desired number of blocks not fewer than two and capable of carrying out hig~-speed encoding by parallel processing.
According to a ~irst aspect of this invention, there i~ provided a Reed-Solomon encoding device which is supplied ~ith an input signal cont~;n;ng N data signal blocks in each single frame ~or carrying out a division of di~iding by a -- - -- ' ;CE;;;
OCT 28 19913 20: 40 51~50302~ P~IGE . 05 , _ . .
98-lo-29;lo:3a ~ BE-L ;81~350302C0 ~ 6i 47 generator polynomial a poly~m;~ corresp~n~ing to the input data ~ignal to produce ~ redun~dancy signal blocks corre~psnA;n~ to a r~ -;n~ar obtained by the di~ision and which compri~es:
~ ignal output means for outputting the N data signal block~ by J blocks at a time in a time division fashion ~uccessi~rely from those corresp~n~ing to h;~h~r order~ in the corre~po~d;ng polyns~;al;
adder m~ans, J in number, for calculating, with respect to J data ~ignal blocks outputted from the signal output mRans and J calculated block~ obt~ine~ by a predetermined op~ration ba~ed upon J pre~ ng data signal blocks outputted from the ~i~nal output mean~ at a p~eceA;ng timing, a ~um of a pair of the data signal and the calculated blocXs correspsn~j n~ in their orders to each other;
operating means, J in number, respon~ive to J sum blocks calculated by the J adder mean~, respecti~ely, for carrying out the p~edetermined operation to produce the J
calculated blocks which correspond to orders lower by J
le~els than those of the J ~um block~ calculated by the J
adder means, respectively, and which are supplied to the J
adder meanY, respecti~ely; and sQlective output m~an~, J in number, for outputting (N . J) times J data signal blocks ~upplied from the ~ignal output mean~ and sub-Qequently outputting (K . J) time~ J
calculated blocks produced by the J operating mean~;
N, K, and J being natural number~ where J i~ a mea~ure (or a di~isor) o~ both of N and X.
__ . , ~,, . __ OCT 25 199~ 20: 41 al~ 302~ P~GE. 05 98-10-29;10:3a ~ ; 8ELL :81~350302~0 ~ 7~ 47 With the above-mentioned Reed-Solomon encoding de~ice, it is possible to process the data qignal by ~ block_ at a time in parallel and to pro~uce X re~lln~ncy signal blocks ~uccessi~ely by J blocks at a time. It i~ there~ore pos~ible to perfonm high-speed proce~sing a~ fast a~ J tim~s as rom~red with the cohv6.~tional Reed-Solomon encoding device.
Fur~h~r~ore, as ~ar as N, X, and J are natural nll~h~rs ~here J i~ a measure of both of N and ~, the Reed-Solomon ~nco~;~g de~rice is capable of pro~ ; ng a Reed-Solomon code permitting error correction even if ~ is equal to 4 or more, i.e., permatting multiple error correction more than triple erro~
correction.
Th~ Reed-Solomon encoding device according to the fir~t aspect ~ay further co~prise:
~ N I ~C) . J)-ary counting means 4Or countin~ up at an inter~ral equal to that of~ output ti mingQ of the data signal block_ fro~ the 3ig~al output means. In this event:
the J -Qelective output means ~uccessively output J
data signal blo~ks supplied fro~ the ~ignal output means when the count value of the counting means is bet~een O and (N .
J - 1) and successi~rely output J calculated blockQ produced by the J operating means when the count value of the counting meanQ is between (N J) and ~(N + ~) ' J - 1) According to a second a~pect of this invention, there i~ provided a ~eed-Solomon enc:oding device which i9 supplied with an input signal cont~ining N data signal block~Q in each single ~rame for carrying out a divi~ion o~ dividing by a generator polyno~ial a polynomi~l corresponding to the input data signal to produce ~ re~n~nCy signal blocks OCT 28 1998 20:~1 81~ 2~ PRGE.07 9~-10-29,10:3~ BE~L :81~350302~ ~ 8f 41 eorrespon~in~ to a remainder obt~ by the di~ision and which compri-~es:
~ lYil;~y block appending means for appen~;ng I
a~Y; 1 i ~ry blocks to the N data signal block~;
signal output means for outputting the (N + I) dat~
signal bloeks, ineluding the auxiliary blocks appended by the ;l;~y bloek appen~g ~eans, by ~ bloeks at a time in a tim~ di~ision fashion successi~ely ~rom those eorrespo~ g to higher orders in the eor~esporl~; n~ polyT~
adder means, J in ~ or calculating, with respect to J data signal blocks outputted from the signal output means and J ealeulated block~ obt~ine~ by a predet~ ~ined operation based upon J preeeding data 8ignal bloeks outputted from the signal output means at a pxeceding t;ming, a sum of a pa~r of the data signal and the ealeulated blocks eorrespQ~; ng in their orders to each other;
operating means, J in number, responsive to J sum bloeks ealeulated by the J adder means, respectively, for c~-r~ing out the predete-mined operation to produee the J
caleulated ~loeks whieh eorrespond to orders lower by J
le~els than tho~e of the J sum bloeks ealculated by the J
adder means, respectiv~ly, and which are supplied to the J
adder means, respeeti~ely; and seleetive output means, J in nl~mher, for outputting ~tN + I) ~ J) time~ J data 9ignal blocks supplied from the signal output ~eans and subsequently outputting (x . J) times J calculated bloc~s produced by the J operating m~an~;
N, K, J, and I being natural numbers where J i~ a measure of both o~ (N + 1) and ~.
OCT 28 1998 20:42 61~50~250 P~GE.09 98-la-29,lc 3a ~ ELL ,~1~350302C0 ~ 9f 47 ~ ccording to the abo~e-mentioned Reed-Solomon encodlng device, the I auxiliary bloc~s are appended to the N data signal bloc~s. The re~l~nA~n~y signal blocks are produced ~or the (N ~ I) data signal block~ in total, including the ~ ry blocks appended thereto. Thus, the de~ice is applicable even if N can not be divided by J without a rem~n~qr. It i~ pos~ible to proce~s the (N + I) data signal blocks by J blocks at a time in paral~el and to pro~uce ~
r~ n~n~.~.y signal blocks ~ucces~ively by J blocks at a ~ime.
It i~ there~ore poc~ible to perform high-speed proces~ing as fa~t a~ J times as ro~p~red with the conventional Reed-Solomon encoding device. Fu~hermore, as far as N, X, and J
are natural n~lmher~ where J i~ a measure of both of (N + I) and X and I is smaller than J, the Reed-Solomon t~n~ot~i ng device i~ ~p~hle Of pro~ i ng a Reed-Solomon code permitting srror correction even if K is et~ual to 4 or more, i.e., permitting multiple error correction more than triple error correction.
The Reed-Solomon enc.~o~i; ng device according to the ~econd aspect may further comprise:
(tN + K) . J)-ary counting mean~ for counting up at an interval equal to t~at of output ti~ings o~ the data signal blocks from the signal output mean~. In this e~ent:
the J 3elective output mean~ ~ucce.~si~ely output J
data ~ignal block3 supplied from the ~ignal output means when the count value of the counting means i~ between O and (~N +
I) . J - 1) and s~cces~ively output J calculated block~
produced by the J operating means when the count value o~ the counting mean~ i.c between ((N + I) J) and ((N + ~ + K) CA 02252182 1998-10-29 _ .
OCT 28 l99e 20: ~13 81~030~ P~GE . 03 .
98-10-29:10:38 ;~ Y.~f ~ELL ,81~,350302CO ~; 10~ 47 J - 1).
In the Reed-Solomon encoding de~ice according to the second aspect:
each of the I auxiliary blocks may comprise a bit string of "O"
Ad~antageou~ly, the signal output mean~ at fir~t output~ the I a~lY~ y blocks as higher-order ones than the N data ~ignal blocks.
Thus, the highe~t-order term in the polynomial has a coe~ficient equal to O and is therefore excluded ~rom e ror correction by the Reed-Solomon code produced.
In eac~ of the Reed-Solomon encoding device according to the fir-~t and ~he second aspect3, for example;
each of the ~ operating m8an3 ~xecutes the predetermined operation upon coe~icients o~ such terms in the corre3po~di~g polyn~ that re~ind~s equal to one another are produced when their orders are ~i~ided by Ji and each o~ the J adder m~an8 calculates, with respect to the calculated bloc~s as a result of the operation by t~e J
operating means and the J data signal blocks outputted fro~
the signal output means, a sum of a pair of the calculated and the data signal block~ equal in their orders in the correspon~ing polynomi~l to each other In thi~ event, each o~ the J operating meanc may c~mprise recei~ing mean~ ~or r~cei~ing another calculated block which corresponds to the order of the calculated block calculated by this operating mQans and which is produced a~ a result of the operation b~ any operating means other than this operating means, and operating means for carrying out CA 02252182 1998-10-29 __.
OCT 28 1998 20:43 813~j03~2jl~ Pi~GE. 10 98-l0-29;lC:3a ;~ qc~ ELL ,~l~350302~0 ,~ llJ 47 the predet~rm;~ed operation by the use of the above-mentioned another calculated block recei~ed by the receiving means.
In each of the Reed-Solo~on encoding de~ice according to the fir~t and the s~cond a~pect~, for example:
the ~ignal output means produces a bit -~tring of "O"
when the J selecti~e output m~ans output the J sum blocks as a result of the addition by the J adder means.
ACcording to a third aspect of this in~ention, there iQ pro~ided a ~eed-Solomon encodang method which is supplied with an input signal cont~; n; n~ N data signal blocks in each single frame for carrying out a di~ision of dividing by a generator polynomial a polynomial corresponding to the input data sàgnal to produce ~ re~n~ncy ~ignal block~
corre~p~n~;n~ to a r~i~d~r ob~;n~ by the division, the method comprising:
a signal output step o~ outputting the N data signal block~ by ~ block~ at a time in a time division ~ashion successi~ely ~rom tho-~e corresponding to higher orders in the correspo~; ng polynomial;
an adding step of calculating, with ~e~pect to J data signal blockQ outputted in the signal output ~tep and J
calculated ~locks obt~ined by a p~edeterm;ns~ operation ba~ed upon J prece~in~ data signal blocks outputted in the s~gnal output step at a preceding ti~ing, a su~ of a pair of the data signal and the calc~lated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step o~ carrying out, in re~ponse to the J ~um blocks calculated in the ~ddin~ step, the predet~rmined operation to produce the J calculated block~ which correspond OCT 28 1998 20:44 81~0~0250 P~GE. 11 98-10-29,10:38 ;~ BELL ~ ,350302~0 ~ J 4 to orders lower by J levels than those of the sum blocks calculated in t~e ~Ai ng step and which are re~pecti~ely added in the ~d~n~ step at ~ next t;ming;
N, X, and J ~eing natural number~ w~ere J i~ a measure of both of N and ~.
According to a fourth aspect of this invention, there i-~ provided a Reed-Solomon encoding method ~hich is 8upplied with an input signal cont~inin~ N data signal ~locks in eac~
single fr~ for carrying out a di~ision of dividing by a generator poly~-iAl a polynomial correspo~ g to the input data ~ignal to produce K re~n~ncy signal blocks correspo~ding to a ~. ~;n~f~r obt~;ne~ by the di~ision, the method comprising:
an auxiliary signal appending step of appending I
al-Y;li~ry blocks to the data s~gnal N blocXs;
a si~al output step Of outputting the (N + I) data signal blocks, including the at~Yi 1; ~ty blocks appended in the ~llY;liAt~ signal app~ndjn~ step, by J ~locks at a time in a time division fashion succes3ively $rom those corresponding to higher order~ in the corresponding polynomial;
an ~ ing step of calculating, with re~pect to J data signal blocks outputted in the s;~n~l output step and J
calculated ~locks obtained by a predeterm;ne~ operation based upon J preceding data signal blocks outputted in the sif~nal output step at a pre~s~i~g timing, a sum of a pair of the data signal and the calculated bloc~s corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in respon~e to the J sum blocks calculated in the :3~rling step, the predeterm;ned CA 02252l82 l998-l0-29 OCT 28 1999 20:4~ 81~ 2~ PRGE.12 9~-1û-2~;~0:38 ~ 6~ ELL :81~350302~a ~; 13~ 47 .
operation to produce the J calculated block~ which correspond to orders lower by J le~els than those of the 5um block~
calcula~ed in the ~i ng s~ep and which are respectively added in the ~;n~ step at a next tim;~g;
N, ~, ~, and I being natural numbers where J is a measure of both of (N ~ I) and K.
~ r; ef Des~ ;on o~ ~he Drawi~:
Fig. 1 is a block diagram sho~ing a structure of a first conventional Reed-Solomon encoding circuit;
Fig. 2 is a block diagram showing a structure of a second conventional Reed-Solomon encoding circuit;
Fig. 3 is a ~iew showing a ~tructure of a P~ in Fig. 2;
Fig. ~ is a view showing a format of data en~o~ by Reed-Solomon encoding according to a first embodi~ent of this in~e~tion;
Fig. 5 is a bloc~ diagram showing a structure of a Reed-Solomon encoding de~ice according to the first embodiment of this inYention;
Fig. 6 i~ a view showing a format o~ data encoded by Reed-Solomon encoding according to a ~econd z ho~iment of thi~ in~ention; and Fig. 7 is a block diagram showing a structure of a Reed-Solomon ~co~;n~ de~ice according to the second embod~ment of this in~ention ~ tail~d DescriP~io~ of t~e Tnv~ntion Now, description ~ill be made abo~t em~odimentq of this in~ention with reference to the dra~ing.
OCT 25 l99G 20:45 61~0~25~ P~GE.13 . ._ 98-10-29;1~:3~ t~ BELL ;~1~,350302~0 ~i 14~ 47 [lst Embodiment~
In this e~bodi~ent, a (16, 12) Reed-Solomon encoding device which perform~ parallel p~oce~ing o~ two bytes and which can carry out error correction of two bytec will be de~cribed for brevity o~ description. A data format after Reed-Solomon encoding in this e~bodiment is illustrated in ~ig. 4.
At first, de~cription will be made about the principle of the Reed-Solomon en~o~;~g in this embodiment.
The Reed-Solomon encoding i executed by the use o~ a set, called a Ga~ois field, ha~ing a predetsrmined rule. The Galois field i~ clo~ed ~ithin tho Galois ~ield for multiplication and addition and thus for~s a complete set.
Therefore, data ha~ing a predet~rmined bit length ~one data block) can be replaced by elements of the Galois field. ~et the bit length be represented by N. Then, the Galois f ield i~ ~ormed by the elements of 2N or less in nu~er.
In this embodiment, a singlo block of a signal compri~es one byte, i.e., eight bits aa will later be de~cribed. The Galois field then comprises the elements of 2~ = 256 in number. The~e elements of the Galois field are p ssed as ~0, 1, a ~ a2, a3, a254) correspond to a ~ignal formed by a combination of vector exp~ession of coefficients of a seventh-order polyno i~l a~ a r~m~;nd~r obtained by di~iding x tn = O, 1, ..., 255) by a primiti~e polynom al G~x) hereunder on a binary operation and zero Qlements (O, O, O, O, O, O, O, O).
G~x) = x8 + x4 ~ x3 + x2 + 1 (2) OCT 2E1 1998 20:46 81.5~0~ Pf1GE. 14 sa-10-25;1~:38 ~ EL~ ;81~35C302~0 If n = O for example, the r~; nd~r ob~; n~A by dividing xn by the primitive polynomial G(x) is equal to 1.
~herefore, the elements of the Galo~ field correspond to (O, O, O, O, O, O, O, l). If n = l, the r~m~inde~ obtained by dividing xn by the psimitive polynomial G(x) i8 equal to x.
Then, the elemenks of the Galoi-q ~ield correspond to (O, O, O, O, O, O, l, O). If aP correspond~ to tb7, b6, b5, b4, b3, b2, bl, bo)~ the relation~hip in Equation (3) hold~ (~here each of b7 to bo iY equal to O or l).
aP = ~ bi-ai ~3) i=O
At this time, each addition i~ executed as a ~inary ~ummation per bit. In this embodiment, the addition i9 carried out ~y ~he use of an exclusive OR operation per bit as will later be descri~ed. There~ore, the result~ of addition and subtraction are equi~alent. On the other hand, the relationship in Equation (4) holds for multiplication of the elements of the Galois field.
aP x aq - a (P~q) ~4) From Equations (3) and (4), a product of t~o given vectors i5 calculated.
In this e~bodi~ent, two bytes of the signal are proce~ed in parallel. Then, con~ideration will be made about the ca~e wh~re division o~ quadratic coefficients i~
proce~ed at a ti~e. To produce the Reed-Solomon code permitting two-byte error correction, a generator polynomial F(x) iq a fourth-order polynomial given by Equation (5).
F(x) = ~x + a)(x ~ a2)(x ~ ~3)(x + ~) (5) .. . _ . _ _ .. , . . ... _ _ .
OCT 28 1998 20:'~6 81~030~5~ P~GE. 15 9~ 29:10:38 ~ BELL :~1 350302~0 ~ 16~ 47 Herein, the Reed-Solo~on code i~ produced ~or a 12-byte signal. Then, an input code polynomial A(x) is gi~en by Equation ~6).
A(x) = ~ ai x (6) i=4 The coe~ficient ai in each term o~ the input code polynomial A(x) forms an ~1~ e~lt of the Galoi~ field ~orresponding to on~ ~yte o~ input data.
5!his e~odi~Lent is directed to double error corsection.
It is assumed that the ~uotient and the re~inr~r obtained by dividing ~y the generator polynomial F(x) a product of the input code polynomial A(x) and x . In this event, the relationship given by Equation (7) holds.
A(x) x = q(x)F(x) ~ r(x) (7) Herein, ~he product o~ the input code poly~ mi ~1 A(x) and x and the generator polyno~ial F(x) are represented by Equations (8) and (9), re~pecti~ely.
A(x)-x4 = ~ ai.xi (8) i=4 F (x) = ~ gi x (9) i--O
Herein, g4 = 1. .
Assuming that F~x) = O, the relationship in Equation (lO) holds.
x~ = ~ gi~x ~10) i=O
Let Equation (10) be substituted into A(x) x as shown in Equation (11) . Ac a result, the r~m~in~r r(x) as a CA 02252182 1998-10-29 ~
OCT 28 1998 2~:47 81~ P~GE.16 _ . . .. .
Sa-la-29;10:38 ;~ 8ELL .81~350302~ 7i 47 re~lurd~ byte in the format illuqtrated in Fig. 4 is obtained .
P~c~o--n~ of the In~ention:
~ hi~ in~ention relates to a Reed-Solomon encoding de~ice and method and, in particular, to such device and method adapted to error correction of a deQired numher of blocks not fewe~ than two.
In data communication, a re~n~n~y ~ignal i~
generally appPn~ to data ~information signal) to be trangm itted 50 that a data error occurring in a tr~r~ sion path can be detected and corrected at a receiving end. As the rP~ln~ncy signal to be appended to the information sign~l, a Reed-Solomon cod~ iy widely known.
~ xamples of a de~ice ~or car~ying out Reed-Solomon encoding are disclosed in J~nese U~ex~ined Patent tion (JP-A) Nos. 59-226951 (226951/1984), 60-73752 (73752/1985), and 9-36753 (36753/1997). ~o~e~er, each of these publication~ disclo~es no more than a Reed-Solomon encoding device adapted to error correction of a single block or two hlock~ ~t most.
In contr~t, as a Reed-Solomon encoding circuit adapted to error correction of a desired nu~ber of block~ not fewer than two, a circuit u~ing a polynomlal division circuit i~ diqclosed in ~Essence of Error Correction Encoding Technique~ upervised by Hideki Imai, Japan Indu.qtrial Technology Center, 1986), page 30 (hereinafter called a conventional example 1). In addition, a circuit for successi~ely processing input signals in a systolic array OCT 28 1998 20:39 81~030250 P~GE.03 . , 98-10-29:10:3~ BELL .a1 3so302~0 ~ 4~ 47 .
structure i~ disclosed in "A Con~truction Method for Reed-Solomon Codec Suitable for V~SI Design" (Proceedings o~
Institute of Electronics, Information, Communication Engineers of Japan, Vol. J71-A, pp. 751-759) ~hereinafter called a conventional example 2).
Fig. l is a block diagram sho~ing a ~tructure of the Reed-Solomon ~nco~; ng circuit in the conventional example l.
The Reed-Solomon enCo~; ng circuit of the conventional ~Y~ .~le 1 compri~es a di~ision circuit ~hich is composed of exclu~ive-OR circuits 531 through 53n, Galois ~ield multiplication circuits 541 through 5~n, and D flop-flop~ 55l through 55n and which calculate6 a ~ormula obtained by di~iding a polyno.i~1 correspondi~ to an input signal by a generator polynomial. Note that multipliers of the Galois field multiplication circuits 541 through 54n are det~ i n~
*rom coefficients of the generator polynomial F(x) represented by Equation tl).
F(x) = (x ~ a)(x I a2)(x + a3) . . (x + am) (l) In the abo~e-mentioned R~ed-Solomon encoding circuit, a selector 52 i8 responsive to a count value of a counter 51 and selects either the input in~ormatlon signal or an output signal of the D flo~-flop 55n as a selector output. ~us, the selector ~2 ~uccessi~ely output~ the in~ormation signal and a Reed-Solomon code as a re~ ncy code. Herein, by controlling which one is to be outputted ~rom the -~elector 52 with reference to the count value of the counter 51, it is possible to produce the Reed-Solomon code permitting error correction of a de3ired n ~~r of blocks.
OCT 28 1998 20: 39 81~0~ 0 PRGE. 04 9~-lC-29;10:38 ;~ X~ ELL ;~1~350302~0 $ S~ 47 Fig. 2 is a block diagram showing a structure of the Reed-Solomon encoding circuit in the con~entional example 2.
As illustrated in the figure, the Reed-Solo~on encoding circuit in the con~entional example 2 comprise~ a divi~ion circuit formed by ronn~ting in cascade a plurality of proce~sing elements PE illustrated in Fig. 3, instead of the division circuit composed of the exclusive-OR circuits ~1 through 53n, the Galois ~ield multiplication circuits 541 through 54n, and the D flop-flops 551 through 55n illustrated in ~ig. 1.
Ho~e~er, in each of the circuits in the conven~; ~n~l examples 1 and 2, the information signal is supplied one byte by one byte. E~ery time ~hen the information ~i~nal i.c ~upplied, orders or degrees are lo~ered by one at a time.
After completion o~ input of the information -~ignal, re~n~nCy 9ignalg corre8pO~Ai ng to respective te~m~ of a gr poly~omi~l as a result of calculation are successi~ely outputted. ~herefore, it takes a long time before completion o~ the Reed-Solomon encoding.
S~mm~ry o~ ~h~ Tnven~;on:
It is therefore an object of thi~ in~ention to provide a Reed-Solomon encoding device and method adapted to error correction of a desired number of blocks not fewer than two and capable of carrying out hig~-speed encoding by parallel processing.
According to a ~irst aspect of this invention, there i~ provided a Reed-Solomon encoding device which is supplied ~ith an input signal cont~;n;ng N data signal blocks in each single frame ~or carrying out a division of di~iding by a -- - -- ' ;CE;;;
OCT 28 19913 20: 40 51~50302~ P~IGE . 05 , _ . .
98-lo-29;lo:3a ~ BE-L ;81~350302C0 ~ 6i 47 generator polynomial a poly~m;~ corresp~n~ing to the input data ~ignal to produce ~ redun~dancy signal blocks corre~psnA;n~ to a r~ -;n~ar obtained by the di~ision and which compri~es:
~ ignal output means for outputting the N data signal block~ by J blocks at a time in a time division fashion ~uccessi~rely from those corresp~n~ing to h;~h~r order~ in the corre~po~d;ng polyns~;al;
adder m~ans, J in number, for calculating, with respect to J data ~ignal blocks outputted from the signal output mRans and J calculated block~ obt~ine~ by a predetermined op~ration ba~ed upon J pre~ ng data signal blocks outputted from the ~i~nal output mean~ at a p~eceA;ng timing, a ~um of a pair of the data signal and the calculated blocXs correspsn~j n~ in their orders to each other;
operating means, J in number, respon~ive to J sum blocks calculated by the J adder mean~, respecti~ely, for carrying out the p~edetermined operation to produce the J
calculated blocks which correspond to orders lower by J
le~els than those of the J ~um block~ calculated by the J
adder means, respectively, and which are supplied to the J
adder meanY, respecti~ely; and sQlective output m~an~, J in number, for outputting (N . J) times J data signal blocks ~upplied from the ~ignal output mean~ and sub-Qequently outputting (K . J) time~ J
calculated blocks produced by the J operating mean~;
N, K, and J being natural number~ where J i~ a mea~ure (or a di~isor) o~ both of N and X.
__ . , ~,, . __ OCT 25 199~ 20: 41 al~ 302~ P~GE. 05 98-10-29;10:3a ~ ; 8ELL :81~350302~0 ~ 7~ 47 With the above-mentioned Reed-Solomon encoding de~ice, it is possible to process the data qignal by ~ block_ at a time in parallel and to pro~uce X re~lln~ncy signal blocks ~uccessi~ely by J blocks at a time. It i~ there~ore pos~ible to perfonm high-speed proce~sing a~ fast a~ J tim~s as rom~red with the cohv6.~tional Reed-Solomon encoding device.
Fur~h~r~ore, as ~ar as N, X, and J are natural nll~h~rs ~here J i~ a measure of both of N and ~, the Reed-Solomon ~nco~;~g de~rice is capable of pro~ ; ng a Reed-Solomon code permitting error correction even if ~ is equal to 4 or more, i.e., permatting multiple error correction more than triple erro~
correction.
Th~ Reed-Solomon encoding device according to the fir~t aspect ~ay further co~prise:
~ N I ~C) . J)-ary counting means 4Or countin~ up at an inter~ral equal to that of~ output ti mingQ of the data signal block_ fro~ the 3ig~al output means. In this event:
the J -Qelective output means ~uccessively output J
data signal blo~ks supplied fro~ the ~ignal output means when the count value of the counting means is bet~een O and (N .
J - 1) and successi~rely output J calculated blockQ produced by the J operating means when the count value of the counting meanQ is between (N J) and ~(N + ~) ' J - 1) According to a second a~pect of this invention, there i~ provided a ~eed-Solomon enc:oding device which i9 supplied with an input signal cont~ining N data signal block~Q in each single ~rame for carrying out a divi~ion o~ dividing by a generator polyno~ial a polynomi~l corresponding to the input data signal to produce ~ re~n~nCy signal blocks OCT 28 1998 20:~1 81~ 2~ PRGE.07 9~-10-29,10:3~ BE~L :81~350302~ ~ 8f 41 eorrespon~in~ to a remainder obt~ by the di~ision and which compri-~es:
~ lYil;~y block appending means for appen~;ng I
a~Y; 1 i ~ry blocks to the N data signal block~;
signal output means for outputting the (N + I) dat~
signal bloeks, ineluding the auxiliary blocks appended by the ;l;~y bloek appen~g ~eans, by ~ bloeks at a time in a tim~ di~ision fashion successi~ely ~rom those eorrespo~ g to higher orders in the eor~esporl~; n~ polyT~
adder means, J in ~ or calculating, with respect to J data signal blocks outputted from the signal output means and J ealeulated block~ obt~ine~ by a predet~ ~ined operation based upon J preeeding data 8ignal bloeks outputted from the signal output means at a pxeceding t;ming, a sum of a pa~r of the data signal and the ealeulated blocks eorrespQ~; ng in their orders to each other;
operating means, J in number, responsive to J sum bloeks ealeulated by the J adder means, respectively, for c~-r~ing out the predete-mined operation to produee the J
caleulated ~loeks whieh eorrespond to orders lower by J
le~els than tho~e of the J sum bloeks ealculated by the J
adder means, respectiv~ly, and which are supplied to the J
adder means, respeeti~ely; and seleetive output means, J in nl~mher, for outputting ~tN + I) ~ J) time~ J data 9ignal blocks supplied from the signal output ~eans and subsequently outputting (x . J) times J calculated bloc~s produced by the J operating m~an~;
N, K, J, and I being natural numbers where J i~ a measure of both o~ (N + 1) and ~.
OCT 28 1998 20:42 61~50~250 P~GE.09 98-la-29,lc 3a ~ ELL ,~1~350302C0 ~ 9f 47 ~ ccording to the abo~e-mentioned Reed-Solomon encodlng device, the I auxiliary bloc~s are appended to the N data signal bloc~s. The re~l~nA~n~y signal blocks are produced ~or the (N ~ I) data signal block~ in total, including the ~ ry blocks appended thereto. Thus, the de~ice is applicable even if N can not be divided by J without a rem~n~qr. It i~ pos~ible to proce~s the (N + I) data signal blocks by J blocks at a time in paral~el and to pro~uce ~
r~ n~n~.~.y signal blocks ~ucces~ively by J blocks at a ~ime.
It i~ there~ore poc~ible to perform high-speed proces~ing as fa~t a~ J times as ro~p~red with the conventional Reed-Solomon encoding device. Fu~hermore, as far as N, X, and J
are natural n~lmher~ where J i~ a measure of both of (N + I) and X and I is smaller than J, the Reed-Solomon t~n~ot~i ng device i~ ~p~hle Of pro~ i ng a Reed-Solomon code permitting srror correction even if K is et~ual to 4 or more, i.e., permitting multiple error correction more than triple error correction.
The Reed-Solomon enc.~o~i; ng device according to the ~econd aspect may further comprise:
(tN + K) . J)-ary counting mean~ for counting up at an interval equal to t~at of output ti~ings o~ the data signal blocks from the signal output mean~. In this e~ent:
the J 3elective output mean~ ~ucce.~si~ely output J
data ~ignal block3 supplied from the ~ignal output means when the count value of the counting means i~ between O and (~N +
I) . J - 1) and s~cces~ively output J calculated block~
produced by the J operating means when the count value o~ the counting mean~ i.c between ((N + I) J) and ((N + ~ + K) CA 02252182 1998-10-29 _ .
OCT 28 l99e 20: ~13 81~030~ P~GE . 03 .
98-10-29:10:38 ;~ Y.~f ~ELL ,81~,350302CO ~; 10~ 47 J - 1).
In the Reed-Solomon encoding de~ice according to the second aspect:
each of the I auxiliary blocks may comprise a bit string of "O"
Ad~antageou~ly, the signal output mean~ at fir~t output~ the I a~lY~ y blocks as higher-order ones than the N data ~ignal blocks.
Thus, the highe~t-order term in the polynomial has a coe~ficient equal to O and is therefore excluded ~rom e ror correction by the Reed-Solomon code produced.
In eac~ of the Reed-Solomon encoding device according to the fir-~t and ~he second aspect3, for example;
each of the ~ operating m8an3 ~xecutes the predetermined operation upon coe~icients o~ such terms in the corre3po~di~g polyn~ that re~ind~s equal to one another are produced when their orders are ~i~ided by Ji and each o~ the J adder m~an8 calculates, with respect to the calculated bloc~s as a result of the operation by t~e J
operating means and the J data signal blocks outputted fro~
the signal output means, a sum of a pair of the calculated and the data signal block~ equal in their orders in the correspon~ing polynomi~l to each other In thi~ event, each o~ the J operating meanc may c~mprise recei~ing mean~ ~or r~cei~ing another calculated block which corresponds to the order of the calculated block calculated by this operating mQans and which is produced a~ a result of the operation b~ any operating means other than this operating means, and operating means for carrying out CA 02252182 1998-10-29 __.
OCT 28 1998 20:43 813~j03~2jl~ Pi~GE. 10 98-l0-29;lC:3a ;~ qc~ ELL ,~l~350302~0 ,~ llJ 47 the predet~rm;~ed operation by the use of the above-mentioned another calculated block recei~ed by the receiving means.
In each of the Reed-Solo~on encoding de~ice according to the fir~t and the s~cond a~pect~, for example:
the ~ignal output means produces a bit -~tring of "O"
when the J selecti~e output m~ans output the J sum blocks as a result of the addition by the J adder means.
ACcording to a third aspect of this in~ention, there iQ pro~ided a ~eed-Solomon encodang method which is supplied with an input signal cont~; n; n~ N data signal blocks in each single frame for carrying out a di~ision of dividing by a generator polynomial a polynomial corresponding to the input data sàgnal to produce ~ re~n~ncy ~ignal block~
corre~p~n~;n~ to a r~i~d~r ob~;n~ by the division, the method comprising:
a signal output step o~ outputting the N data signal block~ by ~ block~ at a time in a time division ~ashion successi~ely ~rom tho-~e corresponding to higher orders in the correspo~; ng polynomial;
an adding step of calculating, with ~e~pect to J data signal blockQ outputted in the signal output ~tep and J
calculated ~locks obt~ined by a p~edeterm;ns~ operation ba~ed upon J prece~in~ data signal blocks outputted in the s~gnal output step at a preceding ti~ing, a su~ of a pair of the data signal and the calc~lated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step o~ carrying out, in re~ponse to the J ~um blocks calculated in the ~ddin~ step, the predet~rmined operation to produce the J calculated block~ which correspond OCT 28 1998 20:44 81~0~0250 P~GE. 11 98-10-29,10:38 ;~ BELL ~ ,350302~0 ~ J 4 to orders lower by J levels than those of the sum blocks calculated in t~e ~Ai ng step and which are re~pecti~ely added in the ~d~n~ step at ~ next t;ming;
N, X, and J ~eing natural number~ w~ere J i~ a measure of both of N and ~.
According to a fourth aspect of this invention, there i-~ provided a Reed-Solomon encoding method ~hich is 8upplied with an input signal cont~inin~ N data signal ~locks in eac~
single fr~ for carrying out a di~ision of dividing by a generator poly~-iAl a polynomial correspo~ g to the input data ~ignal to produce K re~n~ncy signal blocks correspo~ding to a ~. ~;n~f~r obt~;ne~ by the di~ision, the method comprising:
an auxiliary signal appending step of appending I
al-Y;li~ry blocks to the data s~gnal N blocXs;
a si~al output step Of outputting the (N + I) data signal blocks, including the at~Yi 1; ~ty blocks appended in the ~llY;liAt~ signal app~ndjn~ step, by J ~locks at a time in a time division fashion succes3ively $rom those corresponding to higher order~ in the corresponding polynomial;
an ~ ing step of calculating, with re~pect to J data signal blocks outputted in the s;~n~l output step and J
calculated ~locks obtained by a predeterm;ne~ operation based upon J preceding data signal blocks outputted in the sif~nal output step at a pre~s~i~g timing, a sum of a pair of the data signal and the calculated bloc~s corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in respon~e to the J sum blocks calculated in the :3~rling step, the predeterm;ned CA 02252l82 l998-l0-29 OCT 28 1999 20:4~ 81~ 2~ PRGE.12 9~-1û-2~;~0:38 ~ 6~ ELL :81~350302~a ~; 13~ 47 .
operation to produce the J calculated block~ which correspond to orders lower by J le~els than those of the 5um block~
calcula~ed in the ~i ng s~ep and which are respectively added in the ~;n~ step at a next tim;~g;
N, ~, ~, and I being natural numbers where J is a measure of both of (N ~ I) and K.
~ r; ef Des~ ;on o~ ~he Drawi~:
Fig. 1 is a block diagram sho~ing a structure of a first conventional Reed-Solomon encoding circuit;
Fig. 2 is a block diagram showing a structure of a second conventional Reed-Solomon encoding circuit;
Fig. 3 is a ~iew showing a ~tructure of a P~ in Fig. 2;
Fig. ~ is a view showing a format of data en~o~ by Reed-Solomon encoding according to a first embodi~ent of this in~e~tion;
Fig. 5 is a bloc~ diagram showing a structure of a Reed-Solomon encoding de~ice according to the first embodiment of this inYention;
Fig. 6 i~ a view showing a format o~ data encoded by Reed-Solomon encoding according to a ~econd z ho~iment of thi~ in~ention; and Fig. 7 is a block diagram showing a structure of a Reed-Solomon ~co~;n~ de~ice according to the second embod~ment of this in~ention ~ tail~d DescriP~io~ of t~e Tnv~ntion Now, description ~ill be made abo~t em~odimentq of this in~ention with reference to the dra~ing.
OCT 25 l99G 20:45 61~0~25~ P~GE.13 . ._ 98-10-29;1~:3~ t~ BELL ;~1~,350302~0 ~i 14~ 47 [lst Embodiment~
In this e~bodi~ent, a (16, 12) Reed-Solomon encoding device which perform~ parallel p~oce~ing o~ two bytes and which can carry out error correction of two bytec will be de~cribed for brevity o~ description. A data format after Reed-Solomon encoding in this e~bodiment is illustrated in ~ig. 4.
At first, de~cription will be made about the principle of the Reed-Solomon en~o~;~g in this embodiment.
The Reed-Solomon encoding i executed by the use o~ a set, called a Ga~ois field, ha~ing a predetsrmined rule. The Galois field i~ clo~ed ~ithin tho Galois ~ield for multiplication and addition and thus for~s a complete set.
Therefore, data ha~ing a predet~rmined bit length ~one data block) can be replaced by elements of the Galois field. ~et the bit length be represented by N. Then, the Galois f ield i~ ~ormed by the elements of 2N or less in nu~er.
In this embodiment, a singlo block of a signal compri~es one byte, i.e., eight bits aa will later be de~cribed. The Galois field then comprises the elements of 2~ = 256 in number. The~e elements of the Galois field are p ssed as ~0, 1, a ~ a2, a3, a254) correspond to a ~ignal formed by a combination of vector exp~ession of coefficients of a seventh-order polyno i~l a~ a r~m~;nd~r obtained by di~iding x tn = O, 1, ..., 255) by a primiti~e polynom al G~x) hereunder on a binary operation and zero Qlements (O, O, O, O, O, O, O, O).
G~x) = x8 + x4 ~ x3 + x2 + 1 (2) OCT 2E1 1998 20:46 81.5~0~ Pf1GE. 14 sa-10-25;1~:38 ~ EL~ ;81~35C302~0 If n = O for example, the r~; nd~r ob~; n~A by dividing xn by the primitive polynomial G(x) is equal to 1.
~herefore, the elements of the Galo~ field correspond to (O, O, O, O, O, O, O, l). If n = l, the r~m~inde~ obtained by dividing xn by the psimitive polynomial G(x) i8 equal to x.
Then, the elemenks of the Galoi-q ~ield correspond to (O, O, O, O, O, O, l, O). If aP correspond~ to tb7, b6, b5, b4, b3, b2, bl, bo)~ the relation~hip in Equation (3) hold~ (~here each of b7 to bo iY equal to O or l).
aP = ~ bi-ai ~3) i=O
At this time, each addition i~ executed as a ~inary ~ummation per bit. In this embodiment, the addition i9 carried out ~y ~he use of an exclusive OR operation per bit as will later be descri~ed. There~ore, the result~ of addition and subtraction are equi~alent. On the other hand, the relationship in Equation (4) holds for multiplication of the elements of the Galois field.
aP x aq - a (P~q) ~4) From Equations (3) and (4), a product of t~o given vectors i5 calculated.
In this e~bodi~ent, two bytes of the signal are proce~ed in parallel. Then, con~ideration will be made about the ca~e wh~re division o~ quadratic coefficients i~
proce~ed at a ti~e. To produce the Reed-Solomon code permitting two-byte error correction, a generator polynomial F(x) iq a fourth-order polynomial given by Equation (5).
F(x) = ~x + a)(x ~ a2)(x ~ ~3)(x + ~) (5) .. . _ . _ _ .. , . . ... _ _ .
OCT 28 1998 20:'~6 81~030~5~ P~GE. 15 9~ 29:10:38 ~ BELL :~1 350302~0 ~ 16~ 47 Herein, the Reed-Solo~on code i~ produced ~or a 12-byte signal. Then, an input code polynomial A(x) is gi~en by Equation ~6).
A(x) = ~ ai x (6) i=4 The coe~ficient ai in each term o~ the input code polynomial A(x) forms an ~1~ e~lt of the Galoi~ field ~orresponding to on~ ~yte o~ input data.
5!his e~odi~Lent is directed to double error corsection.
It is assumed that the ~uotient and the re~inr~r obtained by dividing ~y the generator polynomial F(x) a product of the input code polynomial A(x) and x . In this event, the relationship given by Equation (7) holds.
A(x) x = q(x)F(x) ~ r(x) (7) Herein, ~he product o~ the input code poly~ mi ~1 A(x) and x and the generator polyno~ial F(x) are represented by Equations (8) and (9), re~pecti~ely.
A(x)-x4 = ~ ai.xi (8) i=4 F (x) = ~ gi x (9) i--O
Herein, g4 = 1. .
Assuming that F~x) = O, the relationship in Equation (lO) holds.
x~ = ~ gi~x ~10) i=O
Let Equation (10) be substituted into A(x) x as shown in Equation (11) . Ac a result, the r~m~in~r r(x) as a CA 02252182 1998-10-29 ~
OCT 28 1998 2~:47 81~ P~GE.16 _ . . .. .
Sa-la-29;10:38 ;~ 8ELL .81~350302~ 7i 47 re~lurd~ byte in the format illuqtrated in Fig. 4 is obtained .
A (x) x4 = al5 xi+ll ~ gi xi + ~ ai x i=O i=g = al5 ~ gi xi 11 + ~ ai x i=O i=O
= alS~g3~Xl4 + al4~Xl4 2 lO
+ ~; (al5 g~ + a~ ) X + ~; ai~x i=O i-4 (alS g3 + al4) xll ~; gi x3 i=O
+ (alS-g3 ~ ai+ll) xi~ ai X
i--4~
~ { ~al5 g3 ~ al4)gi + al5 gi-l + ai+ll) } 'X
i=O
+ ~ ~i-~ (11) i=4 ~erein, gl = ~-OCT 2s 1998 20: 47 B~ 0~2~ P~GE. 17 98-lC-29:10:3~ BELL ;81~3503~2C0 ~ la~ 47 Let hi be defined as ~ho~n in Equation (12). Then, Equation ~11) can be rewritten into Equation (13).
hi = g3'gi ~ g~-1 (12) 3 1~
~(x) x4 = ~(a15~hi ~ a1~ gi)x10~i + ~ ai x1 tl3) i=O i=4 ~ hu~, it is po~-~ible to lower the order of the input data simultaneousiy by two levels. This means that the input two-byte data are multiplied by gi and hi and re~ultant products are added to next input data. In this case, gi and h~ correspond to multipliers of a Galoi~ field multiplication circuit which will later be de~cribed. Herein, hl can be obtained fro~ a coeffic~ent of a r~in~ pol~nomial obt~; n~ by di~iding x by the generator polynomial F(x). ~y the u~e of hi obtained f~om the generator polyn~ l F~x), it i9 pos~ible to simultaneou~ly lower the order by two level~
and to obtain the re~7in~r r(x).
~ trancm;s~ion code polyno~i~l C(x) upon data tran~mission through a tranqmi~sion path i5 calculated by Esuation (14).
C(x) = A(x)-x2X2 _ r(x) (14) In the similar r~nn~r~ equations required in circuit formation can be ob~i n~l for arly number of bytes of 'che data signal or any number of byte~ o~ the red~lnA~cy signal and e~en if the ~lock compri~e~ any other unit than byte.
Now, the Reed-Solomon encoding de~ice in this embodiment ha~ing the structure according to the abo~e-~entioned principle will be described with reference to a block diagram in Fig. 5.
. _. .. _ . . . ............. .. . . . . _ _ OCT 28 1998 20: 43 81~ 30250 P~GE. 1~
98-10-29;10:38 ;~ c~ ; BELL ;81~350302C0 ~ 19~ 47 .
As illustrated in the figure, the Reed-Solomon enco~;ng device compris~s a signal separati~g circuit 100, a counter 1, selectors 2 and 3, exclusi~e-OR circuits 4 and 5, Galois field multiplication circuits 6 through 1~, exclu~ive-OR circuits 14 through 19, and D flip-flops 20 through 23.
The Reed-Solomon encoding deYice is supplied with an extern~l input signal including clocks and a data signal.
The ~ignal separating circuit 100 is supplied with a single frame (12 byte~) o~ the data ~isnal. In synchronism with the clocks, the sig~al separating circuit 100 distributes the input data ~ignal byte by byte in a ~nnr~r such that one to be a coefficient of a higher-order ~odd-numbered order) term in an input code pol~nomial is allotted to a signal B while another to be a coef~icient of a lower-order (even-nu~bered order) term is allotte~ to a signal A.
~he signal-~ ~ and B are successi~ely outputted from a higher-order one in the corre pon~ing input code poly~om;~l. ~8 will later be d~scri~ed, the signal ~eparating circuit 100 output~ the input data ~ignal as the signals A and B when a count ~alue of the counter 1 i~ bet~een "O" and "5". On the other hand, the ~ignal separating circuit 100 produces "00000000" as the signals A and B when the count ~alue o~ the counter 1 is "6" or "7" as will later be de~cribed.
The co~nter 1 is an octal counter counted up at e~ery clock input.
The selector 2 i~ responsive to the count ~alue of the counter 1 and selects as an output either the ~ignal A ~hich is the external input signal or a signal C ~hich i~ an output signal of the D flip-~10p 21. ~he selector 3 is responsi~e OCT 28 1998 20:~8 813~ 0250 PflGE. 19 98-1~-29;10:38 ;~ EL~ :81'350302~0 ~ 20f 47 .
to the count ~alue of the counter 1 an~ selects as an output either the ~ignal ~ which is the extsrn~l input ignal and a s;~n~l D which is an output signal of the D flip-~lop 23.
The selectors 2 and 3 selecta a~ outputs the signals A and B
when the count value of the counter 1 i~ between "0" and "5"
and the ~ignals C and D when the count value of the counter 1 is ll6ll or "7".
For each of the exclu~ OR circuits 4 and 5, the Galoic field multiplication circuits 6 through 13, the exclusive-O~ circuits 14 through 19, and the D flop-flop-~ 20 through 23, eight similar circuits are arranged in parallel in corre~pon~nce to the ~ignal length ~1 byte = 8 bits) of each of the signals A and B. By the exclu~i~e-OR circuits 4 and 5, the Galois field multiplication circuits 6 through 13, the exclusi~e-OR circuits 14 through 19, and the D flop-flopc 20 through 23, the r~ ~in~e~ r ~x) de~cribed in conjunction with the abo~e-mentioned principle is calculated.
The e~clusi~e-OR circuit 4 exocute~ an exclusive OR
operation upon the signals A and C (output signal of the D
flip-flop 211 to produce an output signal which is supplied to the Galois field multiplication ci~cuits 6 through 9. ~he exclu~i~e-OR circuit 5 executes an exclusiYe OR operation upon the si~n~ls B and D (output signal of the D flip-flop 23) per bit to produce an outp~t ~ignal which is supplied to the Galois field multiplication circuits 10 through 13. The operation in each of the exclusive-OR circuit~ 4 and 5 corresponds to addition of the Galois fields.
The multipliers in the Galois field multiplication circ~its 6 through 9 are calculated ~rom coefficients of the OCT 28 1998 20:~9 81~030250 P~GE.2 9a-lO-29 lO:3~ BE~L ;8l~,350302CO ~ 2l~ 47 generator polyn~ i~l F(Y) given by Equation (5) and are equal to a lo a 81 a 251 and a 76, respecti~elY-The Galoi~ field multiplication circuits 6 through 9multiply the output signal of the exclusi~e-OR circuit 4 by the a~ove-mentioned multipliers to produce output signals.
The multiplie-s in the Galois field multiplication circuits 10 through 13 are calculated from r~;n~e~3 obt~i~e~ by di~iding x5 by the generator polynomial F(x) and are e~ual to a ~6 a 63 ~ 192 and ~165 regpQctivel The Galoi~ field multiplication circuits 10 through 13 multiply the output signal of the exclu3ive-OR circuit 5 by ~he abo~e-~entioned multipliers to produce output signals.
The exclu~ive-OR circuit 14 execute3 an exclusive 0 operation upon the output s~ of the Galois field multiplication circuits 6 and ~0. This correspond3 to addition of the Galois fields. An output ~ignal of the exclusi~e-OR circuit 14 is a coe~ficient of a lo~er-o~der one o~ even-n~ b~red ord~r term~ produced by the operation and is lower in order by four le~els than the coefficient o~ the signal ~. The D flip-flop 20 delays the output signal of the exclusive-OR circuit 14 by one clock tim;ng to prod~ce a delayed output signal. Thus, the coe~ficient-~ and the orde~
a~ the next ~ g (when the count ~alue of the counter 1 proceeds to a next value) are matched with respect to the exclu~i~e-OR circuits 15 and 16.
The exclusive-O~ circuit 15 executes an exclusive OR
operation upon the output signals of the D flip-flop 20 and the Galois ~ield multiplicatio~ circuit 7. The excl~siv~-OR
circuit 16 executes an exclusive OR operation upon the output . _ .. _ . _ . . _, .. , . . . ._ _ OCT 28 1998 20:50 81~ 0~ld230 PRGE.21 98-10-29:10:38 ;i~ ~ffl~ 8ELL ;8l~,350302CO i~ 22i 47 s;~n~1s o~ the exclusi~e-OR circuit 15 and the Galois field multiplication circuit 10. Each of these operations corresponds to the addition of the Galois ~ields. Arl output signal of the exclusive-OR circuit 16 is a coefficient of a h~ r-order one of eYen~nu~bered orde~ terms pro~ by the operation and i9 lower in order by two levels than the coefficient of the signal A.
The D flip-flop 21 delays the output signal of the exclusi~e-OR circuit 16 by one clock timing to produce the 3ignal C which i8 supplied to the selector 2 and the exclusive-OR circ~it 4. ~he signal C corresponds to a ter~
of an order equal to that o~ the ~ignal A produced b~ the ~ignal separating circuit 100 at the ~ame t; i~g. The signal i~ added to the -qignal A by the exclusi~e-OR circuit 4. A
coef~icient of a term produced during the operation is reflected in the operation o~ the coefficient of the term lo~er by two le~el~.
The exclusi~e-OR circuit 17 execute~ an exclusive O~
operation upon the output ~ignals o~ the Galois ~ield multiplication circuits 8 and 12. This correspond~ to addition of the Galois fieldq. An output signal of the exclusive-OR circuit 17 i~ a coefficient of a lower-order one of odd-numbered order terms produced by the operation and is lower in order by ~our levels than the coefficient of the signal B. The D flip-~lop 22 delays the output ~ignal of the exclusive-OR circuit 17 by one clock timing to produce a delayed output ~ignal. Thus, the coefficients and the order~
at the next t; ~ ng ~when the count value of the counter 1 proceeds to a next value) are matched with respect to the OCT 28 1998 20: 5a 813.5~03~25~ PRGE . 22 9~-l0-29:lC:38 ~ BELL ,8l~350302~0 ~ 23~ 47 exclusive-OR circuits 18 and 19.
The exclusi~e-OR circuit 18 executes an exclusive OR
operation upon the output signals of the D flip-flop 22 and the Galois ~ield multiplication circuit 9. The exclusive-OR
circuit 19 executes an exclusi~e OR operation upon the output signals of the exclusive-OR circuit 18 a~d the Galois ~ield multiplication circuit 13. Each ~f these ope~ation~
corresponds to the addition o~ th~ Galois fields. An output signal of the exclusive-O~ circuit 19 i~ a coefficient of a higher-order one of odd-numbered order term~ produced by the operation and is lower in order by two levels than the coefficient o~ the si~nal B.
The D flip-flop 23 delay~ the output ~ignal of the exclus~ve-OR circuit lS ~y one ~locX ti~; n~ to produce the ~;~n~l D ~hich is supplied to the selector 3 and the exclusive-OR ci~cuit 5. The sig~al D corresponds to a term of an order eq~al to that of the signal B produced by the ~ignal separating circuit 100 at the same ~i ;~g. The signal is added to the signal B by the exclusi~e-OR circuit 4. A
coefficient o~ a. term produced during the opsration is reflected in the operat.ion of the coefficient of the ter~
lower by two le~els.
With the above-mentioned structure, the order~ of the output ~ignal~ of the D flip-flops 21 and 23 a~e lo~ered ~y two levels at a time. Those having th~ ~econd and the third order~ when the counter 1 ~as a value ~l6~l are changed into zeroth-order and first-order one~, re~pectively, when the counter 1 has a value "7~'. Thus, the output ~ignals produced b~ the D ~lip-flops 21 and 23 when the counter 1 has the OCT 28 1998 20:51 81~030~50 P~GE.23 s~-la-2s;l0 38 ~ ~ EL~ 3s~302'o ~ 24~ 47 ~alue of 1'6" and l'7'' are the coeffi~ients of the respecti~e terms of the ~ n~er r(x).
Each of the D flip-flop~ 20 through 23 is cleared a~
the output timing o~ the dat~ signal in the next frame, i.e., at the time instant when the count ~alue of the counter 1 ret~rns from "7" to "0~'.
No~, de~cription will be ~ade about an operation of the Reed-Solomon'encoding device o~ this embodiment.
In synchronism with ~e clock~, i.e., in synchronism with the output t;mi n~ of ~he signals ~ and B from the signal separating circuit 100, the counter 1 successi~ely counts "0 to ~'7". Herein, the signal ~eparating circuit 100 iq already supplied with the data signal of a single f~ame (12 bytes).
When the value of the counter 1 return~ from "7" to "0" ~ollowing the input of the clock~, the D flip-flops 20 through 23 are cleared. Simultaneously, the ~ignal separating circuit 100 produce~, a-q the signals B and ~, coefficient~ al5 and al4 of fifteenth-order and fourteenth-order terms of the product (fi~teenth-order polyno~ial) obtained by multiplying the input code polynomial A(x) correQponding to the data signal by x2X2, respectively.
~ erein, each of the D ~lip-flop~ 2~ through 23 i9 cleared and therefore does not affect the operation at the exclu~i~e-OR circuits 15, 18, ~, and 5. The exclusive-O~
ci~cuits 4 and 5 produce the signal~ A and B as they are, respecti~ely.
A polynomial a~ a result of di~iding the polynomial corresponding to the signals A and B by the generator polynomial F(x) compri~es thirteenth-order to tenth-order OCT 28 1998 20: 52 81~ 31~250 P~GE. 24 . .
98-lC-29'10:38 ~ c~ ELL ,81~35G302~G ~ ~, 4/
term-~.
The coefficient of the thirteenth-order term i~
calculated by the Galois field multiplication circuit~ 9 and 13 and the exclu~ive-OR circuit~ 18 and 19 and supplied to the D flip-flop 23. The coef~i cient of the t~elfth-order term i9 calculated by the Galois field multiplication circuit~ 7 and 11 and the exclusi~e-O~ circuits lS and 16 and supplied to the D flip-~lop 23. T~e coe~ficient of the ele~enth-order term i~ calculated by the Galois field multiplication circuits 8 and 12 and t~e exclusi~e-OR cixcuit 17 and supplied to the D flip-flop 21. The coefficient of the tenth-order term i~ calculated by the Galoi~ field multiplication circuits 6 and 7 and the exclu~ive-OR circuit 14 and supplied to the D ~lip-flop 20.
Next, when the counter has the value 'l2ll, the signal separating circuit 100 outputs, a~ the ~ignals B and A, the coef~icients a13 and a14 o~ thirteenth-order and fourteenth-order term~ of a product (fifteenth-order polyno:~~l) obtained by multiplying thc input code polync i~l A(x) corre~ponding to the data signal by x , re3pectively.
Herein, the D flip-flops 20 through 23 output the coef~icients of tenth-order to thirteenth-order terms of the poly~o~ia~ produced by the operation when the counter 1 ha~
the value l'2".
The exclusive-OR circuit 5 add~ thn coefficient al3 of the thirteenth-order term of the product obtained by multiplying the input code polynomial A (x) hy x and the coe~ficient of the thirteenth-order term calculated at the prec~in~ 1j~in~. The exclusi~re-OR circuit 4 add~ the OCT 28 1998 20:52 81~030250 P~GE.25 _, . . .
9~-10-29,10:38 ~ ?; BELL ,81~350302CO t; 26~ 47 . , .
coefficient al2 of the twelfth-order term of the product o~tained by multiplying the input code polynomial A~x) by x and the coe~ficient of the twel~th-order term calculated at the preceding t;~; ng, A polynomial as a result of di~iding the polynomial correspon~;ng to the ~ ls produced by the exclusive-OR
circuits 4 and 5 by the generator polynomial F~x) comprises eleventh-order to eighth-order terms.
The coefficient of the ele~enth-order term i~
calculated ~y the Galois field multiplication circuit~ 9 and 13 and the exclu~i~e-OR circuit 19 and i9 added by the exclusive-O~ circuit 18 to the coefficient o~ the eleventh-order term produced when the counter 1 has the v~lue "0" to ~e supplied to the D flip-flop 23. The coe~ficient o~ the tenth-o~der term i9 calculated by the Galois ~ield multiplication circuit-~ 7 and 11 and the exclusive-OR
circuits 15 and 16 and is added by the exclusive-OR circuit 15 to the coefficient of the tenth-order term produced when the counter 1 has the ~alue "0" to be supplied to the D flip-flop 23. The coefficient of the ninth-order term iR
calculated by the Galoi-~ field multiplication circuit5 8 and 12 and the exclusive-OR circuit 17 and supplied to the D
flip-flop 21. The coefficient of the eighth-order term is calculated by the Galois ~ield multiplication circuit~ 6 and 7 and the exclu~ive-OR circuit 14 and is supplied to the D
flip-flop 20.
Subsequently, similar calculation is repeated. Upon calculation when the counte~ 1 has the ~al~e "5", the D flip-~lops 20 through 23 are ~upplied with the coefficients of the OCT 28 1998 20: 53 81~032252 P~GE . 26 98-l0-29;l0:3~ h~ ELL ;~l~350302~0 ~ 27~ ~7 third-order to the zeroth-order terms.
When the counter 1 has the value between ll~'' and ~l5'', the selectors 2 and 3 select the signals A and B for output aY the coefficients of the respective terms of the polynomial obt~;ne~ by multiplying the input code polynom;~ A(x) by x2x2 ~
When the counter 1 has the value ~6", the exclusive-OR
circuits 4 and 5 output the coefficients o* the second-order and the third-order terss supplied to the D flip-flops 21 and 23 when the counter 1 ha~ the value "5", respecti~ely. At thiQ time, the selector~ 2 and 3 select the signals C and D
for out~ut a~ the coe~ficients of the second-order and the third-order terms of the r~ n~er r(x), re~pecti~ely. When the counter 1 has the value "7", the ~electors 2 and 3 select the signal~ C and D for output as the coefficients of the zeroth-order and the first-order term~ of the r~-;n~r r(x).
Supplied with the data signal of 12 byteq and the redl~d~ signal of ~ bytes outp~tted from the ~electors 2 and 3 by the above-mentioned proces~, a transmission cod~
poly~e~i~l operating circuit (not shown) executes the operation given by Equation (14) to produce a transmission code polynomial C(x). Then, a signal corresponAing to the coef~icientg of the respective terms of the tr~nsmi~sion cod0 polyno~ is deli~ered ~rom the transmission code polynomial operating circuit to a tran~mission line.
As described abo~e, in the Reed-Solomon encodins de~ice of th~s embodiment, the information separating circuit lOO outputs the data signal as the sigmals A and E~
simultaneou~ly by two ~ytes at a time. The two byte signals OCT 28 1998 20: 54 81~0~2~ P~GE. 27 .
9~-1û-29;10:3~ ELL :81.350302C0 ~ 2~ 47 .
are processed in parallel. The re~nA~cy signal is produced by t~o bytes at a time to be outputted. Therefore, Reed-Solomon enco~i ng i~ carried out at a _peed a~ high as t~ice as compared with the co~ tien~l Reed-Solomon encoding device. It i~ therefore possible to process a signal of a twice ~r~r;ty.
In the above-mentioned first embodiment, de~cription has been directed to the ca~e ~here the data ~ignal has twelve byte~ and the re~ ncy sign~1 ha~ four bytes.
However, t~e data -Qignal may ha~e any number o~ bytes up to 252 bytes ~but the number of byte~ must be an e~en number).
In either e~ent, the number of bytes of the red~n~n~y sign~l is equal to 4. The counter 1 is of a ((number of bytes of the data signal ~ 4) . 2)-ary type. For example, when the data signal has 252 ~ytes, the ~electors 2 and 3 output the ~ignal~ A and ~, respecti~ely, when the counter 1 has the value bet~een "O" and "125" and the signal~ C and D when th~
counter 1 haQ the value l'126" or "127".
In the abo~e-mentioned first embodim~nt, description has been directed to the Reed-Solomon encoding circuit for executing Reed-~olomon encoding with an error co~recting func~ion of two bytes. Ho~ever, the error correction function of three byte~ or more can be achieved in the gimi 1 ~r m~nn~r, In this e~ent, the counter 1 i~ of a (~numb~r of bytes o~ the data signal + number of bytes of the re~-~nd~ncy QigTlal) ~ 2)-a~y type The selectors 2 and 3 output the signals C and D when the value of the counter is a (number of byte~ o~ the re~n~ancy signal . 2)-th one ~rom the laRt.
OCT 28 1998 20: 54 81~030250 Pl:~GE. 2e 98-t0-29:10:38 ~ BEL~ ;81~,350302CO $ 29~ 47 , In the above-mentioned fi~st embodiment, de~cription has been made about the case uhere the ~ignal is proce~-~ed by two byte~ in parallel. Howe~er, ~ignal procesqing by three or more bytes in parallel can be achieved in the si~ r manner. It is noted here that, in ca~e of the signal processing by ~ bytes in parallel, J must be a mea~ure of both of the number N of bytes o~ the data signal and the number ~ of byteQ of the re~n~ncy signal. In this case, the Reed-Solomon en~o~;~g device is implemented by a circuit ~tructure aecording to equation_ modified in the ~n~
~imilar to the above-mentioned principle.
In the above-~entioned first embc~ t, a ~ingle block comprise~ one byte (8 bits) in each of the data signal and the re~ c~ signal. However, the single block of data in this i~ention may comprise any desired number of ~its.
In this case, the element~ of the Galois field which correspond to the number of bits of the ~ingle block are used a~ the elementQ of,the input code poly~omi~l A (x) .
[2nd Embodiment~
In the fir~t embodiment, description ha~ been made about the case where the number of byte~ of the data signal can be di~ided without a rem~ er by the num~er of the signals sepa~ated by the signal separating circuit 0. In contrast, this embod~ment is directed to a Reed-Solomon encodin~ circuit in ~hich a dummy byte is added to the data ~ignal so that a total num~er of byte~ can be divided ~ithout a .- -; n~er by the number of ~yte~ of the signals separated by the signal separating circuit 0.
OCT 28 1998 20:55 1 - 81~03~25~ P~GE.25 98~ 29:10:38 ,~ ; BELL 81~350302CO i~ 30~ 47 Fig. 7 is a block diagram sho~ing the structure o~ the Reed-Solomon encoding de~ice according to this embodiment.
As illustrated in the figure, the Reed-Solomon encoding device comprise3 a dum~y byte append~n~ circuit 101 and a ~eed-Solomon encoding circuit 102.
The dummy byte appending circuit 102 appends a dummy byte o~ a single byte to an input data ~ignal in which each single frame comprises 251 byte~, a~d ~upplies the signal to the Reed-Solomon encoding circuit 102. Herein, the dummy byte appended to the data signal by the dummy byte appen~ing circuit 102 is ~IOOOOOOOO~. This dum~y ~yte ser~es as a hjghest-order term in the input code polynomial A(x).
Therefore, the highest-order term ha3 a coefficient equal to "O" ancl i9 not subjected to error correction by a re~ultant Re~d-Solo~ n code.
The Reed-Solomon encoding circuit 102 is ~;~; l~r in structure to the ~eed-Sol~mon encoding device illustrated in Fig. 5. ~owever, the counter 1 is of a (~251 + 4 ~ 1) . 2) = 128-ary type. The selectors 2 and 3 select an~ output the signals from the signal separating circuit O when the counte~
1 ha8 a count value between "O" and "125" and the 3ignals C
and D when the count value i9 ~'125~' or ~126~.
The ~ignal separating eircuit O is supplied ~ith the data signal ha~ing 252 bits in total including the du~my byte of a single byte. The Reed-Solomon encoding circuit 102 carrie~ out proces~ing 8i~ r to that of the ~irst embodime~t. ln this embodiment, ho~ever, the selectors 2 and 3 select and output the ~ignals from the signal separating circuit O when the counter 1 has the count value ~etween "O"
OCT 28 1998 2z:56 81~ 0~ P~GE.32 , .
98-1~-2g:10:38 ~ EL~ ;al.3so302~o ~ 31 and ~125~' and the signals C and D when the count value is 125 or 126.
As described aboYe, the Reed-Solomon encoding de~ice of this embodiment p~oduces the Reed-Solo~on code from the data signal with the dummy byte added thereto. There~ore, even if the number of bytes of the data signal can not be divided without a r~in~r by the number of separated signal~ prod~ced by the qignal separating circuit 0, parallel processing is posqible.
In the second embodiment, de~cription has been made about the case where the data ~;gn~l i5 ~eparated by the signal separating circuit O into two for parallel processing.
It is noted here that prod~ction of the Reed-Solomon code with the dummy byte added to the data signal is also applicable to the case where t~e ~ r of the separated -~ignal~ deri~ed from the data signal i~ e~ual to three or more. For example, i~ the data ~ignal o~ N byte~ i~
separated into every J bytes ~or parallel proce~si~g, the dummy byte~ of I bytes are added ~here ~N + I) i~ a measure of J ~I ~ J).
A~ described above, according to thi9 invention, the data signal i~ proce~ed by J blocks at a time in parallel to produce the re~l~n~cy signal by J blocks at a time.
There~ore, as compared with the con~entio~al Reed-Solomon encoding de~ice, high-speed proceqsing aq high as J time~ can be carried out. In this Reed-Solomon encoding device, an~
desired nllmber can be selected as the number N o~ the blocks of the re~ cy signaI as ~ar as a predet~r~ned condition i~ m0t. Therefore, it is possible to produce the Reed-OCT 28 1998 20: 56 81~ a25~ P~GE . 31 9~-10-29:10:3~ e~ BELL al3350302C0 ~ 32~ 47 Solomon code pen~itting multiple error correctiorl.
An auxiliary signal of I blocks is added to the data ~ignal of N blocks and the redundancy ~ignal i9 produced for t~e data -c~ignal ha~ring (N + I) block~ in total with the Yi ~ ry signal added. l'here~ore, e-ren if ~ can not be di~ided by ~ ~ithout a ro-~in~e~, it iQ po~ible to perform Reed-Solomon encoding by parallel processing.
. . . _ _,,, , , ,, I _, , , ,, - . _ OCT 28 199~1 20:56 el~ 225~ PRGE.32
= alS~g3~Xl4 + al4~Xl4 2 lO
+ ~; (al5 g~ + a~ ) X + ~; ai~x i=O i-4 (alS g3 + al4) xll ~; gi x3 i=O
+ (alS-g3 ~ ai+ll) xi~ ai X
i--4~
~ { ~al5 g3 ~ al4)gi + al5 gi-l + ai+ll) } 'X
i=O
+ ~ ~i-~ (11) i=4 ~erein, gl = ~-OCT 2s 1998 20: 47 B~ 0~2~ P~GE. 17 98-lC-29:10:3~ BELL ;81~3503~2C0 ~ la~ 47 Let hi be defined as ~ho~n in Equation (12). Then, Equation ~11) can be rewritten into Equation (13).
hi = g3'gi ~ g~-1 (12) 3 1~
~(x) x4 = ~(a15~hi ~ a1~ gi)x10~i + ~ ai x1 tl3) i=O i=4 ~ hu~, it is po~-~ible to lower the order of the input data simultaneousiy by two levels. This means that the input two-byte data are multiplied by gi and hi and re~ultant products are added to next input data. In this case, gi and h~ correspond to multipliers of a Galoi~ field multiplication circuit which will later be de~cribed. Herein, hl can be obtained fro~ a coeffic~ent of a r~in~ pol~nomial obt~; n~ by di~iding x by the generator polynomial F(x). ~y the u~e of hi obtained f~om the generator polyn~ l F~x), it i9 pos~ible to simultaneou~ly lower the order by two level~
and to obtain the re~7in~r r(x).
~ trancm;s~ion code polyno~i~l C(x) upon data tran~mission through a tranqmi~sion path i5 calculated by Esuation (14).
C(x) = A(x)-x2X2 _ r(x) (14) In the similar r~nn~r~ equations required in circuit formation can be ob~i n~l for arly number of bytes of 'che data signal or any number of byte~ o~ the red~lnA~cy signal and e~en if the ~lock compri~e~ any other unit than byte.
Now, the Reed-Solomon encoding de~ice in this embodiment ha~ing the structure according to the abo~e-~entioned principle will be described with reference to a block diagram in Fig. 5.
. _. .. _ . . . ............. .. . . . . _ _ OCT 28 1998 20: 43 81~ 30250 P~GE. 1~
98-10-29;10:38 ;~ c~ ; BELL ;81~350302C0 ~ 19~ 47 .
As illustrated in the figure, the Reed-Solomon enco~;ng device compris~s a signal separati~g circuit 100, a counter 1, selectors 2 and 3, exclusi~e-OR circuits 4 and 5, Galois field multiplication circuits 6 through 1~, exclu~ive-OR circuits 14 through 19, and D flip-flops 20 through 23.
The Reed-Solomon encoding deYice is supplied with an extern~l input signal including clocks and a data signal.
The ~ignal separating circuit 100 is supplied with a single frame (12 byte~) o~ the data ~isnal. In synchronism with the clocks, the sig~al separating circuit 100 distributes the input data ~ignal byte by byte in a ~nnr~r such that one to be a coefficient of a higher-order ~odd-numbered order) term in an input code pol~nomial is allotted to a signal B while another to be a coef~icient of a lower-order (even-nu~bered order) term is allotte~ to a signal A.
~he signal-~ ~ and B are successi~ely outputted from a higher-order one in the corre pon~ing input code poly~om;~l. ~8 will later be d~scri~ed, the signal ~eparating circuit 100 output~ the input data ~ignal as the signals A and B when a count ~alue of the counter 1 i~ bet~een "O" and "5". On the other hand, the ~ignal separating circuit 100 produces "00000000" as the signals A and B when the count ~alue o~ the counter 1 is "6" or "7" as will later be de~cribed.
The co~nter 1 is an octal counter counted up at e~ery clock input.
The selector 2 i~ responsive to the count ~alue of the counter 1 and selects as an output either the ~ignal A ~hich is the external input signal or a signal C ~hich i~ an output signal of the D flip-~10p 21. ~he selector 3 is responsi~e OCT 28 1998 20:~8 813~ 0250 PflGE. 19 98-1~-29;10:38 ;~ EL~ :81'350302~0 ~ 20f 47 .
to the count ~alue of the counter 1 an~ selects as an output either the ~ignal ~ which is the extsrn~l input ignal and a s;~n~l D which is an output signal of the D flip-~lop 23.
The selectors 2 and 3 selecta a~ outputs the signals A and B
when the count value of the counter 1 i~ between "0" and "5"
and the ~ignals C and D when the count value of the counter 1 is ll6ll or "7".
For each of the exclu~ OR circuits 4 and 5, the Galoic field multiplication circuits 6 through 13, the exclusive-O~ circuits 14 through 19, and the D flop-flop-~ 20 through 23, eight similar circuits are arranged in parallel in corre~pon~nce to the ~ignal length ~1 byte = 8 bits) of each of the signals A and B. By the exclu~i~e-OR circuits 4 and 5, the Galois field multiplication circuits 6 through 13, the exclusi~e-OR circuits 14 through 19, and the D flop-flopc 20 through 23, the r~ ~in~e~ r ~x) de~cribed in conjunction with the abo~e-mentioned principle is calculated.
The e~clusi~e-OR circuit 4 exocute~ an exclusive OR
operation upon the signals A and C (output signal of the D
flip-flop 211 to produce an output signal which is supplied to the Galois field multiplication ci~cuits 6 through 9. ~he exclu~i~e-OR circuit 5 executes an exclusiYe OR operation upon the si~n~ls B and D (output signal of the D flip-flop 23) per bit to produce an outp~t ~ignal which is supplied to the Galois field multiplication circuits 10 through 13. The operation in each of the exclusive-OR circuit~ 4 and 5 corresponds to addition of the Galois fields.
The multipliers in the Galois field multiplication circ~its 6 through 9 are calculated ~rom coefficients of the OCT 28 1998 20:~9 81~030250 P~GE.2 9a-lO-29 lO:3~ BE~L ;8l~,350302CO ~ 2l~ 47 generator polyn~ i~l F(Y) given by Equation (5) and are equal to a lo a 81 a 251 and a 76, respecti~elY-The Galoi~ field multiplication circuits 6 through 9multiply the output signal of the exclusi~e-OR circuit 4 by the a~ove-mentioned multipliers to produce output signals.
The multiplie-s in the Galois field multiplication circuits 10 through 13 are calculated from r~;n~e~3 obt~i~e~ by di~iding x5 by the generator polynomial F(x) and are e~ual to a ~6 a 63 ~ 192 and ~165 regpQctivel The Galoi~ field multiplication circuits 10 through 13 multiply the output signal of the exclu3ive-OR circuit 5 by ~he abo~e-~entioned multipliers to produce output signals.
The exclu~ive-OR circuit 14 execute3 an exclusive 0 operation upon the output s~ of the Galois field multiplication circuits 6 and ~0. This correspond3 to addition of the Galois fields. An output ~ignal of the exclusi~e-OR circuit 14 is a coe~ficient of a lo~er-o~der one o~ even-n~ b~red ord~r term~ produced by the operation and is lower in order by four le~els than the coefficient o~ the signal ~. The D flip-flop 20 delays the output signal of the exclusive-OR circuit 14 by one clock tim;ng to prod~ce a delayed output signal. Thus, the coe~ficient-~ and the orde~
a~ the next ~ g (when the count ~alue of the counter 1 proceeds to a next value) are matched with respect to the exclu~i~e-OR circuits 15 and 16.
The exclusive-O~ circuit 15 executes an exclusive OR
operation upon the output signals of the D flip-flop 20 and the Galois ~ield multiplicatio~ circuit 7. The excl~siv~-OR
circuit 16 executes an exclusive OR operation upon the output . _ .. _ . _ . . _, .. , . . . ._ _ OCT 28 1998 20:50 81~ 0~ld230 PRGE.21 98-10-29:10:38 ;i~ ~ffl~ 8ELL ;8l~,350302CO i~ 22i 47 s;~n~1s o~ the exclusi~e-OR circuit 15 and the Galois field multiplication circuit 10. Each of these operations corresponds to the addition of the Galois ~ields. Arl output signal of the exclusive-OR circuit 16 is a coefficient of a h~ r-order one of eYen~nu~bered orde~ terms pro~ by the operation and i9 lower in order by two levels than the coefficient of the signal A.
The D flip-flop 21 delays the output signal of the exclusi~e-OR circuit 16 by one clock timing to produce the 3ignal C which i8 supplied to the selector 2 and the exclusive-OR circ~it 4. ~he signal C corresponds to a ter~
of an order equal to that o~ the ~ignal A produced b~ the ~ignal separating circuit 100 at the ~ame t; i~g. The signal i~ added to the -qignal A by the exclusi~e-OR circuit 4. A
coef~icient of a term produced during the operation is reflected in the operation o~ the coefficient of the term lo~er by two le~el~.
The exclusi~e-OR circuit 17 execute~ an exclusive O~
operation upon the output ~ignals o~ the Galois ~ield multiplication circuits 8 and 12. This correspond~ to addition of the Galois fieldq. An output signal of the exclusive-OR circuit 17 i~ a coefficient of a lower-order one of odd-numbered order terms produced by the operation and is lower in order by ~our levels than the coefficient of the signal B. The D flip-~lop 22 delays the output ~ignal of the exclusive-OR circuit 17 by one clock timing to produce a delayed output ~ignal. Thus, the coefficients and the order~
at the next t; ~ ng ~when the count value of the counter 1 proceeds to a next value) are matched with respect to the OCT 28 1998 20: 5a 813.5~03~25~ PRGE . 22 9~-l0-29:lC:38 ~ BELL ,8l~350302~0 ~ 23~ 47 exclusive-OR circuits 18 and 19.
The exclusi~e-OR circuit 18 executes an exclusive OR
operation upon the output signals of the D flip-flop 22 and the Galois ~ield multiplication circuit 9. The exclusive-OR
circuit 19 executes an exclusi~e OR operation upon the output signals of the exclusive-OR circuit 18 a~d the Galois ~ield multiplication circuit 13. Each ~f these ope~ation~
corresponds to the addition o~ th~ Galois fields. An output signal of the exclusive-O~ circuit 19 i~ a coefficient of a higher-order one of odd-numbered order term~ produced by the operation and is lower in order by two levels than the coefficient o~ the si~nal B.
The D flip-flop 23 delay~ the output ~ignal of the exclus~ve-OR circuit lS ~y one ~locX ti~; n~ to produce the ~;~n~l D ~hich is supplied to the selector 3 and the exclusive-OR ci~cuit 5. The sig~al D corresponds to a term of an order eq~al to that of the signal B produced by the ~ignal separating circuit 100 at the same ~i ;~g. The signal is added to the signal B by the exclusi~e-OR circuit 4. A
coefficient o~ a. term produced during the opsration is reflected in the operat.ion of the coefficient of the ter~
lower by two le~els.
With the above-mentioned structure, the order~ of the output ~ignal~ of the D flip-flops 21 and 23 a~e lo~ered ~y two levels at a time. Those having th~ ~econd and the third order~ when the counter 1 ~as a value ~l6~l are changed into zeroth-order and first-order one~, re~pectively, when the counter 1 has a value "7~'. Thus, the output ~ignals produced b~ the D ~lip-flops 21 and 23 when the counter 1 has the OCT 28 1998 20:51 81~030~50 P~GE.23 s~-la-2s;l0 38 ~ ~ EL~ 3s~302'o ~ 24~ 47 ~alue of 1'6" and l'7'' are the coeffi~ients of the respecti~e terms of the ~ n~er r(x).
Each of the D flip-flop~ 20 through 23 is cleared a~
the output timing o~ the dat~ signal in the next frame, i.e., at the time instant when the count ~alue of the counter 1 ret~rns from "7" to "0~'.
No~, de~cription will be ~ade about an operation of the Reed-Solomon'encoding device o~ this embodiment.
In synchronism with ~e clock~, i.e., in synchronism with the output t;mi n~ of ~he signals ~ and B from the signal separating circuit 100, the counter 1 successi~ely counts "0 to ~'7". Herein, the signal ~eparating circuit 100 iq already supplied with the data signal of a single f~ame (12 bytes).
When the value of the counter 1 return~ from "7" to "0" ~ollowing the input of the clock~, the D flip-flops 20 through 23 are cleared. Simultaneously, the ~ignal separating circuit 100 produce~, a-q the signals B and ~, coefficient~ al5 and al4 of fifteenth-order and fourteenth-order terms of the product (fi~teenth-order polyno~ial) obtained by multiplying the input code polynomial A(x) correQponding to the data signal by x2X2, respectively.
~ erein, each of the D ~lip-flop~ 2~ through 23 i9 cleared and therefore does not affect the operation at the exclu~i~e-OR circuits 15, 18, ~, and 5. The exclusive-O~
ci~cuits 4 and 5 produce the signal~ A and B as they are, respecti~ely.
A polynomial a~ a result of di~iding the polynomial corresponding to the signals A and B by the generator polynomial F(x) compri~es thirteenth-order to tenth-order OCT 28 1998 20: 52 81~ 31~250 P~GE. 24 . .
98-lC-29'10:38 ~ c~ ELL ,81~35G302~G ~ ~, 4/
term-~.
The coefficient of the thirteenth-order term i~
calculated by the Galois field multiplication circuit~ 9 and 13 and the exclu~ive-OR circuit~ 18 and 19 and supplied to the D flip-flop 23. The coef~i cient of the t~elfth-order term i9 calculated by the Galois field multiplication circuit~ 7 and 11 and the exclusi~e-O~ circuits lS and 16 and supplied to the D flip-~lop 23. T~e coe~ficient of the ele~enth-order term i~ calculated by the Galois field multiplication circuits 8 and 12 and t~e exclusi~e-OR cixcuit 17 and supplied to the D flip-flop 21. The coefficient of the tenth-order term i~ calculated by the Galoi~ field multiplication circuits 6 and 7 and the exclu~ive-OR circuit 14 and supplied to the D ~lip-flop 20.
Next, when the counter has the value 'l2ll, the signal separating circuit 100 outputs, a~ the ~ignals B and A, the coef~icients a13 and a14 o~ thirteenth-order and fourteenth-order term~ of a product (fifteenth-order polyno:~~l) obtained by multiplying thc input code polync i~l A(x) corre~ponding to the data signal by x , re3pectively.
Herein, the D flip-flops 20 through 23 output the coef~icients of tenth-order to thirteenth-order terms of the poly~o~ia~ produced by the operation when the counter 1 ha~
the value l'2".
The exclusive-OR circuit 5 add~ thn coefficient al3 of the thirteenth-order term of the product obtained by multiplying the input code polynomial A (x) hy x and the coe~ficient of the thirteenth-order term calculated at the prec~in~ 1j~in~. The exclusi~re-OR circuit 4 add~ the OCT 28 1998 20:52 81~030250 P~GE.25 _, . . .
9~-10-29,10:38 ~ ?; BELL ,81~350302CO t; 26~ 47 . , .
coefficient al2 of the twelfth-order term of the product o~tained by multiplying the input code polynomial A~x) by x and the coe~ficient of the twel~th-order term calculated at the preceding t;~; ng, A polynomial as a result of di~iding the polynomial correspon~;ng to the ~ ls produced by the exclusive-OR
circuits 4 and 5 by the generator polynomial F~x) comprises eleventh-order to eighth-order terms.
The coefficient of the ele~enth-order term i~
calculated ~y the Galois field multiplication circuit~ 9 and 13 and the exclu~i~e-OR circuit 19 and i9 added by the exclusive-O~ circuit 18 to the coefficient o~ the eleventh-order term produced when the counter 1 has the v~lue "0" to ~e supplied to the D flip-flop 23. The coe~ficient o~ the tenth-o~der term i9 calculated by the Galois ~ield multiplication circuit-~ 7 and 11 and the exclusive-OR
circuits 15 and 16 and is added by the exclusive-OR circuit 15 to the coefficient of the tenth-order term produced when the counter 1 has the ~alue "0" to be supplied to the D flip-flop 23. The coefficient of the ninth-order term iR
calculated by the Galoi-~ field multiplication circuit5 8 and 12 and the exclusive-OR circuit 17 and supplied to the D
flip-flop 21. The coefficient of the eighth-order term is calculated by the Galois ~ield multiplication circuit~ 6 and 7 and the exclu~ive-OR circuit 14 and is supplied to the D
flip-flop 20.
Subsequently, similar calculation is repeated. Upon calculation when the counte~ 1 has the ~al~e "5", the D flip-~lops 20 through 23 are ~upplied with the coefficients of the OCT 28 1998 20: 53 81~032252 P~GE . 26 98-l0-29;l0:3~ h~ ELL ;~l~350302~0 ~ 27~ ~7 third-order to the zeroth-order terms.
When the counter 1 has the value between ll~'' and ~l5'', the selectors 2 and 3 select the signals A and B for output aY the coefficients of the respective terms of the polynomial obt~;ne~ by multiplying the input code polynom;~ A(x) by x2x2 ~
When the counter 1 has the value ~6", the exclusive-OR
circuits 4 and 5 output the coefficients o* the second-order and the third-order terss supplied to the D flip-flops 21 and 23 when the counter 1 ha~ the value "5", respecti~ely. At thiQ time, the selector~ 2 and 3 select the signals C and D
for out~ut a~ the coe~ficients of the second-order and the third-order terms of the r~ n~er r(x), re~pecti~ely. When the counter 1 has the value "7", the ~electors 2 and 3 select the signal~ C and D for output as the coefficients of the zeroth-order and the first-order term~ of the r~-;n~r r(x).
Supplied with the data signal of 12 byteq and the redl~d~ signal of ~ bytes outp~tted from the ~electors 2 and 3 by the above-mentioned proces~, a transmission cod~
poly~e~i~l operating circuit (not shown) executes the operation given by Equation (14) to produce a transmission code polynomial C(x). Then, a signal corresponAing to the coef~icientg of the respective terms of the tr~nsmi~sion cod0 polyno~ is deli~ered ~rom the transmission code polynomial operating circuit to a tran~mission line.
As described abo~e, in the Reed-Solomon encodins de~ice of th~s embodiment, the information separating circuit lOO outputs the data signal as the sigmals A and E~
simultaneou~ly by two ~ytes at a time. The two byte signals OCT 28 1998 20: 54 81~0~2~ P~GE. 27 .
9~-1û-29;10:3~ ELL :81.350302C0 ~ 2~ 47 .
are processed in parallel. The re~nA~cy signal is produced by t~o bytes at a time to be outputted. Therefore, Reed-Solomon enco~i ng i~ carried out at a _peed a~ high as t~ice as compared with the co~ tien~l Reed-Solomon encoding device. It i~ therefore possible to process a signal of a twice ~r~r;ty.
In the above-mentioned first embodiment, de~cription has been directed to the ca~e ~here the data ~ignal has twelve byte~ and the re~ ncy sign~1 ha~ four bytes.
However, t~e data -Qignal may ha~e any number o~ bytes up to 252 bytes ~but the number of byte~ must be an e~en number).
In either e~ent, the number of bytes of the red~n~n~y sign~l is equal to 4. The counter 1 is of a ((number of bytes of the data signal ~ 4) . 2)-ary type. For example, when the data signal has 252 ~ytes, the ~electors 2 and 3 output the ~ignal~ A and ~, respecti~ely, when the counter 1 has the value bet~een "O" and "125" and the signal~ C and D when th~
counter 1 haQ the value l'126" or "127".
In the abo~e-mentioned first embodim~nt, description has been directed to the Reed-Solomon encoding circuit for executing Reed-~olomon encoding with an error co~recting func~ion of two bytes. Ho~ever, the error correction function of three byte~ or more can be achieved in the gimi 1 ~r m~nn~r, In this e~ent, the counter 1 i~ of a (~numb~r of bytes o~ the data signal + number of bytes of the re~-~nd~ncy QigTlal) ~ 2)-a~y type The selectors 2 and 3 output the signals C and D when the value of the counter is a (number of byte~ o~ the re~n~ancy signal . 2)-th one ~rom the laRt.
OCT 28 1998 20: 54 81~030250 Pl:~GE. 2e 98-t0-29:10:38 ~ BEL~ ;81~,350302CO $ 29~ 47 , In the above-mentioned fi~st embodiment, de~cription has been made about the case uhere the ~ignal is proce~-~ed by two byte~ in parallel. Howe~er, ~ignal procesqing by three or more bytes in parallel can be achieved in the si~ r manner. It is noted here that, in ca~e of the signal processing by ~ bytes in parallel, J must be a mea~ure of both of the number N of bytes o~ the data signal and the number ~ of byteQ of the re~n~ncy signal. In this case, the Reed-Solomon en~o~;~g device is implemented by a circuit ~tructure aecording to equation_ modified in the ~n~
~imilar to the above-mentioned principle.
In the above-~entioned first embc~ t, a ~ingle block comprise~ one byte (8 bits) in each of the data signal and the re~ c~ signal. However, the single block of data in this i~ention may comprise any desired number of ~its.
In this case, the element~ of the Galois field which correspond to the number of bits of the ~ingle block are used a~ the elementQ of,the input code poly~omi~l A (x) .
[2nd Embodiment~
In the fir~t embodiment, description ha~ been made about the case where the number of byte~ of the data signal can be di~ided without a rem~ er by the num~er of the signals sepa~ated by the signal separating circuit 0. In contrast, this embod~ment is directed to a Reed-Solomon encodin~ circuit in ~hich a dummy byte is added to the data ~ignal so that a total num~er of byte~ can be divided ~ithout a .- -; n~er by the number of ~yte~ of the signals separated by the signal separating circuit 0.
OCT 28 1998 20:55 1 - 81~03~25~ P~GE.25 98~ 29:10:38 ,~ ; BELL 81~350302CO i~ 30~ 47 Fig. 7 is a block diagram sho~ing the structure o~ the Reed-Solomon encoding de~ice according to this embodiment.
As illustrated in the figure, the Reed-Solomon encoding device comprise3 a dum~y byte append~n~ circuit 101 and a ~eed-Solomon encoding circuit 102.
The dummy byte appending circuit 102 appends a dummy byte o~ a single byte to an input data ~ignal in which each single frame comprises 251 byte~, a~d ~upplies the signal to the Reed-Solomon encoding circuit 102. Herein, the dummy byte appended to the data signal by the dummy byte appen~ing circuit 102 is ~IOOOOOOOO~. This dum~y ~yte ser~es as a hjghest-order term in the input code polynomial A(x).
Therefore, the highest-order term ha3 a coefficient equal to "O" ancl i9 not subjected to error correction by a re~ultant Re~d-Solo~ n code.
The Reed-Solomon encoding circuit 102 is ~;~; l~r in structure to the ~eed-Sol~mon encoding device illustrated in Fig. 5. ~owever, the counter 1 is of a (~251 + 4 ~ 1) . 2) = 128-ary type. The selectors 2 and 3 select an~ output the signals from the signal separating circuit O when the counte~
1 ha8 a count value between "O" and "125" and the 3ignals C
and D when the count value i9 ~'125~' or ~126~.
The ~ignal separating eircuit O is supplied ~ith the data signal ha~ing 252 bits in total including the du~my byte of a single byte. The Reed-Solomon encoding circuit 102 carrie~ out proces~ing 8i~ r to that of the ~irst embodime~t. ln this embodiment, ho~ever, the selectors 2 and 3 select and output the ~ignals from the signal separating circuit O when the counter 1 has the count value ~etween "O"
OCT 28 1998 2z:56 81~ 0~ P~GE.32 , .
98-1~-2g:10:38 ~ EL~ ;al.3so302~o ~ 31 and ~125~' and the signals C and D when the count value is 125 or 126.
As described aboYe, the Reed-Solomon encoding de~ice of this embodiment p~oduces the Reed-Solo~on code from the data signal with the dummy byte added thereto. There~ore, even if the number of bytes of the data signal can not be divided without a r~in~r by the number of separated signal~ prod~ced by the qignal separating circuit 0, parallel processing is posqible.
In the second embodiment, de~cription has been made about the case where the data ~;gn~l i5 ~eparated by the signal separating circuit O into two for parallel processing.
It is noted here that prod~ction of the Reed-Solomon code with the dummy byte added to the data signal is also applicable to the case where t~e ~ r of the separated -~ignal~ deri~ed from the data signal i~ e~ual to three or more. For example, i~ the data ~ignal o~ N byte~ i~
separated into every J bytes ~or parallel proce~si~g, the dummy byte~ of I bytes are added ~here ~N + I) i~ a measure of J ~I ~ J).
A~ described above, according to thi9 invention, the data signal i~ proce~ed by J blocks at a time in parallel to produce the re~l~n~cy signal by J blocks at a time.
There~ore, as compared with the con~entio~al Reed-Solomon encoding de~ice, high-speed proceqsing aq high as J time~ can be carried out. In this Reed-Solomon encoding device, an~
desired nllmber can be selected as the number N o~ the blocks of the re~ cy signaI as ~ar as a predet~r~ned condition i~ m0t. Therefore, it is possible to produce the Reed-OCT 28 1998 20: 56 81~ a25~ P~GE . 31 9~-10-29:10:3~ e~ BELL al3350302C0 ~ 32~ 47 Solomon code pen~itting multiple error correctiorl.
An auxiliary signal of I blocks is added to the data ~ignal of N blocks and the redundancy ~ignal i9 produced for t~e data -c~ignal ha~ring (N + I) block~ in total with the Yi ~ ry signal added. l'here~ore, e-ren if ~ can not be di~ided by ~ ~ithout a ro-~in~e~, it iQ po~ible to perform Reed-Solomon encoding by parallel processing.
. . . _ _,,, , , ,, I _, , , ,, - . _ OCT 28 199~1 20:56 el~ 225~ PRGE.32
Claims (13)
1. A Reed-Solomon encoding device which is supplied with an input signal containing N data signal blocks in each single frame for carrying out a division of dividing by a generator polynomial a polynomial corresponding to said input data signal to produce K redundancy signal blocks corresponding to a remainder obtained by said division and which comprises:
signal output means for outputting said N data signal blocks by J blocks at a time in a time division fashion successively from those corresponding to higher orders in said corresponding polynomial;
adder means, J in number, for calculating, with respect to J data signal blocks outputted from said signal output means and J calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted from said signal output means at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other;
operating means, J in number, responsive to J sum blocks calculated by said J adder means, respectively, for carrying out the predetermined operation to produce said J
calculated blocks which correspond to orders lower by J
levels than those of said J sum blocks calculated by said J
adder means, respectively, and which are supplied to said J
adder means, respectively; and selective output means, J in number, for outputting (N
~ J) times J data signal blocks supplied from said signal output means and subsequently outputting (K~J) times J
calculated blocks produced by said J operating means;
N, K, and J being natural numbers where J is a measure of both of N and K.
signal output means for outputting said N data signal blocks by J blocks at a time in a time division fashion successively from those corresponding to higher orders in said corresponding polynomial;
adder means, J in number, for calculating, with respect to J data signal blocks outputted from said signal output means and J calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted from said signal output means at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other;
operating means, J in number, responsive to J sum blocks calculated by said J adder means, respectively, for carrying out the predetermined operation to produce said J
calculated blocks which correspond to orders lower by J
levels than those of said J sum blocks calculated by said J
adder means, respectively, and which are supplied to said J
adder means, respectively; and selective output means, J in number, for outputting (N
~ J) times J data signal blocks supplied from said signal output means and subsequently outputting (K~J) times J
calculated blocks produced by said J operating means;
N, K, and J being natural numbers where J is a measure of both of N and K.
2. A Reed-Solomon encoding device as claimed in claim 1, further comprising:
((N + K) ~ J)-ary counting means for counting up at an interval equal to that of output timings of said data signal blocks from said signal output means;
said J selective output means successively outputting J data signal blocks supplied from said signal output means when the count value or said counting means is between 0 and (N ~ J - 1) and successively outputting J calculated blocks produced by said J operating means when the count value of said counting means is between (N ~ J) and ((N + K) ~ J - 1).
((N + K) ~ J)-ary counting means for counting up at an interval equal to that of output timings of said data signal blocks from said signal output means;
said J selective output means successively outputting J data signal blocks supplied from said signal output means when the count value or said counting means is between 0 and (N ~ J - 1) and successively outputting J calculated blocks produced by said J operating means when the count value of said counting means is between (N ~ J) and ((N + K) ~ J - 1).
3. A Reed-Solomon encoding device as claimed in claim 1, wherein:
each of said J operating means executes the predetermined operation upon coefficients of such terms in the corresponding polynomial that remainders equal to one another are produced when their orders are divided by J;
each of said J adder means calculating, with respect to said calculated blocks as a result of the operation by said J operating means and said J data signal blocks outputted from said signal output means, a sum of a pair of said calculated and said data signal blocks equal in their orders in the corresponding polynomial to each other.
each of said J operating means executes the predetermined operation upon coefficients of such terms in the corresponding polynomial that remainders equal to one another are produced when their orders are divided by J;
each of said J adder means calculating, with respect to said calculated blocks as a result of the operation by said J operating means and said J data signal blocks outputted from said signal output means, a sum of a pair of said calculated and said data signal blocks equal in their orders in the corresponding polynomial to each other.
4. A Reed-Solomon encoding device as claimed in claim 3, wherein:
each of said J operating means comprises receiving means for receiving another calculated block which corresponds to the order of said calculated block calculated by this operating means and which is produced as a result of the operation by any operating means other than this operating means, and operating means for carrying out the predetermined operation by the use of the above-mentioned another calculated block received by said receiving means.
each of said J operating means comprises receiving means for receiving another calculated block which corresponds to the order of said calculated block calculated by this operating means and which is produced as a result of the operation by any operating means other than this operating means, and operating means for carrying out the predetermined operation by the use of the above-mentioned another calculated block received by said receiving means.
5. A Reed-Solomon encoding device as claimed in claim 1, wherein:
said signal output means produces a bit string of "0"
when said J selective output means output said J sum blocks as a result of the addition by said J adder means.
said signal output means produces a bit string of "0"
when said J selective output means output said J sum blocks as a result of the addition by said J adder means.
6. A Reed-Solomon encoding device which is supplied with an input signal containing N data signal blocks in each single frame for carrying out a division of dividing by a generator polynomial a polynomial corresponding to said input data signal to produce K redundancy signal blocks corresponding to a remainder obtained by said division and which comprises:
auxiliary block appending means for appending I
auxiliary block to said N data signal blocks;
signal output means for outputting the (N + I) data signal blocks, including said auxiliary blocks appended by said auxiliary block appending means, by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
adder means, J in number, for calculating, with respect to J data signal blocks outputted from said signal output means and J calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted from said signal output means at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other;
operating means, J in number, responsive to J sum blocks calculated by said J adder means, respectively, for carrying out the predetermined operation to produce said J
calculated blocks which correspond to orders lower by J
levels than those of said J sum blocks calculated by said J
adder means, respectively, and which are supplied to said J
adder means, respectively; and selective output means, J in number, for outputting ((N ~I) ~ J) times J data signal blocks supplied from said signal output means and subsequently outputting (K ~ J) times J calculated blocks produced by said J operating means;
N, K, J, and I being natural numbers where J is a measure of both of (N ~ 1) and K.
auxiliary block appending means for appending I
auxiliary block to said N data signal blocks;
signal output means for outputting the (N + I) data signal blocks, including said auxiliary blocks appended by said auxiliary block appending means, by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
adder means, J in number, for calculating, with respect to J data signal blocks outputted from said signal output means and J calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted from said signal output means at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other;
operating means, J in number, responsive to J sum blocks calculated by said J adder means, respectively, for carrying out the predetermined operation to produce said J
calculated blocks which correspond to orders lower by J
levels than those of said J sum blocks calculated by said J
adder means, respectively, and which are supplied to said J
adder means, respectively; and selective output means, J in number, for outputting ((N ~I) ~ J) times J data signal blocks supplied from said signal output means and subsequently outputting (K ~ J) times J calculated blocks produced by said J operating means;
N, K, J, and I being natural numbers where J is a measure of both of (N ~ 1) and K.
7. A Reed-Solomon encoding device as claimed in claim 6, further comprising:
((N ~ X) ~ J)-ary counting means for counting up at an interval equal to that of output timings of said data signal blocks from said signal output means;
said J selective output means successively outputting J data signal blocks supplied from said signal output means when the count value of said counting means is between 0 and ((N + I) ~ J - 1) and successively outputting J calculated blocks produced by said J operating means when the count value of said counting means is between ((N + I) ~ J) and ((N + I + K) ~ J - 1).
((N ~ X) ~ J)-ary counting means for counting up at an interval equal to that of output timings of said data signal blocks from said signal output means;
said J selective output means successively outputting J data signal blocks supplied from said signal output means when the count value of said counting means is between 0 and ((N + I) ~ J - 1) and successively outputting J calculated blocks produced by said J operating means when the count value of said counting means is between ((N + I) ~ J) and ((N + I + K) ~ J - 1).
8. A Reed-Solomon encoding device as claimed in claim 6, wherein:
each of said I auxiliary blocks comprises a bit string of "0";
said signal output means at first outputting said I
auxiliary blocks as higher-order ones than said N data signal blocks.
each of said I auxiliary blocks comprises a bit string of "0";
said signal output means at first outputting said I
auxiliary blocks as higher-order ones than said N data signal blocks.
9. A Reed-Solomon encoding device as claimed in claim 6, wherein:
each of said J operating means executes the predetermined operation upon coefficients of such terms in the corresponding polynomial that remainders equal to one another are produced when their orders are divided by J;
each of said J adder means calculating, with respect to said calculated blocks as a result of the operation by said J operating means and said J data signal blocks outputted from said signal output means, a sum of a pair of said calculated and said data signal blocks equal in their orders in the corresponding polynomial to each other.
each of said J operating means executes the predetermined operation upon coefficients of such terms in the corresponding polynomial that remainders equal to one another are produced when their orders are divided by J;
each of said J adder means calculating, with respect to said calculated blocks as a result of the operation by said J operating means and said J data signal blocks outputted from said signal output means, a sum of a pair of said calculated and said data signal blocks equal in their orders in the corresponding polynomial to each other.
10. A Reed-Solomon encoding device as claimed in claim 9, wherein:
each of said J operating means comprises receiving means for receiving another calculated block which corresponds to the order of said calculated block calculated by this operating means and which is produced as a result of the operation by any operating means other than this operating means, and operating means for carrying out the predetermined operation by the use of the above-mentioned another calculated block received by said receiving means.
each of said J operating means comprises receiving means for receiving another calculated block which corresponds to the order of said calculated block calculated by this operating means and which is produced as a result of the operation by any operating means other than this operating means, and operating means for carrying out the predetermined operation by the use of the above-mentioned another calculated block received by said receiving means.
11. A Reed-Solomon encoding device as claimed in claim 6, wherein:
said signal output means produces a bit string of "0"
when said J selective output means output said J sum blocks as a result of the addition by said J adder means.
said signal output means produces a bit string of "0"
when said J selective output means output said J sum blocks as a result of the addition by said J adder means.
12. A Reed-Solomon encoding method which is supplied with an input signal containing N data signal blocks in each single frame for carrying out a division of dividing by a generator polynomial a polynomial corresponding to said input data signal to produce K redundancy signal blocks corresponding to a remainder obtained by said division;
said method comprising:
a signal output step of outputting said N data signal blocks by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
an adding step of calculating, with respect to J data signal blocks outputted in said signal output step and J
calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted in said signal output step at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in response to said J sum blocks calculated in said adding step, the predetermined operation to produce said J calculated blocks which correspond to orders lower by J levels than those of said sum blocks calculated in said adding step and which are respectively added in said adding step at a next timing;
N, K, and J being natural numbers where J is a measure of both of N and K.
said method comprising:
a signal output step of outputting said N data signal blocks by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
an adding step of calculating, with respect to J data signal blocks outputted in said signal output step and J
calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted in said signal output step at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in response to said J sum blocks calculated in said adding step, the predetermined operation to produce said J calculated blocks which correspond to orders lower by J levels than those of said sum blocks calculated in said adding step and which are respectively added in said adding step at a next timing;
N, K, and J being natural numbers where J is a measure of both of N and K.
13. A Reed-Solomon encoding method which is supplied with an input signal containing N data signal blocks in each single frame for carrying out a division of dividing by a generator polynomial a polynomial corresponding to said input data signal to produce K redundancy signal blocks corresponding to a remainder obtained by said division;
said method comprising:
an auxiliary signal appending step of appending I
auxiliary blocks to said N data signal blocks;
a signal output step of outputting the (N + I) data signal blocks, including said auxiliary blocks appended in said auxiliary signal appending step, by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
an adding step of calculating, with respect to J data signal blocks outputted in said signal output step and J
calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted in said signal output step at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in response to said J sum blocks calculated in said adding step, the predetermined operation to produce said J calculated blocks which correspond to orders lower by J levels than those of said sum blocks calculated in said adding step and which are respectively added in said adding step at a next timing;
N, K, J, and I being natural numbers where J is a measure of both of (N + I) and K.
said method comprising:
an auxiliary signal appending step of appending I
auxiliary blocks to said N data signal blocks;
a signal output step of outputting the (N + I) data signal blocks, including said auxiliary blocks appended in said auxiliary signal appending step, by J blocks at a time in a time division fashion successively from those corresponding to higher orders in the corresponding polynomial;
an adding step of calculating, with respect to J data signal blocks outputted in said signal output step and J
calculated blocks obtained by a predetermined operation based upon J preceding data signal blocks outputted in said signal output step at a preceding timing, a sum of a pair of said data signal and said calculated blocks corresponding in their orders to each other to produce J sum blocks; and an operating step of carrying out, in response to said J sum blocks calculated in said adding step, the predetermined operation to produce said J calculated blocks which correspond to orders lower by J levels than those of said sum blocks calculated in said adding step and which are respectively added in said adding step at a next timing;
N, K, J, and I being natural numbers where J is a measure of both of (N + I) and K.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9296966A JPH11136136A (en) | 1997-10-29 | 1997-10-29 | Reed solomon coding device and method |
| JP296966/1997 | 1997-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2252182A1 CA2252182A1 (en) | 1999-04-29 |
| CA2252182C true CA2252182C (en) | 2002-04-30 |
Family
ID=17840513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002252182A Expired - Fee Related CA2252182C (en) | 1997-10-29 | 1998-10-29 | Device and method for carrying out reed-solomon encoding |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6219816B1 (en) |
| EP (1) | EP0913949A3 (en) |
| JP (1) | JPH11136136A (en) |
| CA (1) | CA2252182C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3351413B2 (en) | 2000-03-01 | 2002-11-25 | 日本電気株式会社 | Parallel processing Reed-Solomon encoding circuit and parallel processing Reed-Solomon encoding method used therefor |
| KR100361033B1 (en) * | 2001-01-16 | 2003-01-24 | 한국과학기술원 | Multicarrier DS/CDMA system using a turbo code with nonuniform repetition coding |
| US6826723B2 (en) * | 2001-05-09 | 2004-11-30 | Agere Systems Inc. | Multi-rate reed-solomon encoders |
| JP2003032122A (en) * | 2001-07-18 | 2003-01-31 | Nec Eng Ltd | Encoder |
| US7146391B2 (en) * | 2002-01-24 | 2006-12-05 | Broadcom Corporation | Method and system for implementing SLICE instructions |
| US7082564B2 (en) * | 2002-09-23 | 2006-07-25 | Agere Systems Inc. | High throughput Reed-Solomon encoder |
| TWI226758B (en) * | 2003-11-28 | 2005-01-11 | Mediatek Inc | Encoding method and apparatus for cross interleaved cyclic codes |
| CN1922797A (en) * | 2004-03-18 | 2007-02-28 | 三星电子株式会社 | Method and apparatus for transmitting and receiving broadcast data using outer-coding in a mobile communication system |
| US7729384B1 (en) * | 2005-11-01 | 2010-06-01 | Metanoia Technologies, Inc. | Multiple channel digital subscriber line framer/deframer system and method |
| KR100733963B1 (en) | 2005-11-09 | 2007-06-29 | 한국전자통신연구원 | Apparatus and method for Reed-Solomon Decoder through High Error Correction Capability |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4413339A (en) * | 1981-06-24 | 1983-11-01 | Digital Equipment Corporation | Multiple error detecting and correcting system employing Reed-Solomon codes |
| JPS59226951A (en) | 1983-06-09 | 1984-12-20 | Sony Corp | Coding device of read solomon code |
| JPS6073752A (en) | 1983-09-29 | 1985-04-25 | Sony Corp | Parity generating circuit of two-error reed solomon code |
| US4555784A (en) * | 1984-03-05 | 1985-11-26 | Ampex Corporation | Parity and syndrome generation for error detection and correction in digital communication systems |
| US4998252A (en) * | 1987-08-06 | 1991-03-05 | Sony Corporation | Method and apparatus for transmitting digital data |
| DE4140018A1 (en) * | 1991-12-04 | 1993-06-09 | Bts Broadcast Television Systems Gmbh, 6100 Darmstadt, De | METHOD AND CIRCUIT FOR DECODING RS-CODED DATA SIGNALS |
| US5471485A (en) * | 1992-11-24 | 1995-11-28 | Lsi Logic Corporation | Reed-solomon decoder using discrete time delay in power sum computation |
| JPH0774655A (en) * | 1993-09-03 | 1995-03-17 | Toshiba Corp | Error correction encoding device |
| US5699368A (en) * | 1994-03-25 | 1997-12-16 | Mitsubishi Denki Kabushiki Kaisha | Error-correcting encoder, error-correcting decoder, and data transmitting system with error-correcting codes |
| EP0684712B1 (en) * | 1994-05-17 | 2005-05-04 | Nippon Telegraph And Telephone Corporation | Line terminating equipment in SDH networks, using forward error correcting codes |
| US5757826A (en) | 1995-07-12 | 1998-05-26 | Quantum Corporation | Word-wise processing for reed-solomon codes |
| US6079041A (en) * | 1995-08-04 | 2000-06-20 | Sanyo Electric Co., Ltd. | Digital modulation circuit and digital demodulation circuit |
| US5754563A (en) * | 1995-09-11 | 1998-05-19 | Ecc Technologies, Inc. | Byte-parallel system for implementing reed-solomon error-correcting codes |
| AU4064697A (en) * | 1996-08-15 | 1998-03-06 | Quantum Corporation | Parallel input ecc encoder and associated method of remainder computation |
| US5883907A (en) * | 1997-05-01 | 1999-03-16 | Motorola, Inc. | Asymmetrical digital subscriber line (ADSL) block encoder circuit and method of operation |
| US5943348A (en) * | 1997-10-14 | 1999-08-24 | Lsi Logic Corporation | Method to check for burst limiting in error correcting systems |
-
1997
- 1997-10-29 JP JP9296966A patent/JPH11136136A/en active Pending
-
1998
- 1998-10-29 US US09/181,650 patent/US6219816B1/en not_active Expired - Lifetime
- 1998-10-29 CA CA002252182A patent/CA2252182C/en not_active Expired - Fee Related
- 1998-10-29 EP EP98120190A patent/EP0913949A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0913949A2 (en) | 1999-05-06 |
| US6219816B1 (en) | 2001-04-17 |
| CA2252182A1 (en) | 1999-04-29 |
| JPH11136136A (en) | 1999-05-21 |
| EP0913949A3 (en) | 2004-10-06 |
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