CA2124855A1 - A real-time running averaging device - Google Patents
A real-time running averaging deviceInfo
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- CA2124855A1 CA2124855A1 CA002124855A CA2124855A CA2124855A1 CA 2124855 A1 CA2124855 A1 CA 2124855A1 CA 002124855 A CA002124855 A CA 002124855A CA 2124855 A CA2124855 A CA 2124855A CA 2124855 A1 CA2124855 A1 CA 2124855A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/18—Complex mathematical operations for evaluating statistical data, e.g. average values, frequency distributions, probability functions, regression analysis
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Abstract
A real-time signal averaging circuit (120) is disclosed. The averaging circuit includes a signal input port (112) for receiving an input signal (130); the input signal representing a value xn which is to be averaged by the averaging circuit. The averaging circuit uses a register (122) for temporarily storing and updating a previous average value ap which was output from the averaging circuit. An averaging circuit is connected to the signal input port and the register. The averaging circuit provides a weighted average value an of the value xn represented by the input signal and of the previous average value ap stored in the register.
The average value an is defined as the sum ((M-1)ap + xn) divided by M, where M is a predetermined positive number greater than 1. The averaging circuit provides to the register the average value an. Finally, the circuit includes an output port (114) for generating an output signal representing the average value an. The output signalling port is connected to the averaging circuit. A clock (110) generates the necessary timing signals.
The average value an is defined as the sum ((M-1)ap + xn) divided by M, where M is a predetermined positive number greater than 1. The averaging circuit provides to the register the average value an. Finally, the circuit includes an output port (114) for generating an output signal representing the average value an. The output signalling port is connected to the averaging circuit. A clock (110) generates the necessary timing signals.
Description
2 1 2 4 8 5 $ PCr/US92/08242 A REAL~T~IVIE RUNNING AVERAGING DEVICE :
F;eld of lhe lnvention The present invention relates to real-time devices, and more specifically to real-time devices for calculating an average of values represented by a signal.
....
Back~round of the Invention `
Mobile radio (electronic) devices often are required to adapt to ; ~ -changes in the;r environment or to vary the output which they are to produce in a nearly instantaneous manner. This has led to an increased reliance upon real-time evaluation of diata representing physical quantities.~ "Real-time" here refers to the fact thal the~ evaluation is performed at essendally ;the same dme as the data is acquired. ~ Real-time systems t~pically require very rapid processing of data as th8 ~ ~
data is obtaine~. Non-real-time evaluation occurs at some time long after the data is ~ ~ .
obtained. For example, when a mobile unit is requesting a service, a response from ~ ;
2 0 the system to the mobile unit takes a long time; the time lag in processing the data ; can cause the results to be obsolete by ~tho time those results are obtained.
The information processin~ limitations of the electronic hardware involved with a particular devico~help~determine the operational capaclty~and~
2;5 ~ ; ma~rm~ um processing speed~ of that devlce. Hence ~minimizadon of hardware complexity and increases in hardware response time are cIitical to evaluation of data for those applîcations.
: ~: : ~ .
Oné~ example of such a~ time-itical appDcation is found in the field of 3 0 ~ ~ ~ cellular telephones. Cellular mobile t~lephones (mobile units~ must receive si~nals broadcast from the cell site transmitters. The mobile telephones are often themselves : ~
WO 93/l t482 2 1 2 ~ Pcr/US92/082 in motion. This motion leads to chan~es in the strength of the signals received by the mobile unit. Cellular telephone networks attempt to maintain an acceptable ;
signal level at each site, and switch the signal to a new cell when the average signal received from the mobile unit becomes weak, i.e. below the acceptable level. This switching may be accomplished by comparing the intensity of the average value of-.~ ....
the signals from different cells and selecting that signal which is strongest. ~ ~
: .. : :
Determination of the avera~e value is presently accomplished in the following manner. The receiver measures the signal intensity at a number of points, I
for example twenty, and stores these values in a memory. The values are then added and the sum is divided by the number of stored values. This yields the mean (average) value of tne signal intensity. Typically, the next average is obtained by discarding the oldest stored value, replacing it with a new value, and performing the averaging computations just described. This leads to a smoother transition of the -computed averagle over time, and utilizes a fixed memory capacity.
This method is not ideal for real-time operations such as are used in cellular telephone systems. It requires memory devices for storing these values to be -averaged. This complicates the hardware of the system and slows the averaging 2 0 process. More importantly, it yields the average value as of the moment that is halfway between the newest and the oldest data value. In the example given above, the average value represents the value at the time midway between the 10th and 11th data value. Thus if instantaneous data were being sampled once every second, theaverage obtained is actually the~ average value as of a point in time ten seconds prior 2 5 to the most recent data value measured. This does not include the delay caused by actually performing the calculations themselves.
This physical delay is a serious problem for cellular telephone networks. In~ addition, the lag in the computed average value is large enough toadversely affect the reliability of the comparisons based upon those averages, which '' ;." ~
Wo 93/1 1482 2 1 2 4 ~ 5 ~ PCr/US92/08242 ~ ~
are not valid for use for real-time comparisons among them. This lag increases as the number of points sampled increases. Thus the more precise the average, the older it is and thus less reliable. This is only compensated for by increasing the sampling rate of the device, which often is accompanied by seYere increases in cost. - -S ' It would therefore be desirable to perform an averaging which yields a more timely result, and one which minimizes the hardware complexity of the average processing device. Also, while the example given relates to cellular telephone networks, it is clear that similar problems may arise in a variety of applications which involve real-time averaging of data to smooth out fluctuations.
Broadly, it is an object of the present invention to provide an improved real-time signal averaging device.
It is a further object of the present invention to provide a real-time si~nal averagin,g circuit which generates an output which represents the average value of data at a time close to the time at which the new data are obtained.
It is a still further object of the present invention to provide a real-time signal averaging circuit which requires no memory hardware.
These and other objects of the present invention will be apparent to those skilled in ~the art from the following detailed description of the invention and the accompanying drawings.
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Sumrnarv of the Invent_n ~ -", The present invention comprises a real-time signal averaging circuit. - ;
The averaging circuit includes clock means for generating timing signals. The averaging circuit also includes signal input means for receiving an input signal. The . . ... ~
input signal represents a value xn which is to be averaged by the averaging circuit~ ~ ;
The averaging circuit further includes register means for temporarily storing and updating a previous avera~e value ap which was output from the averaging circuit.
Averaging means are connected to the clock means, the signal input means and theregister means~ 1~e avera~ing means provides in response to the timing signals aweighted average value an of the value xn represented by the input signal and of the previous average value ap stored in ehe register means~ The average value an is defined as the surn ((M-l)ap ~ xn) divided by M, where M is a predetermined positive number greater than l. The averaging means provides to the register means the average value an. Finally, the circuit includes output signalling means for generating an output signal representing the average value an. The output signalling means is connected to said averaging means.
; 20 Alternative embodiments are disclosed for circuits in which the value is represented digitally, wherein the register means is n digital data regis~er, and in which~the value is represented by an analog amplitude, wherein the register means is ~ . .
~a sarnple and hold~ device, Also, in the preferred embodiment of the present invention, the previous alue ~ is the Immediately previous nvernge value n ~
The present invention also includes a method of producing an average value of a signal in real-time. The method includes obtaining timing signals from a clock means. Next a previous average value a" l is input into a register means. An input signal representing a value X" to be averaged is then received. Then a weighted . ~ , -~ WO93~ 82 2~2~8S~ Pcr/us92/08242 ~ ~
average value an of the previous average value a" l and the value xn represented by said input signal is provided in response to the siming signals. The weighted average value a" is defined as the sum ((M-l)aD.I + xn)) divided by M, where M is a predetermined positive number greater than 1. Finally an output signal is generated representing the weighted average value an.
: ' As for the circuit described above, there are corresponding al~ernative implementations of the present method. The value may be represented digitally, in which case the register means is again a digital register, or an analog ma~nitude 1 0 device.
Brief DescriDtion of the Drawil os :
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F'igure 1 illustrates a signal being sampled at discrete points separated by uniform time intervals.
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Figure 2 is a flow chart illustrating the preferred implementation of the 2 0 method of the present invention.
Figure 3 is a block diagram representation of an implementation of an averaging circult according to the present invention. ;:
Figure 4 is a schematic diagram of a circuit according to the present invention for averaging digital signals. `-~
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Figure 5 is a schematic diagrarn of a circuit according to the present invention for averaging analog signals.
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Figure 6 is a block diagram representation of a comparison circuit according to the present invention. ~-Figure 7 is a schematic diagram of a circuit ; ~
according to the present invention fox comparing the ~;
5 averaging values of a plurality of digital signals. ~;
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Detailed DescriPtion of the Invention The advantages provided by the present invention are best understood in light of the prior art method.
Therefore a brief explanation of the method of the prior art is required. A signal to be averaged is sampled at regular intervals. The times at which these samples were obtained are referred to as tol tl,...tn, where there are n~l data points sampled. The values of these dàta points are denoted as xO, xl,...~. While these signal values axe said to represent the values to be averaged, this does not mean that there must be an ;~
encoding of external data into signal form. The signal may be inherently characterized by the values to be ;~
averaged.
~te ~ver~ge value ob~ai e by th prior art m tho~ ~
This type of average is referred to as an arithmetic ~:-30 mean, or simply a mean. ~ ~ ~
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; . ~` ~''""",.:'- :`' - - Wo 93/11482 21 2 ~ 8 ~ ~ PCr/US92/08242 Fi~ure 1 illustrates an example of how such a sampling is undertaken.
A signal 1 is shown plotted on a graph, where vertical distance represents the value of the signal and ~he horizontal distance represents time. The labelled circles represent the signal values xO, x" ... sampled at the times to~ tl, .... A specified number of these values are added and the sum is divided by that number of values.
Hence, for lS points, the mean is equal to (xO + x, + ... + X14) /15.
Typically, these n+l values are stored in a memory device. The next subsequent mean would be obtained by discarding xO and replacing it with x,~+,. The summation would then be performed by summing the values xl to x"+,. This allows ~-for summation using a continuing adding process using an adder and with a memoryfor storing the n+l most recent values. Such a procedure, utilized for each timesampled, acts to smooth out the values of the means thus obtained. This helps eliminate noise ~md minimizes the possibility of dramatic swings in the average values obtained by the procedure.
It should be noted that the term "memory" is used herein to describe ` ~;
devices for storage of values which are to be statically maintained during the calculation of several avera~e value. In the specific example given above each memory location retains its value for lS average value calculations. This is where the data itself is stored. The term "register", by contrast, is used herein to describe devices for stora~e of values which are to be maintained only until used a single - : ~
time, and then are replaced with a new value. Re~isters would be used to ~ -~ ternporarily store data until it is utilized and replaced durin~ the next average~value 2 5 calculation.
The method described above may be better understood by again referring to Figure l. A first set 4 of 15 data points which are averaged at time tl4 is shown. Also, a second set 5 of lS data points which are averaged at time tl5. Since 3 0 the processor only looks at n+l points out of many that have been taken, it is said . .. ... -.
wo 93/11482 ~12 ~ 8 5 ~ Pcr/uss2/o82ai that the processor is looking at a "window" of values. This refers to the fact that this appears to be a slice on a graph of time plotted against sampled values. The n+1points move on the graph in the direction of increasing time. Hence set 4 is to the left of the later set ~. This is known as "sliding" ~he "window".
. ~
Unfortunately, as described above, the mean does not provide an accurate representation of the average at the time tn. Instead, it actually represents `~
the average value at the time t"~, which is the time halfway between to and tn~ Using the example in Figure 1, the mean is actually effective as of time t7, not tl4. -;
1 0 " ~ ~' ''' This can present problems in real-time applications, as the time t"~
may be suf~lciently remote from the time tn that the mean will have changed sign~lcantly. In the example in Figure 1, the average value at t7 is clearly different ;
than that at tl4. ,Hence it may be necessary to obtain the mean at the time tn.
1 5 . - ~
, To obtain the average at time tn~ one must know the values for times ;~
after t~. This presents no problem in non-real time applications, since the later values are ot~tained and the processing is performed at a time remote from the sampling.
Unfortunately, real-time applications require processing prior to obtaining these later 2 0 values. Hence it is impossible to obtain a mean for tn in a real-time application. ~ ~;
~ ~ Therefore it may be necessary to utilize an alternative avera~ing process to the mean-generating process described above. The present invention -reveals~ a~ different method of generating an average, one which rninirnizes the need for memory and which provides an average which can be effective at a time far later than that of the prior art.
The present~ invention provides a running average of the signal value. . ` - -Each ~subsequent average is a weighted average of the new data point and the ~ ~
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3 0 previous data points. For the preferred embodiment of the present invention, given : ' ' ' . . ~ ' ~
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'' ' ~ '''': ;~`' , -- WO 93/11482 2 ~ 2 4 ~ ~ 5 PCI ~US92/08242 9 ':, --, the previous average value an " the new avera~e value an is generated by the following fo~lmula~
a = (M-1)an l+xn (2 where M is greater than l. It can be shown that this equation is equivalent to the equation:
an= ~ ( M~1 ) lXn_f ( 3 ) 1~0 , .,, ~"
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Here it is obvious that 0 < (M-l)/M < 1. Therefore as i gets larger, the factor ((M- l)/M)~ gets smaller. This factor corresponds to the weight which XD j ` . . .
is glven in the average a.. Henco the method of the present~in7ention welghs those ~10 values which ar~ sarnpled later more heavily than those taken earlier. This results in~
; a ~avér ge value which~more closely approxlmates ~e aver ge;at t than~t e mean ~ ~ .; ` `;
generating method of the pnor ~art.
It should be noted that the weight of the previous values of the signal depends solely upon the choice of M and the time interval between the time when the averae is performed (tn) and the time when that value was;sampled, (tD.j). As M
;~ gets smaller, more recent points~are weighted more heavily.~ As the weights accorded to recent~values~are~increased,~the effective time~of the average~becomes closer to the dme~ t~
Un rtunately,there re~disadva tagestoweighong~t emo recent v~ues~ve~ heavily. Such weightlng reduces the~ smoothing;:effect t at~ ~e aver ging ~
provides~ to ;the~ data. In practical terms, heavily increasing the wei~hts of recént data ~ ~ ;
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.
WO 93/1 1482 ~ ~ 2 ~ 8 ~ 5 PCT/US92/08;~
'"' values produces a similar effect to that caused by diminishing the num'oer of sample points in ~he mean generating method.
Hence there is a tradeoff when selecting weights for recent values S between providing more limely responses and providing accurate responses. Thus a desired M should be chosen in light of the speci~lc needs of the application in which this method is irnplemented. For example, for the case of a moving cellular telephone, values of M = 2 or M = 3 may be satisfactory.
The method of the present invention does not require a memory ;~
device, since in the preferred embodiment only a register is required to hold the previous value of the average, a".,. This can lead to a significant decrease in the ;.
complexity of the hardware necessary to obtain the average over the prior art. - `;
In the preferred embodiment described above, ~" replaces an.l. This is not necessary for all embodiments. The average value may be calculated based upon ~ ~;
some time intervai which is an integer l times the sampling time. This may be desired in cases where the samp~ing occurs faster than the circuit can produce the : ~ .
average. Irl such cases the undesired samples may be neglected while every i~
2 0 sample is averaged. The previous average value may then be denoted as ap, to prevent confusing the indices of the average and the sarnples X
Hence the method of the present invention provides an effective average which is effectively closer in time to the time when the averaging is performed than the methods of the prior art. In addition, a significant decrease in hardware complexity can be a hieved. ;
; ~ ,, . -.
The preferred implementation of the method of the present invention is .
illustrated ln Figure 2. ~ First, the~operational pararneters are set at lO. This includes setting the value of M and obtaining the initial value of the input signal, xO, received ` '~
:
- . WO 93/1 14X2 2 ~ 2 ~1 ~ S S PCI/US92/08242 by an input port. Also, at t = to there is no previous average value. Thus the value xJM is assigned to aO and is read into a register which temporarily holds the average value. Initialization is completed by setting a counter n to 0 at 12.
The method may be implemented as follows. The most recent value of the average, an, is retrieved at 14. The average value may be temporarily stored in a register separate from the arithmetic unit, or may be stored in the arithmetic unit itself. Next7 the value (M-l)an is computed by the arithmetic unit at 16. The counter n is then incremented at 18. The next value of the input signal, Xn~ is read at 20. ~ .
The value xn is then summed at 22 with the output of step 15. It should be notedthat the value of n has been incremented, and therefore the result obtained at 16 is actually (M-l)an.~. Hence the result of step 22 is (M-l)an~ + x,. The result of step ;~
22 is then divided by M at 24. This yields the new average value an = [(M-l)an.l +
xn] / M, which is available for retrieval at 14 for the next iteration. -' ~ ,;
It is possible to implement the preferred method without the --initialization sleps, i.e. without steps 10 and 12. If these steps are ignored, and the ~ `
register is initially set to zero, then an error is introduced into a". The size of this error is~
Err= ( M-1 ) n xO ;~
, ',: .:.',' .
2 0 Therefore the fractional error is given by: ;
.....
X ---M ( M ) -For a typical small value, M = 3, the fractional error is less than 0.01 when n = 9. The fraclional error is reduced to less than 0.001 a~er n = 15. For M
= 2, the fractional error~is less than 0.01 when n = 6, and is less than 0.001 after n =
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~, WO 93/114B2 21 2 4 ~ 5 S PCr/US92/082,~
9. Therefore it iS clear that if M is small then the effects of the error dirninishes rapidly. There may be applications for which $he,effects of the resulting error are outweighed by the benefits of the resulting decrease in hardware complexi~y. In such ' ~ ~;
cases initialization may be omitted.
,' ,' ~ ~ '''', The manner in which $he present inven~ion can be implemented as an ' ,~
apparatus can best be understood in light of the preferred embodiment. Figure 3 is a block diagram of an implementation of an averagin,~ circuit according to the,present invention. A clock 110 is provided for ~enerating timin~ signals which control the ' timin~ of the operations accomplished by the circuit. These signals may be such that ~ "~
different signals operate to control different elements of the circuit, or all elements may be controlled by the same signal. The signal only need be utilized to control some element of the circuit.
First, a signal input port 112 receives on input line 130 an input signal which is to be averaged. The input'signal represents a value XD which is to be averaged by saidl averaging circuit, wher~i the subscript n indicates a measure of the '', ...
time at which the signal is received. The representation may be accomplished in a"' ,', , variety of manners know to the art, including but not limited to digital representation ', ~' ',, and amplitude modulation. The choice of representation schemes is then matched to', ''~ ', the hardware which implements the averaging. This will be discussed in greater ;' ~;''' detail below.
. ' ': :-Next, input port 112 responds to tirning signals on input port clock control line 150 to transmit the signal value at discrete time intervals corresponding to integer values of n as descnbed above. These signals X" are ~ansmitted on input pon transmission line 132 to the averaging circuit 120. Averaging circuit 120 is ~ - -connected to clock 110 and is responsive to timing slgna!s transnutted on timinglines 152, 154 and 158, as discussed below.
~ .
: ~ :
,- - WO 93/11482 2 12 4 ~ 5 S Pcr/US92~08242 Averaging circuit 120 generates an avera~e value an from the value x and the previous average value aD-l. The previous average value an l is received from previous average retrieval line 138 which is connected to an output port setting line 136. Averaging circuit 120 acts to add Xn to (M-1) times the previous average value S a" l, and then divides the sum by M to yield the average value a~. M may be set in the multiplier 122 and the divider 126 by a setting device 140. The role of the weighting factor M is discussed in greater detail above.
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In the preferred embodiment illustrated in Figure 3, averaging circuit 120 receives the previous average value an, from previous average input line 138 and stores it temporarily in multiplying circuit element 122. Multiplying circuit element 122 acts in response to timing signals on timing line 158 to generate a signal which represents the value (M-l)an l. The output signal from multiplying circuit element -122 is transmitted on multiplier output line 142 to addin~ circuit element 124. ;~
Adding circuit element 124 acts in response to timin~ signals on timing line 152 to generate a signal representing the sum of the value corresponding to the output of ; ~
multiplying circuit elemen~ 122 ((M-l)al, ,) and that of the input signal value x". The - -output of adding circuit element 124 is transmitted via adder output line 134 todividing circuit element 126. Dividing circuit element 126 acts in response to timing signals on timing line 154 to generate a signal representing the value obtained by dividing the value represented by the output of adding circuit element 124 by M.The value thus obtained is the average value an.
The resulting signal representing the average a" is then transmitted on output port transmission line 136 to an output port 114. Output port 114 is connected to output line 148 to allow the average an to be accessed by external ~;
circuits.
At the time to~ it is desirable to utilize a different process in order to ~;
3 0 initialize the system, as described above. In the prefelTed embodiment of the present WO 93/1 1482 ~ 5 ~ P~r/US92/08 invention, this is implernented by connecting input port 112 to an initialization circuit 118 via an initialization line 144. Initialization circuit 118 responds to tirning signals from clock 110 on initialization timing line 160 to read the value xJM into memory 116 at time to~ The value xJM is then transmitted to previous average input line 138 and output port setting line 136.
' - ' '~. ~ ~' .
One implementation of a circuit according to the present invention is illustrated in Figure 4. The input si~nal is a digital signal, wherein several individual binary voltage values together comprise a signal. This signal represents the value X
1 0 ' " '' ' A clock 210 ~enerates timing signals which control the timing of the operations accomplished by the circuit. As noted above, these signals may be such that different signals operate to control different elements of the circuit, or all ~ ' elements may be controlled by the same si~nal. In addition, not every signal need be utilized to control some element of the circuit. ~ ~ ~
''.',' ., ~ ': ' ~ signal input port 212 receives on input line 230 a digital input sig:lal which is to be avera~ed. Signal input port may be implemented as a digital ~ ;
2 0 buffer. The input signal represents a value x" which is to be averaged by the averaging circuit, as described above.
.
lnput port ~212 responds to timing signals on input port clock control ~ ;
line 250 to~ transm~it the ~signal value at discrete time intervals as described above.
These signals xn are transmitted o~ input port transmission line 232 to the averaging circult 220. Averagmg circult 220 ls connected to clock 210 and is responslve totiming signals transmitted on timing lines 252, 254 and 25~, as discussed below.
? ~ ~ Averaging circuit 220 ~enerates an average value an from the value xn 3 0 and the previous average value an l. The previous average value an l is received from : ~.
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: . -, - WO93/11482 15212~;5 PCI/US92~08242 ;~
previous avera~e retrieval line 238 which is connected to an output port set~ing line 236. The previous average value may be stored in a standard digital register, asdescribed below. Averaging circuit 220 acts to add xn to (M-1) times the previous average value an l, and then divides the sum by M to yield the average value an. The role of the weighting factor M is discussed in greater detail above.
: '~.., .. '.:.`
Averaging; circuit 220 receives the previous average value an., from previous avera~e retrieval line 238 and stores it temporarily in multiplying circuit ~ ~ -element 222. Multiplying circuit element 222 acts in response to timing signals on timin~ line 258 to generate a si~nal which represents the value (M-l~aO.,. If (M-l) is ~ ~ `
known to always be a power of two, then the multiplyin~ circuit may be implemented as a sin~le digital shift register, considerably simplifying hardware ;
implementation. It may o~herwise include a standard di~ital register and a digital multiplier. Such multipliers are well known in the a~
,~
The output signal from multiplying circuit element 222 is transrnitted on multiplier OlltpUt line 242 to adding circuit element 224. Adding circuit element 224 acts to ~enerate a si~nal representing the sum of the value corresponding to the output of multiplyinc circuit element 222 ((M-l)aO.I) and that of the input signal 2 0 value xn.
The output of addin~ circuit element 224 is transrnitted via adder `
output line 234 to dividing circuit element 226. Dividin~ circuit element 226 acts in response to~dming slgnals on timing line 254 to ~enerate a si~nal representing the ;~
value obtained by dividing the value represented by the output of adding circuitelement 224 by M. If M is known to always be a power of two, then dividing -element~226 may be implemented as a single di~i:al shift register. It may o~erwise include a standard digital register and a digital divider. Such dividers are well known in the art. The value thus obtained is Ihe average value an. ~ ;~
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W0 93/11482 ~ P~r/US~2/~ 2 The resulting si~nal representing the avera~e an is then transmitted on output port transmission line 236 to an output port 214. Output port 214 may be implemented as a digital output buffer. Output port 214 is connected tO output line ~48 to allow the average an tO be accessed by external circuits.
At the time to~ it is desirable to utilize a different process in order to j initialize the system, as described above. ln the preferred embodiment of the present `
invention, this is implemented by connecting input port 212 to an initialization circuit 218 via an initialization line 244. Initialization circuit 218 responds to tirning signals ~;
from clock 210 on initialization timing line 260 to read the value xJM into memory ;:
216 at time to. The value x~JM is then transmitted to previous average input line 238 and output port setting line 236.
An alternative implementation to the circuit of Figure 3 according to the present invention is illustrated in Figure 5. The input si$nal is an analog sl~nal, wherein the vol~age value of the signal represents the value x".
' A clock 310 generates timing signals which control the timing of the operations accomplished by the circui~. As noted above, these signals may be such 2 0 that different signals operate to control different elements of the circuit, or all elements~may be controlled by the same signal. In addition, not every signal need be utilized to control some element of the circuit.
~A signal input po 312 receives on input line 330 an ana10g input signal which is to be averaged. Signal input port may be implemented as an analog ' ' ' I , ! ~
sample-and-hold ci~cuit. The instantaneous voltage value of the input signal represents a value x" which ~is to be averaged by the avera~mg circuit, as described above. ~
, : .: ': .
~WO 93/11482 2 1 2 4 ~ 5 ~ PCI`/US92/08242 lnput port 312 responds to timing signals on input port clock control li!ne 3~0 ~o transrnit the signal value at discrete time intervals as described above.
These signals xn are transmitted on input port transmission line 332 to the averaging - ~ -circuit 320. Averaing circuit 320 is connected to clock 310 and is responsive to ~ ~ -~iming signals transmitted on timing lines 352, 354 and 358. as discussed below.
Averaging circuit 320 generates an average value a~ from the value XD
and the previous average value an.l. The previous average value a" I is received from memory output line 3¢0 which is connected to a sample-and-hold (S/H) device 316.S/H device 316 may be a standard sample-and-hold circui~. Averagin~ circuit 320 acts to add xn to (M~1) times the previous average value an.l, and then divides the sum by M to yield the average value an. The role of the weighting factor M is discussed in ~reater detail above.
AveFaging circuit 320 receives the previous average value an., from ~a S/H devlce 316 via output line 340. Multiplying circuit 322 acts to generate in response to oming signals on timing line 356 a signal which represents the value (M-l)a" l. Multiplying circuit 322 may be implemented as a standard op-amp with a ` :
gain of M-li as shown. l~e gain of op-amp 370is set by the ratio of resistors 372 and 374, i.e. (M-2)R4 / R4, or (M-2). The gam of such an op-amp is the ralio of the resistances plus one. Hence the gain is (M-1). Op-arnp 370 acts to multiply the arnplitude of the si~nal.
The output sinal~ from multiplying circuit 322is transmitted on muldplier output line; 342 to adding circult 324. Adding circuit 324 acts to generate a~voltage representing the sum of the output voltage mul~plying circuit 322 ((M~and~ that of the input signal value~xl; on input port transmission line 332- The ~
value~on~input ~port transmisslon line 332; is changed in response to timing signals on ummg~line 250~to S/H devlce 312.
..... '~
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~124~55 ~8242 ~
Adding circuit 324 may use resistors 376 and 378 to average the voltage between the inputs. The average is an arithmetic mean as the values of resis~ors 376 and 378 is the same, e.g. Rl. The op-amp 3B0 has a gain of two because the ratio of the resistances between resistors 382 and 384 i5 R2/R2 or 1, and the gain of ~uch an op-amp is the ratio of the resistances plus one. The output of op-amp 380 is a pure sum of the voltages, as twice the mean average of two values is the sum of those values. In addition, op-amp 380 acts a~ a driver for subsequent stages.
The output of adding circuit element 324 is transmitted via adder output line 334 to dividing circuit 326. Dividing circuit element 326 acts to divide the voltage representing the value obtained by dividing the value represented by the output of adding circuit 324 by M. Dividing element 326 may be implemented as a resistor-based voltage divider circuit as shown, where the output ~oltage is based upon the values of resistors 386 and 388 and is R3l((M-l)R3 + R3), or ~. The value thus obtained is the average value an.
The resulting signal representing the average an is then transmitted on output port transmission line 336 to an outpu~ port 314. Output Port 314 may be implemented as an analog sample-and-hold circuit. Output port 314 i9 connected to output line 348 to allow the average a to be accessed by external ~ircui~s. In addition, the average value an is ~ransmitted on input line 338 to memory 316, which responds to a timing signal from clock 310 transmitted on transmission line 356 to store the naw average value an.
An example of an application of the averaging method of the present invention is illustrated in Figure 6.
Figure 6 is a flow chart for a method of comparing the average values of ~ distinct signals in real-time.
Timing ~ignal~ are obtained from a clock, which controls the sequence of steps.
8U~TUrE 8H~
:
PC~/~JS92 / 08 ~42 ~12485~ ~P~S 22N0V199 The ~ average values of the j different signals at every instant are obtained by the method described above for calculating the averages by the present invention.
The j previous average values ak,p ~ where 0 < k ~
and p is the index of the immediate previous averi~ge value, are read into j memory devices at 610. An input signal representing a value xk,n to be averaged is received for a kth signal at ~ input ports at 612~ A
weighted average value ak,n of the previous average value ak,p and the value xk,n represented by the corresponding input signal is provided at 614 in response to the timing signals. The weighted average value is defined as the sum ((M-l)ak,p + xk,n) divided by ~, where M is a -' predetermined positive number greater than 1. Next lS output signals representing each of ; said weighted average value ak,n are transmitted at 616 to a comparison device. Finally, the ~ weighted average values ak,n are compared at 618.
It is important to note that this method may include initialization steps such as those discussed above regarding Figure 2. This initialization would occur at -step 610, as initialization essentially provides a prior average value. Such initialization may be less critical in cases such as this implementation where the error of multiple averaging should not disrupt the comparison being provided. ~-~ Although the method described indicates simultaneous proce~sing at each stage~of the averaging proces3, there may be some~flexibility in the precise timing of each 30 step. The cxitical requirement is that the avera~es for - -all ; averaging circuits be complete at the time when ~ ;
the comparison is initiated.
~ This method may be implemented in a circuit, as illustrated in Flgure 7. A comparison circuit for real- ~
35 time comparison of j distinct ak,~ values of ; signals, - - -~ :
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1 9a said comparison circuit would require a clock circuit - -710 for generating timing signals. This circuit may be , constructed from multiple clock~, and may appear as ~
individual circuit clock. ~ :
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WO 93/114B2 ~12 4 8 ~ ~ PCI/US92/OB~-J~
The circuit would include j real-time signal averaging circuits 700, each of said signal averaging circuits being represented by an positive number label k, O ~ k S j - 1. These circuits would be identical to the circuit disclosed above.
The k~ signal averaging circuit 702 includes a k'h signal input port 712 for receiving the k'b one of the j input signals. The input signal received at k~ signal input port 712 represents a value xkn which is to be averaged by k'h signal averaging circuit 702. The k'h memory 716 stores a previous average value akp which was output from k~ signal averaging circuit 702.
The l;lh avera~ing subcircuit 720is connected to clock 710,k'h signal input port 712 and k"' memory 716. The k'h averaging subcircuit 720 provides in response to the timing signals an average value a,~,n. This average is defined as the sum ((M-l)akp + x,~n) divided by M, where M is a predetermined positive number greater than l. Hence average value ak,n is the weighted average of the value x,~.n represented by the ~Ih input signal received at k'h signal input port 712 and of the previous averagre value a,~p stored in k'b memory 716. The k'b averaging subcircuit 720 provides to k~ memory 716 the average value aLn. Finally, k'h output port 714 is ~ ~ ~
connected to k'h averaging subcircuit 720 to generate on k~ averaging circuit output ~ : ;
line 718 a k"' one of j output signals, thereby representing the average value a,~n. `
2 0 ;;
. . .. .
The j output signals are then compared by an appropriate comparison subcircuit 770 connected to each of the j si$nal averaging circuits 702 by one of the -; -j averaging circuit output lines 718.
As discussed above regarding Figure 4, these j averaging subcircuits may be designed to include initialization circuitry.
This comparison circuit may be implemented in a variety of manners corresponding to llle variety of methods of representing signal values, as discloses 3 0 above. The input signals may be digital signals representing the values x~n. In such ~` '"'' '' ~
' "' ~, ~ . .
~ Wo 93/1 ~482 2 ~ 2 ~ 8 ~ S PCI/IJS92/08242 a case the digital k~ averaging circuits 702 may be construc~ed as illustrated in Figure 4 and discuss.ed above. The j output signals of these averaging circuits 702 would be dig,ital signals representing the weighted average values. a",n. Memory 716 could 'oe implemented as a di~ital data registers. Comparison subcircuit 770 may be implemented as a simple digital calculation circuit.
In the alternative, the input signals may be analog signals whose arnplitudes represent the values x,~ n. In such a case the analog k'h averaging circuits 702 may be constructed as illustrated in Figure S and discussed above. The j output signals of these averaging circuits 702 would be analo~ signals representing theweighted average values akn. Memo;y 716 could be implemented as a sample-and-hold-circuit, and comparison subcircuit 770 may be implemented as a simple analog comparator.
l~ach element in the above described embodiments can be constructed ;~
by means of components well known in the appropriate electronic art. Those skilled in those arts can readily design numerous alternative implementations of these embodiments. In addition, other methods of representing data values may be utillæd.
There has been described herein an improved real-time averaging circuit. Various modiflcations to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings.
Accordingly, the present invention is to be limited solely by the following claims.
. .
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F;eld of lhe lnvention The present invention relates to real-time devices, and more specifically to real-time devices for calculating an average of values represented by a signal.
....
Back~round of the Invention `
Mobile radio (electronic) devices often are required to adapt to ; ~ -changes in the;r environment or to vary the output which they are to produce in a nearly instantaneous manner. This has led to an increased reliance upon real-time evaluation of diata representing physical quantities.~ "Real-time" here refers to the fact thal the~ evaluation is performed at essendally ;the same dme as the data is acquired. ~ Real-time systems t~pically require very rapid processing of data as th8 ~ ~
data is obtaine~. Non-real-time evaluation occurs at some time long after the data is ~ ~ .
obtained. For example, when a mobile unit is requesting a service, a response from ~ ;
2 0 the system to the mobile unit takes a long time; the time lag in processing the data ; can cause the results to be obsolete by ~tho time those results are obtained.
The information processin~ limitations of the electronic hardware involved with a particular devico~help~determine the operational capaclty~and~
2;5 ~ ; ma~rm~ um processing speed~ of that devlce. Hence ~minimizadon of hardware complexity and increases in hardware response time are cIitical to evaluation of data for those applîcations.
: ~: : ~ .
Oné~ example of such a~ time-itical appDcation is found in the field of 3 0 ~ ~ ~ cellular telephones. Cellular mobile t~lephones (mobile units~ must receive si~nals broadcast from the cell site transmitters. The mobile telephones are often themselves : ~
WO 93/l t482 2 1 2 ~ Pcr/US92/082 in motion. This motion leads to chan~es in the strength of the signals received by the mobile unit. Cellular telephone networks attempt to maintain an acceptable ;
signal level at each site, and switch the signal to a new cell when the average signal received from the mobile unit becomes weak, i.e. below the acceptable level. This switching may be accomplished by comparing the intensity of the average value of-.~ ....
the signals from different cells and selecting that signal which is strongest. ~ ~
: .. : :
Determination of the avera~e value is presently accomplished in the following manner. The receiver measures the signal intensity at a number of points, I
for example twenty, and stores these values in a memory. The values are then added and the sum is divided by the number of stored values. This yields the mean (average) value of tne signal intensity. Typically, the next average is obtained by discarding the oldest stored value, replacing it with a new value, and performing the averaging computations just described. This leads to a smoother transition of the -computed averagle over time, and utilizes a fixed memory capacity.
This method is not ideal for real-time operations such as are used in cellular telephone systems. It requires memory devices for storing these values to be -averaged. This complicates the hardware of the system and slows the averaging 2 0 process. More importantly, it yields the average value as of the moment that is halfway between the newest and the oldest data value. In the example given above, the average value represents the value at the time midway between the 10th and 11th data value. Thus if instantaneous data were being sampled once every second, theaverage obtained is actually the~ average value as of a point in time ten seconds prior 2 5 to the most recent data value measured. This does not include the delay caused by actually performing the calculations themselves.
This physical delay is a serious problem for cellular telephone networks. In~ addition, the lag in the computed average value is large enough toadversely affect the reliability of the comparisons based upon those averages, which '' ;." ~
Wo 93/1 1482 2 1 2 4 ~ 5 ~ PCr/US92/08242 ~ ~
are not valid for use for real-time comparisons among them. This lag increases as the number of points sampled increases. Thus the more precise the average, the older it is and thus less reliable. This is only compensated for by increasing the sampling rate of the device, which often is accompanied by seYere increases in cost. - -S ' It would therefore be desirable to perform an averaging which yields a more timely result, and one which minimizes the hardware complexity of the average processing device. Also, while the example given relates to cellular telephone networks, it is clear that similar problems may arise in a variety of applications which involve real-time averaging of data to smooth out fluctuations.
Broadly, it is an object of the present invention to provide an improved real-time signal averaging device.
It is a further object of the present invention to provide a real-time si~nal averagin,g circuit which generates an output which represents the average value of data at a time close to the time at which the new data are obtained.
It is a still further object of the present invention to provide a real-time signal averaging circuit which requires no memory hardware.
These and other objects of the present invention will be apparent to those skilled in ~the art from the following detailed description of the invention and the accompanying drawings.
'' ' ~'' :' ''.~''"".','` ~`'';' WQ 93/1 1482 ~ ~ 2 ~ PCr/US92/082~
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Sumrnarv of the Invent_n ~ -", The present invention comprises a real-time signal averaging circuit. - ;
The averaging circuit includes clock means for generating timing signals. The averaging circuit also includes signal input means for receiving an input signal. The . . ... ~
input signal represents a value xn which is to be averaged by the averaging circuit~ ~ ;
The averaging circuit further includes register means for temporarily storing and updating a previous avera~e value ap which was output from the averaging circuit.
Averaging means are connected to the clock means, the signal input means and theregister means~ 1~e avera~ing means provides in response to the timing signals aweighted average value an of the value xn represented by the input signal and of the previous average value ap stored in ehe register means~ The average value an is defined as the surn ((M-l)ap ~ xn) divided by M, where M is a predetermined positive number greater than l. The averaging means provides to the register means the average value an. Finally, the circuit includes output signalling means for generating an output signal representing the average value an. The output signalling means is connected to said averaging means.
; 20 Alternative embodiments are disclosed for circuits in which the value is represented digitally, wherein the register means is n digital data regis~er, and in which~the value is represented by an analog amplitude, wherein the register means is ~ . .
~a sarnple and hold~ device, Also, in the preferred embodiment of the present invention, the previous alue ~ is the Immediately previous nvernge value n ~
The present invention also includes a method of producing an average value of a signal in real-time. The method includes obtaining timing signals from a clock means. Next a previous average value a" l is input into a register means. An input signal representing a value X" to be averaged is then received. Then a weighted . ~ , -~ WO93~ 82 2~2~8S~ Pcr/us92/08242 ~ ~
average value an of the previous average value a" l and the value xn represented by said input signal is provided in response to the siming signals. The weighted average value a" is defined as the sum ((M-l)aD.I + xn)) divided by M, where M is a predetermined positive number greater than 1. Finally an output signal is generated representing the weighted average value an.
: ' As for the circuit described above, there are corresponding al~ernative implementations of the present method. The value may be represented digitally, in which case the register means is again a digital register, or an analog ma~nitude 1 0 device.
Brief DescriDtion of the Drawil os :
~, i .. ~
F'igure 1 illustrates a signal being sampled at discrete points separated by uniform time intervals.
:
Figure 2 is a flow chart illustrating the preferred implementation of the 2 0 method of the present invention.
Figure 3 is a block diagram representation of an implementation of an averaging circult according to the present invention. ;:
Figure 4 is a schematic diagram of a circuit according to the present invention for averaging digital signals. `-~
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Figure 5 is a schematic diagrarn of a circuit according to the present invention for averaging analog signals.
3 0 . ~ ~ -' PCTIU~9~ / ~J ~) 42 2 ~ 2 4 ~ PE~WS 2 2 ~ ~ o\l 1~93 ., . . ~ .; ,. ~
Figure 6 is a block diagram representation of a comparison circuit according to the present invention. ~-Figure 7 is a schematic diagram of a circuit ; ~
according to the present invention fox comparing the ~;
5 averaging values of a plurality of digital signals. ~;
:'.: .' ,' .;~ -..
Detailed DescriPtion of the Invention The advantages provided by the present invention are best understood in light of the prior art method.
Therefore a brief explanation of the method of the prior art is required. A signal to be averaged is sampled at regular intervals. The times at which these samples were obtained are referred to as tol tl,...tn, where there are n~l data points sampled. The values of these dàta points are denoted as xO, xl,...~. While these signal values axe said to represent the values to be averaged, this does not mean that there must be an ;~
encoding of external data into signal form. The signal may be inherently characterized by the values to be ;~
averaged.
~te ~ver~ge value ob~ai e by th prior art m tho~ ~
This type of average is referred to as an arithmetic ~:-30 mean, or simply a mean. ~ ~ ~
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; . ~` ~''""",.:'- :`' - - Wo 93/11482 21 2 ~ 8 ~ ~ PCr/US92/08242 Fi~ure 1 illustrates an example of how such a sampling is undertaken.
A signal 1 is shown plotted on a graph, where vertical distance represents the value of the signal and ~he horizontal distance represents time. The labelled circles represent the signal values xO, x" ... sampled at the times to~ tl, .... A specified number of these values are added and the sum is divided by that number of values.
Hence, for lS points, the mean is equal to (xO + x, + ... + X14) /15.
Typically, these n+l values are stored in a memory device. The next subsequent mean would be obtained by discarding xO and replacing it with x,~+,. The summation would then be performed by summing the values xl to x"+,. This allows ~-for summation using a continuing adding process using an adder and with a memoryfor storing the n+l most recent values. Such a procedure, utilized for each timesampled, acts to smooth out the values of the means thus obtained. This helps eliminate noise ~md minimizes the possibility of dramatic swings in the average values obtained by the procedure.
It should be noted that the term "memory" is used herein to describe ` ~;
devices for storage of values which are to be statically maintained during the calculation of several avera~e value. In the specific example given above each memory location retains its value for lS average value calculations. This is where the data itself is stored. The term "register", by contrast, is used herein to describe devices for stora~e of values which are to be maintained only until used a single - : ~
time, and then are replaced with a new value. Re~isters would be used to ~ -~ ternporarily store data until it is utilized and replaced durin~ the next average~value 2 5 calculation.
The method described above may be better understood by again referring to Figure l. A first set 4 of 15 data points which are averaged at time tl4 is shown. Also, a second set 5 of lS data points which are averaged at time tl5. Since 3 0 the processor only looks at n+l points out of many that have been taken, it is said . .. ... -.
wo 93/11482 ~12 ~ 8 5 ~ Pcr/uss2/o82ai that the processor is looking at a "window" of values. This refers to the fact that this appears to be a slice on a graph of time plotted against sampled values. The n+1points move on the graph in the direction of increasing time. Hence set 4 is to the left of the later set ~. This is known as "sliding" ~he "window".
. ~
Unfortunately, as described above, the mean does not provide an accurate representation of the average at the time tn. Instead, it actually represents `~
the average value at the time t"~, which is the time halfway between to and tn~ Using the example in Figure 1, the mean is actually effective as of time t7, not tl4. -;
1 0 " ~ ~' ''' This can present problems in real-time applications, as the time t"~
may be suf~lciently remote from the time tn that the mean will have changed sign~lcantly. In the example in Figure 1, the average value at t7 is clearly different ;
than that at tl4. ,Hence it may be necessary to obtain the mean at the time tn.
1 5 . - ~
, To obtain the average at time tn~ one must know the values for times ;~
after t~. This presents no problem in non-real time applications, since the later values are ot~tained and the processing is performed at a time remote from the sampling.
Unfortunately, real-time applications require processing prior to obtaining these later 2 0 values. Hence it is impossible to obtain a mean for tn in a real-time application. ~ ~;
~ ~ Therefore it may be necessary to utilize an alternative avera~ing process to the mean-generating process described above. The present invention -reveals~ a~ different method of generating an average, one which rninirnizes the need for memory and which provides an average which can be effective at a time far later than that of the prior art.
The present~ invention provides a running average of the signal value. . ` - -Each ~subsequent average is a weighted average of the new data point and the ~ ~
.,~... . ~
3 0 previous data points. For the preferred embodiment of the present invention, given : ' ' ' . . ~ ' ~
''....: ~.:
'' ' ~ '''': ;~`' , -- WO 93/11482 2 ~ 2 4 ~ ~ 5 PCI ~US92/08242 9 ':, --, the previous average value an " the new avera~e value an is generated by the following fo~lmula~
a = (M-1)an l+xn (2 where M is greater than l. It can be shown that this equation is equivalent to the equation:
an= ~ ( M~1 ) lXn_f ( 3 ) 1~0 , .,, ~"
,, ",..,~
Here it is obvious that 0 < (M-l)/M < 1. Therefore as i gets larger, the factor ((M- l)/M)~ gets smaller. This factor corresponds to the weight which XD j ` . . .
is glven in the average a.. Henco the method of the present~in7ention welghs those ~10 values which ar~ sarnpled later more heavily than those taken earlier. This results in~
; a ~avér ge value which~more closely approxlmates ~e aver ge;at t than~t e mean ~ ~ .; ` `;
generating method of the pnor ~art.
It should be noted that the weight of the previous values of the signal depends solely upon the choice of M and the time interval between the time when the averae is performed (tn) and the time when that value was;sampled, (tD.j). As M
;~ gets smaller, more recent points~are weighted more heavily.~ As the weights accorded to recent~values~are~increased,~the effective time~of the average~becomes closer to the dme~ t~
Un rtunately,there re~disadva tagestoweighong~t emo recent v~ues~ve~ heavily. Such weightlng reduces the~ smoothing;:effect t at~ ~e aver ging ~
provides~ to ;the~ data. In practical terms, heavily increasing the wei~hts of recént data ~ ~ ;
: : ' : ' :' ~
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WO 93/1 1482 ~ ~ 2 ~ 8 ~ 5 PCT/US92/08;~
'"' values produces a similar effect to that caused by diminishing the num'oer of sample points in ~he mean generating method.
Hence there is a tradeoff when selecting weights for recent values S between providing more limely responses and providing accurate responses. Thus a desired M should be chosen in light of the speci~lc needs of the application in which this method is irnplemented. For example, for the case of a moving cellular telephone, values of M = 2 or M = 3 may be satisfactory.
The method of the present invention does not require a memory ;~
device, since in the preferred embodiment only a register is required to hold the previous value of the average, a".,. This can lead to a significant decrease in the ;.
complexity of the hardware necessary to obtain the average over the prior art. - `;
In the preferred embodiment described above, ~" replaces an.l. This is not necessary for all embodiments. The average value may be calculated based upon ~ ~;
some time intervai which is an integer l times the sampling time. This may be desired in cases where the samp~ing occurs faster than the circuit can produce the : ~ .
average. Irl such cases the undesired samples may be neglected while every i~
2 0 sample is averaged. The previous average value may then be denoted as ap, to prevent confusing the indices of the average and the sarnples X
Hence the method of the present invention provides an effective average which is effectively closer in time to the time when the averaging is performed than the methods of the prior art. In addition, a significant decrease in hardware complexity can be a hieved. ;
; ~ ,, . -.
The preferred implementation of the method of the present invention is .
illustrated ln Figure 2. ~ First, the~operational pararneters are set at lO. This includes setting the value of M and obtaining the initial value of the input signal, xO, received ` '~
:
- . WO 93/1 14X2 2 ~ 2 ~1 ~ S S PCI/US92/08242 by an input port. Also, at t = to there is no previous average value. Thus the value xJM is assigned to aO and is read into a register which temporarily holds the average value. Initialization is completed by setting a counter n to 0 at 12.
The method may be implemented as follows. The most recent value of the average, an, is retrieved at 14. The average value may be temporarily stored in a register separate from the arithmetic unit, or may be stored in the arithmetic unit itself. Next7 the value (M-l)an is computed by the arithmetic unit at 16. The counter n is then incremented at 18. The next value of the input signal, Xn~ is read at 20. ~ .
The value xn is then summed at 22 with the output of step 15. It should be notedthat the value of n has been incremented, and therefore the result obtained at 16 is actually (M-l)an.~. Hence the result of step 22 is (M-l)an~ + x,. The result of step ;~
22 is then divided by M at 24. This yields the new average value an = [(M-l)an.l +
xn] / M, which is available for retrieval at 14 for the next iteration. -' ~ ,;
It is possible to implement the preferred method without the --initialization sleps, i.e. without steps 10 and 12. If these steps are ignored, and the ~ `
register is initially set to zero, then an error is introduced into a". The size of this error is~
Err= ( M-1 ) n xO ;~
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2 0 Therefore the fractional error is given by: ;
.....
X ---M ( M ) -For a typical small value, M = 3, the fractional error is less than 0.01 when n = 9. The fraclional error is reduced to less than 0.001 a~er n = 15. For M
= 2, the fractional error~is less than 0.01 when n = 6, and is less than 0.001 after n =
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~, WO 93/114B2 21 2 4 ~ 5 S PCr/US92/082,~
9. Therefore it iS clear that if M is small then the effects of the error dirninishes rapidly. There may be applications for which $he,effects of the resulting error are outweighed by the benefits of the resulting decrease in hardware complexi~y. In such ' ~ ~;
cases initialization may be omitted.
,' ,' ~ ~ '''', The manner in which $he present inven~ion can be implemented as an ' ,~
apparatus can best be understood in light of the preferred embodiment. Figure 3 is a block diagram of an implementation of an averagin,~ circuit according to the,present invention. A clock 110 is provided for ~enerating timin~ signals which control the ' timin~ of the operations accomplished by the circuit. These signals may be such that ~ "~
different signals operate to control different elements of the circuit, or all elements may be controlled by the same signal. The signal only need be utilized to control some element of the circuit.
First, a signal input port 112 receives on input line 130 an input signal which is to be averaged. The input'signal represents a value XD which is to be averaged by saidl averaging circuit, wher~i the subscript n indicates a measure of the '', ...
time at which the signal is received. The representation may be accomplished in a"' ,', , variety of manners know to the art, including but not limited to digital representation ', ~' ',, and amplitude modulation. The choice of representation schemes is then matched to', ''~ ', the hardware which implements the averaging. This will be discussed in greater ;' ~;''' detail below.
. ' ': :-Next, input port 112 responds to tirning signals on input port clock control line 150 to transmit the signal value at discrete time intervals corresponding to integer values of n as descnbed above. These signals X" are ~ansmitted on input pon transmission line 132 to the averaging circuit 120. Averaging circuit 120 is ~ - -connected to clock 110 and is responsive to timing slgna!s transnutted on timinglines 152, 154 and 158, as discussed below.
~ .
: ~ :
,- - WO 93/11482 2 12 4 ~ 5 S Pcr/US92~08242 Averaging circuit 120 generates an avera~e value an from the value x and the previous average value aD-l. The previous average value an l is received from previous average retrieval line 138 which is connected to an output port setting line 136. Averaging circuit 120 acts to add Xn to (M-1) times the previous average value S a" l, and then divides the sum by M to yield the average value a~. M may be set in the multiplier 122 and the divider 126 by a setting device 140. The role of the weighting factor M is discussed in greater detail above.
.',, ,~ ~
In the preferred embodiment illustrated in Figure 3, averaging circuit 120 receives the previous average value an, from previous average input line 138 and stores it temporarily in multiplying circuit element 122. Multiplying circuit element 122 acts in response to timing signals on timing line 158 to generate a signal which represents the value (M-l)an l. The output signal from multiplying circuit element -122 is transmitted on multiplier output line 142 to addin~ circuit element 124. ;~
Adding circuit element 124 acts in response to timin~ signals on timing line 152 to generate a signal representing the sum of the value corresponding to the output of ; ~
multiplying circuit elemen~ 122 ((M-l)al, ,) and that of the input signal value x". The - -output of adding circuit element 124 is transmitted via adder output line 134 todividing circuit element 126. Dividing circuit element 126 acts in response to timing signals on timing line 154 to generate a signal representing the value obtained by dividing the value represented by the output of adding circuit element 124 by M.The value thus obtained is the average value an.
The resulting signal representing the average a" is then transmitted on output port transmission line 136 to an output port 114. Output port 114 is connected to output line 148 to allow the average an to be accessed by external ~;
circuits.
At the time to~ it is desirable to utilize a different process in order to ~;
3 0 initialize the system, as described above. In the prefelTed embodiment of the present WO 93/1 1482 ~ 5 ~ P~r/US92/08 invention, this is implernented by connecting input port 112 to an initialization circuit 118 via an initialization line 144. Initialization circuit 118 responds to tirning signals from clock 110 on initialization timing line 160 to read the value xJM into memory 116 at time to~ The value xJM is then transmitted to previous average input line 138 and output port setting line 136.
' - ' '~. ~ ~' .
One implementation of a circuit according to the present invention is illustrated in Figure 4. The input si~nal is a digital signal, wherein several individual binary voltage values together comprise a signal. This signal represents the value X
1 0 ' " '' ' A clock 210 ~enerates timing signals which control the timing of the operations accomplished by the circuit. As noted above, these signals may be such that different signals operate to control different elements of the circuit, or all ~ ' elements may be controlled by the same si~nal. In addition, not every signal need be utilized to control some element of the circuit. ~ ~ ~
''.',' ., ~ ': ' ~ signal input port 212 receives on input line 230 a digital input sig:lal which is to be avera~ed. Signal input port may be implemented as a digital ~ ;
2 0 buffer. The input signal represents a value x" which is to be averaged by the averaging circuit, as described above.
.
lnput port ~212 responds to timing signals on input port clock control ~ ;
line 250 to~ transm~it the ~signal value at discrete time intervals as described above.
These signals xn are transmitted o~ input port transmission line 232 to the averaging circult 220. Averagmg circult 220 ls connected to clock 210 and is responslve totiming signals transmitted on timing lines 252, 254 and 25~, as discussed below.
? ~ ~ Averaging circuit 220 ~enerates an average value an from the value xn 3 0 and the previous average value an l. The previous average value an l is received from : ~.
~: ~
:
,..
.." ~ ~
: . -, - WO93/11482 15212~;5 PCI/US92~08242 ;~
previous avera~e retrieval line 238 which is connected to an output port set~ing line 236. The previous average value may be stored in a standard digital register, asdescribed below. Averaging circuit 220 acts to add xn to (M-1) times the previous average value an l, and then divides the sum by M to yield the average value an. The role of the weighting factor M is discussed in greater detail above.
: '~.., .. '.:.`
Averaging; circuit 220 receives the previous average value an., from previous avera~e retrieval line 238 and stores it temporarily in multiplying circuit ~ ~ -element 222. Multiplying circuit element 222 acts in response to timing signals on timin~ line 258 to generate a si~nal which represents the value (M-l~aO.,. If (M-l) is ~ ~ `
known to always be a power of two, then the multiplyin~ circuit may be implemented as a sin~le digital shift register, considerably simplifying hardware ;
implementation. It may o~herwise include a standard di~ital register and a digital multiplier. Such multipliers are well known in the a~
,~
The output signal from multiplying circuit element 222 is transrnitted on multiplier OlltpUt line 242 to adding circuit element 224. Adding circuit element 224 acts to ~enerate a si~nal representing the sum of the value corresponding to the output of multiplyinc circuit element 222 ((M-l)aO.I) and that of the input signal 2 0 value xn.
The output of addin~ circuit element 224 is transrnitted via adder `
output line 234 to dividing circuit element 226. Dividin~ circuit element 226 acts in response to~dming slgnals on timing line 254 to ~enerate a si~nal representing the ;~
value obtained by dividing the value represented by the output of adding circuitelement 224 by M. If M is known to always be a power of two, then dividing -element~226 may be implemented as a single di~i:al shift register. It may o~erwise include a standard digital register and a digital divider. Such dividers are well known in the art. The value thus obtained is Ihe average value an. ~ ;~
.;"'.'"";'-~"""'..
.' ''- ~
-, .,, ~...
W0 93/11482 ~ P~r/US~2/~ 2 The resulting si~nal representing the avera~e an is then transmitted on output port transmission line 236 to an output port 214. Output port 214 may be implemented as a digital output buffer. Output port 214 is connected tO output line ~48 to allow the average an tO be accessed by external circuits.
At the time to~ it is desirable to utilize a different process in order to j initialize the system, as described above. ln the preferred embodiment of the present `
invention, this is implemented by connecting input port 212 to an initialization circuit 218 via an initialization line 244. Initialization circuit 218 responds to tirning signals ~;
from clock 210 on initialization timing line 260 to read the value xJM into memory ;:
216 at time to. The value x~JM is then transmitted to previous average input line 238 and output port setting line 236.
An alternative implementation to the circuit of Figure 3 according to the present invention is illustrated in Figure 5. The input si$nal is an analog sl~nal, wherein the vol~age value of the signal represents the value x".
' A clock 310 generates timing signals which control the timing of the operations accomplished by the circui~. As noted above, these signals may be such 2 0 that different signals operate to control different elements of the circuit, or all elements~may be controlled by the same signal. In addition, not every signal need be utilized to control some element of the circuit.
~A signal input po 312 receives on input line 330 an ana10g input signal which is to be averaged. Signal input port may be implemented as an analog ' ' ' I , ! ~
sample-and-hold ci~cuit. The instantaneous voltage value of the input signal represents a value x" which ~is to be averaged by the avera~mg circuit, as described above. ~
, : .: ': .
~WO 93/11482 2 1 2 4 ~ 5 ~ PCI`/US92/08242 lnput port 312 responds to timing signals on input port clock control li!ne 3~0 ~o transrnit the signal value at discrete time intervals as described above.
These signals xn are transmitted on input port transmission line 332 to the averaging - ~ -circuit 320. Averaing circuit 320 is connected to clock 310 and is responsive to ~ ~ -~iming signals transmitted on timing lines 352, 354 and 358. as discussed below.
Averaging circuit 320 generates an average value a~ from the value XD
and the previous average value an.l. The previous average value a" I is received from memory output line 3¢0 which is connected to a sample-and-hold (S/H) device 316.S/H device 316 may be a standard sample-and-hold circui~. Averagin~ circuit 320 acts to add xn to (M~1) times the previous average value an.l, and then divides the sum by M to yield the average value an. The role of the weighting factor M is discussed in ~reater detail above.
AveFaging circuit 320 receives the previous average value an., from ~a S/H devlce 316 via output line 340. Multiplying circuit 322 acts to generate in response to oming signals on timing line 356 a signal which represents the value (M-l)a" l. Multiplying circuit 322 may be implemented as a standard op-amp with a ` :
gain of M-li as shown. l~e gain of op-amp 370is set by the ratio of resistors 372 and 374, i.e. (M-2)R4 / R4, or (M-2). The gam of such an op-amp is the ralio of the resistances plus one. Hence the gain is (M-1). Op-arnp 370 acts to multiply the arnplitude of the si~nal.
The output sinal~ from multiplying circuit 322is transmitted on muldplier output line; 342 to adding circult 324. Adding circuit 324 acts to generate a~voltage representing the sum of the output voltage mul~plying circuit 322 ((M~and~ that of the input signal value~xl; on input port transmission line 332- The ~
value~on~input ~port transmisslon line 332; is changed in response to timing signals on ummg~line 250~to S/H devlce 312.
..... '~
,. ~ . . . ' :'. .
: ,', ..." ':.
~124~55 ~8242 ~
Adding circuit 324 may use resistors 376 and 378 to average the voltage between the inputs. The average is an arithmetic mean as the values of resis~ors 376 and 378 is the same, e.g. Rl. The op-amp 3B0 has a gain of two because the ratio of the resistances between resistors 382 and 384 i5 R2/R2 or 1, and the gain of ~uch an op-amp is the ratio of the resistances plus one. The output of op-amp 380 is a pure sum of the voltages, as twice the mean average of two values is the sum of those values. In addition, op-amp 380 acts a~ a driver for subsequent stages.
The output of adding circuit element 324 is transmitted via adder output line 334 to dividing circuit 326. Dividing circuit element 326 acts to divide the voltage representing the value obtained by dividing the value represented by the output of adding circuit 324 by M. Dividing element 326 may be implemented as a resistor-based voltage divider circuit as shown, where the output ~oltage is based upon the values of resistors 386 and 388 and is R3l((M-l)R3 + R3), or ~. The value thus obtained is the average value an.
The resulting signal representing the average an is then transmitted on output port transmission line 336 to an outpu~ port 314. Output Port 314 may be implemented as an analog sample-and-hold circuit. Output port 314 i9 connected to output line 348 to allow the average a to be accessed by external ~ircui~s. In addition, the average value an is ~ransmitted on input line 338 to memory 316, which responds to a timing signal from clock 310 transmitted on transmission line 356 to store the naw average value an.
An example of an application of the averaging method of the present invention is illustrated in Figure 6.
Figure 6 is a flow chart for a method of comparing the average values of ~ distinct signals in real-time.
Timing ~ignal~ are obtained from a clock, which controls the sequence of steps.
8U~TUrE 8H~
:
PC~/~JS92 / 08 ~42 ~12485~ ~P~S 22N0V199 The ~ average values of the j different signals at every instant are obtained by the method described above for calculating the averages by the present invention.
The j previous average values ak,p ~ where 0 < k ~
and p is the index of the immediate previous averi~ge value, are read into j memory devices at 610. An input signal representing a value xk,n to be averaged is received for a kth signal at ~ input ports at 612~ A
weighted average value ak,n of the previous average value ak,p and the value xk,n represented by the corresponding input signal is provided at 614 in response to the timing signals. The weighted average value is defined as the sum ((M-l)ak,p + xk,n) divided by ~, where M is a -' predetermined positive number greater than 1. Next lS output signals representing each of ; said weighted average value ak,n are transmitted at 616 to a comparison device. Finally, the ~ weighted average values ak,n are compared at 618.
It is important to note that this method may include initialization steps such as those discussed above regarding Figure 2. This initialization would occur at -step 610, as initialization essentially provides a prior average value. Such initialization may be less critical in cases such as this implementation where the error of multiple averaging should not disrupt the comparison being provided. ~-~ Although the method described indicates simultaneous proce~sing at each stage~of the averaging proces3, there may be some~flexibility in the precise timing of each 30 step. The cxitical requirement is that the avera~es for - -all ; averaging circuits be complete at the time when ~ ;
the comparison is initiated.
~ This method may be implemented in a circuit, as illustrated in Flgure 7. A comparison circuit for real- ~
35 time comparison of j distinct ak,~ values of ; signals, - - -~ :
~ .
: ~ .'.
: ~;'.:. ~: '':
SUBSTITUTE~ SHE~ -` :
,:~: . ~ .::~
21291855 ~S221VOI~I393 ~ ;~
1 9a said comparison circuit would require a clock circuit - -710 for generating timing signals. This circuit may be , constructed from multiple clock~, and may appear as ~
individual circuit clock. ~ :
. . ., ~ .
;~
' . . . ~ .
. . .
, : :
:: : : : , . ~
, :.
SU13SllTUTE SHEEl~
WO 93/114B2 ~12 4 8 ~ ~ PCI/US92/OB~-J~
The circuit would include j real-time signal averaging circuits 700, each of said signal averaging circuits being represented by an positive number label k, O ~ k S j - 1. These circuits would be identical to the circuit disclosed above.
The k~ signal averaging circuit 702 includes a k'h signal input port 712 for receiving the k'b one of the j input signals. The input signal received at k~ signal input port 712 represents a value xkn which is to be averaged by k'h signal averaging circuit 702. The k'h memory 716 stores a previous average value akp which was output from k~ signal averaging circuit 702.
The l;lh avera~ing subcircuit 720is connected to clock 710,k'h signal input port 712 and k"' memory 716. The k'h averaging subcircuit 720 provides in response to the timing signals an average value a,~,n. This average is defined as the sum ((M-l)akp + x,~n) divided by M, where M is a predetermined positive number greater than l. Hence average value ak,n is the weighted average of the value x,~.n represented by the ~Ih input signal received at k'h signal input port 712 and of the previous averagre value a,~p stored in k'b memory 716. The k'b averaging subcircuit 720 provides to k~ memory 716 the average value aLn. Finally, k'h output port 714 is ~ ~ ~
connected to k'h averaging subcircuit 720 to generate on k~ averaging circuit output ~ : ;
line 718 a k"' one of j output signals, thereby representing the average value a,~n. `
2 0 ;;
. . .. .
The j output signals are then compared by an appropriate comparison subcircuit 770 connected to each of the j si$nal averaging circuits 702 by one of the -; -j averaging circuit output lines 718.
As discussed above regarding Figure 4, these j averaging subcircuits may be designed to include initialization circuitry.
This comparison circuit may be implemented in a variety of manners corresponding to llle variety of methods of representing signal values, as discloses 3 0 above. The input signals may be digital signals representing the values x~n. In such ~` '"'' '' ~
' "' ~, ~ . .
~ Wo 93/1 ~482 2 ~ 2 ~ 8 ~ S PCI/IJS92/08242 a case the digital k~ averaging circuits 702 may be construc~ed as illustrated in Figure 4 and discuss.ed above. The j output signals of these averaging circuits 702 would be dig,ital signals representing the weighted average values. a",n. Memory 716 could 'oe implemented as a di~ital data registers. Comparison subcircuit 770 may be implemented as a simple digital calculation circuit.
In the alternative, the input signals may be analog signals whose arnplitudes represent the values x,~ n. In such a case the analog k'h averaging circuits 702 may be constructed as illustrated in Figure S and discussed above. The j output signals of these averaging circuits 702 would be analo~ signals representing theweighted average values akn. Memo;y 716 could be implemented as a sample-and-hold-circuit, and comparison subcircuit 770 may be implemented as a simple analog comparator.
l~ach element in the above described embodiments can be constructed ;~
by means of components well known in the appropriate electronic art. Those skilled in those arts can readily design numerous alternative implementations of these embodiments. In addition, other methods of representing data values may be utillæd.
There has been described herein an improved real-time averaging circuit. Various modiflcations to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings.
Accordingly, the present invention is to be limited solely by the following claims.
. .
'
Claims (14)
1. A real-time running average circuit, comprising:
(a) signal input means for receiving an input signal representing a value xn;
(b) register means for storing a signal representing a previous average value ap;
(c) averaging means, connected to the signal input means and the register means, for generating a signal representing a weighted average value an from the received v alue xn and the stored previous average value ap according to:
wherein M is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and (d) signal output, connected to the averaging means, for generating an output signal representing the average value an.
(a) signal input means for receiving an input signal representing a value xn;
(b) register means for storing a signal representing a previous average value ap;
(c) averaging means, connected to the signal input means and the register means, for generating a signal representing a weighted average value an from the received v alue xn and the stored previous average value ap according to:
wherein M is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and (d) signal output, connected to the averaging means, for generating an output signal representing the average value an.
2. The averaging circuit of claim 1 wherein the previous average value ap is an immediately previous average value an-1.
3. The averaging circuit of claim 1 wherein the input signal is a digital value representing the value the output signal is a digital value representing the average value an, and the register means comprise a digital data register.
4. The averaging circuit of claim 1 wherein the input signal is an analog signal representing the value xn, the output signal is an analog signal representing the average value an, and the register means comprise analog sample and hold devices.
5. A method of determining the running average of value of signals in real-time, the method comprising:
(a) receiving an input signal to be averaged representing a value xn;
(b) storing a signal representing a previous average value ap in a register;
(c) generating a signal representing a weighted average value an from the received value xn and the stored previous average value ap according to:
wherein N is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and (d) generating an output signal representing the average value an.
(a) receiving an input signal to be averaged representing a value xn;
(b) storing a signal representing a previous average value ap in a register;
(c) generating a signal representing a weighted average value an from the received value xn and the stored previous average value ap according to:
wherein N is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and (d) generating an output signal representing the average value an.
6. The averaging method of claim 5 wherein the input signal is a digital signal representing the value xn, the output signal is a digital signal representing the average value an, and the register comprises a digital data register.
7. The averaging method of claim 5 wherein the input signal is an analog signal representing the value xn, the output signal is an analog signal representing the average value an, and the register comprises analog sample and hold devices.
8. The averaging method of claim 5 wherein the previous average value ap is an immediately previous average value an-1.
9. An apparatus for monitoring and controlling signal power levels in a radio communications system, comprising:
(a) signal input means for receiving an input signal representing a signal power level value xn;
(b) a register for storing a signal representing a previous average power level value ap;
(c) averaging means, connected to the signal input means and the register, for generating a signal representing a weighted average power level value an from the received power level value xn and the stored previous average power level value ap according to:
wherein M is a predetermined weight value greater than 1, n is a number of samples, and M is independent of n;
(d) signal output means, connected to the averaging means, for generating an output signal representing the weighted average power level value an; and (e) control means, coupled to the signal output means, for controlling one or more transmitters in the radio communications system in response to the weighted:
average power level value an.
(a) signal input means for receiving an input signal representing a signal power level value xn;
(b) a register for storing a signal representing a previous average power level value ap;
(c) averaging means, connected to the signal input means and the register, for generating a signal representing a weighted average power level value an from the received power level value xn and the stored previous average power level value ap according to:
wherein M is a predetermined weight value greater than 1, n is a number of samples, and M is independent of n;
(d) signal output means, connected to the averaging means, for generating an output signal representing the weighted average power level value an; and (e) control means, coupled to the signal output means, for controlling one or more transmitters in the radio communications system in response to the weighted:
average power level value an.
10. The apparatus of claim 9 wherein the previous average power level value ap is an immediately previous average power level value an-1.
11. The apparatus of claim 9 wherein the input signal is a digital value representing the power level value xn, the output signal is a digital value representing the average power level value an, and the register comprises a digital data register.
12. The apparatus of claim 9 wherein the input signal is an analog signal representing the power level value xn, the output signal is an analog signal representing the average power level value an, and the register comprises an analog sample and hold device.
13. A method of producing an average value of a signal in real-time, said method comprising: receiving an input signal representing a value Xn; storing a signal representing a previous average value ap; generating a signal representing a weighted average value an from the received value xn and the stored previous average value ap according to:
wherein M is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and generating an output signal representing the average value an.
wherein M is a predetermined weighted value greater than 1, n is a number of samples, and M is independent of n;
and generating an output signal representing the average value an.
14. The method of Claim 13 wherein said previous average value ap is the immediately previous average value an-1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US798,502 | 1985-11-15 | ||
| US79850291A | 1991-11-26 | 1991-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2124855A1 true CA2124855A1 (en) | 1993-06-10 |
Family
ID=25173565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002124855A Abandoned CA2124855A1 (en) | 1991-11-26 | 1992-09-28 | A real-time running averaging device |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0615638A1 (en) |
| JP (1) | JPH07501431A (en) |
| CA (1) | CA2124855A1 (en) |
| FI (1) | FI942426A (en) |
| WO (1) | WO1993011482A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5475822A (en) * | 1993-11-15 | 1995-12-12 | Motorola, Inc. | Data processing system for resuming instruction execution after an interrupt and method therefor |
| JP3097074B2 (en) | 1997-12-09 | 2000-10-10 | 日本電気株式会社 | Receiver synchronization circuit and reception synchronization method, and receiver and digital communication system using the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1104649A (en) * | 1965-12-27 | 1968-02-28 | Ibm | Continuous averaging system |
| US3809874A (en) * | 1971-07-30 | 1974-05-07 | Finike Italiana Marposs | Device for calculating the mean value of a succession of data |
| US4054786A (en) * | 1973-09-24 | 1977-10-18 | The United States Of America As Represented By The Secretary Of The Navy | Running average computer |
| US4193118A (en) * | 1978-07-18 | 1980-03-11 | Motorola, Inc. | Low pass digital averaging filter |
| US4551817A (en) * | 1983-10-24 | 1985-11-05 | Director General Of Agency Of Industrial Science And Technology | Device for detecting center position of two-dimensionally distributed data |
| DE3509762A1 (en) * | 1985-03-19 | 1986-09-25 | Battelle-Institut E.V., 6000 Frankfurt | CIRCUIT ARRANGEMENT FOR Averaging |
| JP2603134B2 (en) * | 1989-06-06 | 1997-04-23 | 三菱電機株式会社 | Moving average processor |
-
1992
- 1992-09-28 CA CA002124855A patent/CA2124855A1/en not_active Abandoned
- 1992-09-28 JP JP5510085A patent/JPH07501431A/en active Pending
- 1992-09-28 WO PCT/US1992/008242 patent/WO1993011482A1/en not_active Application Discontinuation
- 1992-09-28 EP EP92921904A patent/EP0615638A1/en not_active Withdrawn
-
1994
- 1994-05-25 FI FI942426A patent/FI942426A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0615638A1 (en) | 1994-09-21 |
| JPH07501431A (en) | 1995-02-09 |
| FI942426A0 (en) | 1994-05-25 |
| FI942426A (en) | 1994-05-25 |
| WO1993011482A1 (en) | 1993-06-10 |
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