CA1340968C - Signal processing apparatus - Google Patents

Abstract

The present invention provides a two-system A/D
converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D
converter. Conversely, by using a two-system D/A converter, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A
converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first an d second clocks. A high-precision A/D and D/A
converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP).

Description

13409fi8 - , -Field of the Invention The present invention relates to a signal processing apparatus for performing a coding/decoding end other processes on digital PCM signals, for example, by combining a PCM.CODEC and a DSP (Digital Signal Processor), and more particularly, t.o a technology for realizing a practical signal processing in DSP by using equivalently high precision and inexpensive A/D or D/A converters, and to an output signal clock changing apparatus necessary for performing the above signal processing in synchronization with the same clock.
Description of the Related Art The signal processing apparatus performs a coding/decoding and other processes, for example, on digtal PC6! signals.
Two representative apparatuses are ( 1 ) an A/D
converter for performing a coding between an analog telephone band signal on a subscriber line and a digital PCM signal on a relaying line, and (2) a D/A
converter f:or performing a decoding therebetween.
Generally speaking, when an analog signal is converted t:o a digital signal on a receiving side, it is first sampled at predertermined intervals by using respective sampling signals, and then quantized.
Quantizing is executed to predivide the amplitude of the analog signal into a plurality of ranges so that the analog signals within these ranges can be represented by a corresponding representative digital value. The' resulting quantized signal is transmitted on a transmission line as a coded digital PCM signal.
On the re~~eivirig side, the digital PCM signal is reconverted to an analog signal and reproduced as a telephone :signal such as a human voice.
Durincf the ~quantizing process, a certain range of analog signals can be expressed by the same code, even if sampled values vary to some extent, and on the receiving side the sampled value within the range can be decoded as an analog signal of the same amplitude.
Therefore, there may be a substantial difference, between an analog signal before coding and an analog signal afi=er decoding. This difference is called 134o9s8 quantization noise.
The signal to quantizing noise ratio (S/N) is used to evaluate the quality of the communicated signal. The range presented by one code is called a quantizing step, and when the quantizing step is uniform, quantizing noise is constant. Therefore, if the analog-input-signal amplitude is large, S/N is high, and if it is small, S/N is low. However, for good communication quality, S/N should be maintained constant :regardless of the analog-input-signal amplitude. A nonlinear quantization in which the quantizing step is made small for a small analog input-signal amplitude, and large for a large analog-input-signal amplitude, is generally adopted.
This is called companding. To produce good companding characteristics for a nonlinear quantizatic>n of a telephone signal, a companding rule called u-l.aw i~~ adopted in ~7apan and the united States, and a companding rule called A-law is adopted in other areas, including Europe and parts of Asia.
Recently, 8 bit companding A/D or D/A converters for performing a signal conversion based on the above compandinc~ rule have been produced by many makers.

Although their structures are complicated, they are relatively inexpensive. The ICs are generally called "PCM.CODEC." (PCM
coder/decoder).
On the other hand, when data transmission other than voice signals is c:onduci~ed by using a telephone band signal, a signal processing circuit such as an equalizer, an attenuator or a balancing network as redundant when combined with a converter such as a PCM.CODEC. These circuits are conventionally coristruci~ed as analog circuits. On a coding side they are provided an a stage before an A/D converter, and on a decoding side in a stage after a D/A converter.
Summary of the Invention In accordance with the present invention there is provided a digita:L sign<~1 processing apparatus for use in a digital signal clock changing apparatus for converting a first digital data train synchronized with a first clock, to a second digital data train synchronized with a second clock, comprising:
means for performing a high frequency sampling of the first digital data train to produce a sampled first digital data t rain;
timing difference detecting means for detecting a timing difference between the :First clock and. the second clock;
interpolation means for interpolating the sampled first digital data train based on the timing difference to produce an interpolation output; and means for producing the second digital data train in - 4a -synchronization wja h this second clock based on the interpolation output of said means for interpolating.
In accordance with the present invention there is also provided a s:Lgnal ~orocessing system for use in a digital signal clock chancing apparatus for converting a first digital data system train synchronous with a first clock, and a second digital data systs~m train synchronous with a second clock, comprising:
first digital data system t rain convert ing means for converting the first digital data system train to a converted data train having n times more data than the first digital data system train per unit time, where n is a natural number greater than one;
a high-sampling digital low-pass filter for performing a high sampling on i:he converted data train at a speed n times that of the first clock to produce a sampled data train;
t iming diffe rence detect ing mean; for detect ing a t iming difference between the first ClOCk and the second clock;
interpolation means for interpolating the sampled data train based on the timing difference obtained from said timing difference detecting means to provide amplitude data; and output timing adjusting means for synchronizing the amplitude data with the second clock t:o provide the second digital data syst~=m train.
Brief Description of Drawings Fig. 1 shows a structural view of a conventional example of a digital PCM channel apparatus;

- 4b -Fig. 2 :shows a structural view of the example which is generally used for a digital PCM channel apparatus;
Fig. 3 ~~hows a structural view of the example which is generally used for a digital PCM channel apparatus;
Fig. 4 :>hows a st ructural view of the convent ional example of the clock changing apparatus;
Fig. 5 shows a basic structural view of an A/D
conversion apparai:us a.c~~ording to the first embodiment;
Fig. 6 :shows 'the basic structure of a D/A conversion apparatus according to the first _ 5 embodiment;
Fig. 7 is a table which details the relationship between various numerical values under general u-law;
Fig. 8.is a table which details the relationship ,between values of various portions in an A/D
conversion apparatus;
Fig. 9 shows a view for explaining the operation of an A/D conver~;ion apparatus;
Fig. 10 shows a view for explaining the operation of a D/'A conversion apparatus;
Figs. 11A a.nd 11B are tables which detail the relationship between values of various portions pf a D/A convere;ion apparatus;
Fig. 12 is a detailed block diagram of a preferred structure of an A/D and D/A conversion apparatus according to the first embodiment;
Figs. 13A and 13B show views of basic structures of c:Lock changing apparatuses according to the second embodiment;
Figs. 14A, 14B and 14C show timing charts of waveform~; for various portions of the second embodiment;
Fig. 15 i.s a block diagram of a digital conversion circuit;

13409fig '' _ 6 _ Fig. 16 is a block diagram of a high-sampling digital low pass filter;
Fig. 17 shows the characteristics of an attenuation amount of the filter shown in Fig. 16;
Fig. 18 is an operational flowchart of an interpolation processing unit;
Fig. 1!~ is a block diagram of a timing difference detecting circuit;
Fig. 20 is a detailed block diagram of a digital PCM channel apparatus according to the second embodiment;
Fig. :?1 is a block diagram of a high-sampling digital low-pass filter which is divided into a plurality of blocks;
Fig. 2;2 shows characteristics of an attenuation amount of ~~arious sections in Fig. 21;
Fig. ~!3 shows characteristics of an attenuation amount of l.he whole filter shown in Fig. 21;
Fig. ;24 shows the detailed structure of a timing differencE~ detecting circuit according to the third embodiment;
Fig. 25 show the detailed structure of a timing difference detecting circuit according to the fourth embodiment;

Fig. 26 is an operational flowchart of an interpolation processing unit according to the fourth embodiment;
Figs. 27A and 27B are operation timing charts of the fourth embodiment;
Fig. 28 is a. structural.view of an output timing adjusting circuit according to the fourth embodiment;
Fig. 29 is am operation timing chart of an output timing adjusting circuit.
Fig. 1 show:c a conventional digital PCM channel apparatus which can be: realized as a combination of the above circuits and a PCM.CODEC.
PCM.CC~DEC 1 comprises an A/D converting unit including a low-pass filter (LPF) 7 and an A/D converter 8, and a D/A
converting unit including a D/A converter 10 and a LPF 11. A/D
converter 8 and D/A converter 10 conduct data conversion based on 8-bit N-law comL~anding. LPFs 7 and 11 limit the frequency range of the analog input and output signals to a frequency band which can be expressed by a sampling 8 _ frequency, namely a frequency band up to 1/2 the sampling frE~quenc~y. As described above, PCM.CODEC 1 integrally forms a low-pass filter in a chip. As a result the cost of coding/decoding portions can be reduced.
Hybrid transformer 3 divides an analog telephone band signal (ana.log data) transmitted on a 2-wire subscriber line 2 into a transmitting signal and a receiving ;signal.. Equalizers 4 and 13 correct~the frequency-.Loss characteristics of signals in 2-wire subscriber line 2: or 4-wire tansmission path 9 within a telephon~a band. .Attenuaters 6 and 12 correct the signal-loss caused, during propagation along a line.
Balancing network 15 adjusts the impedance of hybrid transformer: 3 in order to reduce leak (echo-back) of signals from th~a receiving side to the transmitting side, thE: leak being caused by an impedance mismatching in hybrid transformer 3. Amplifiers 5 and 14 adjust the signal levels. Setting and controlling of the above circuits is conducted electrically by a remote control of a center (station) not sh~~wn, as designated by the dotted line in Fig.l. This control is generally called a remote provision.

The above circuits 4,6,12,13 and 15 increase the communication quality. However, when they are analog circuits, they are large and the cost of the apparatus as a whole becomes high. ~ Provision for remotely setting a. plurality of analog circuits becomes complicated.
However, DS~Ps (Digital Signal Processor) have started to become widely used in various fields, and LSIs of DS'~Ps can be obtained at a low price. The Performance. of D;SPs has increased annually, a portion of which are subjected to a conventional analog process. This is also because the scale of .the hardware c:an be reduced by a DSP process. Use of a DSP suppresses the effect of deviations caused among various kinds of products and in the manufacturing process, to a minimum value, although the deviations in the manufacturing process have a large effect on products in an analog circuit. Further, only a modification of an installed firmware can facilitate a change in a process operation. Based on this technology, a nits conventionally subjected to an analog process are replaced by a DSP in the field of telephone band signal processing. Namely, it is desired that thE~ aforementioned equalizer, attenuator, _ ,o _ and balancing network be replaced by a DSP.
Fig.2 shows the structure of a digital PCM
channel apparatus, in which the process of the above respective circuit is conducted by a DSP. In Fig. 2, . portions designated by the same reference numbers as in Fig. 1 p<~rform the same function as the portions in Fig. 1. As shown in Fig. 2, DSP 16 is provided on the digital. signal side of PCM.CODEC 1 , and the same function as the impedance control of hybrid transformer 3, which is conducted in balancing network circuit 1_'i in :Fig. l, can be realized by DSP16.
Therefore, the impedance of hybrid transformer 3 is fixed at a constant value as is conceptually represented by resistance value R in Fig. 2 and an occurrence of signal leakage is allowed. Coarse attenuators 17 a.nd 18 perform a rough adjustment of signal level in the 3dB range of analog signal, and also have a. preprocessing function.
As shown in Fig. 2, DSP 16 is preferably combined with PCM.CODEC1 which is available at a low cost.
However, mere combination of DSP16 and PCM.CODEC 1 cannot realize a coder and decoder apparatus with a desired performance. This is because of the recited S/N ratio. According to a u-law companding by ~134Q968 - " -PCM.CODEC, a digital signal coded on a transmitting side is transmitted to a receiving side through a transmission path without suffering any modification, and is decoded on the receiving side following the same companding rule as on the transmitting side and the u-law comp,anding is a kind of code conversion rule determined based on the above condition.
Therefore, when DSP processing is applied t.o a digital signal after an A/D conversion, a quantizing noise instinctivESly occurring only upon coding is also produced upon decoding. Thus, in order to raise the communicai~ion quality the number of quantizing bits must be made as large as possible, and the respective quantizing steps made as small as possible, thereby suppressing quantizing noise to a minimum value.
Most currently available PCM.CODECs perform an eight bit quantizat.ion, and the accuracy of this quantizati~~n is relatively low. Therefore, there is a problem that deterioration of .communication signal S/N cannot be avoided if a PCM.CODEC currently on market is merely combined with a DSP.
In order t:o solve the above problem of S/N
deterioration, consideration is given to use of a quantization apparatus with a smaller quantizing step than an 8-bit quantizing apparatus, which can maintain the same step size up to a high level, as a converter corresponding to A/D converter 8 and D/A
converter 10 in Fig. 2. For example, use of a linear converter performing 16 bit linear quantization can be considered. A linear converter for about 15 bits may be sufficient, depending on the degree of signal processing performed by the DSP but, considering that PCM.CODEC based on the 8 bit a -law companding has a resolution 'which is similar to that of a 14-bit linear converter, a resolution of about 16 bits may be necessary.
An A/D and D/A converter having a high resolution such as 15 or 16 bits has a more complicated circuit and a larger scale than PCM.CODECs currently on the market. Therefore 16 or 15 bit A/D or D/A converters are extremely disadvantageous in respect of cost.
Further, a PCM.CODEC is installed with a low-pass filter and the above-recited linear converter with a high resolution does not have such filter. Thus, it has to be provided with a new low pass filter, thereby causing a great cost increase and increasing the chip area.
Next, where a digital PCM channel apparatus is constructed by combining the A/D and D/A converter with the D;3P, a technology considered to enable a DSP
to perform processing similar to the aforerecited equalizer, attE~nuator and balancing network, as . explained below.
A general ;structure prior art considered as a digital PC:M channel apparatus based on the above structure will again be shown in Fig. 3. Here, hybrid transformer 21, A/D converter 23 and D/A
converter 24 pE:rform the same functions as those represents:d by the reference numbers 3, 8 and 10, respectively, in Fig. 2. The impedance of hybrid transformE~r 21 can be maintained constant, as in Fig. 2. 2-wire subscriber 20 and 4-wire transmission path 30 are also similar to those represented by the reference numbers 2 and 9 in Fig. 2. Preprocessing circuit 22 is shown by including amplifier 5, coarse attenuator 17 and LPF 7 in Fig. 2 and post-processing circuit 25 is represented by combining LPF 11, coarse attenuator 18 and amplifier 14 of Fig. 2. Although it is abbreviated in Fig. 2, it sometime performs the process of emphasizing a high frequency component of an analog signal in order to raise the quality of a communication signal. In contrast, post-processing circuit 25, in some cases, performs a process in which characteristics of signals emphasized on~the transmitting side return to the appropriate process.
In Fid. 3, input signal SIN converted to digital - data by A/I) conv~=_rter 23 receiving PCM signal RIN from 4-wire transmission path 30, is input to DSP 19. In DSP 1 9, tr;~nsmi:~sion level setting - equalizer 27 and receiving level setting~ equalizer 28 are realized as firmware and perform the same operation as equalizers 4 and 13, rind attenuators 6 and 12 in Fig. 1. Namely, with reg~ird to the above input signal SIN and receiving PCM signal RIN, a loss of frequency characteristics of signals on 2-wire subscriber line or 4-wire transmission path 30 is accurately corrected within a telephone band, and a loss of signal level caused by a line is accurately corrected.
At this time a part of a signal advanced from post-processing circuit 25 to subscriber line 20, is turned to input DSP 19 through hybrid transformer 21 20 such that it is included in input signal SIN making it necessary for the component entered into DSP 19 to be cancelled,. Therefore, the abave component is produced from recE~iving output signal ROUT in precise balance circuit ~'.9, and this is added to input signal SIN at adder 26 (actually, this is substraction) thereby cancelling the above component.
This process is performed to obtain a difference between processed output signal ROUT i.e. a receiving system signal, and input signal SIN i.e. a transmitting system signal, and to bridge a receiving system and a transmitting system.
A digital transmission system including the digital PCM channel apparatus of Fig. 3 has a transmission speed of , for example, 64 Kbit/sec and operates in synchronization with an 8KHz clock. As far as it is not a complete dependent synchronization network, in Fig. 3 a receiving system circuit such as D/A converter 24 operates in synchronization with a receiving clock extracted from received PCM signal RIN and a transmitting system circuit such as A/D
converter 23 operates in synchronization with a transmitting clock produced within a channel apparatus not shown. In. this case, a receiving clock is 20 obtained lay dividing a master clock of the other terminal station, and a transmitting clock is formed by dividing a master clock of the own station.
Therefore , bot.h transmitting and receiving clocks have an indicated frequency of 8KHz but, as they do - 16~ -not use the same master clock, their frequencies are slightly d:iffere:nt in practice, and this difference is around 10-'~ at the maximum.
The difference of 10-4 means that, when transmitting system data is input 10000 times, the receiving :system data becomes '10001.
This oesults in sampling timings of received PCM
signal RID1 and input signal SIN, which are input to DSP19, always differing slightly. Therefore, even if a receiving signal component included in input signal SIN is intended to be cancelled by an output from precise balance circuit 29 to which a received PCM
signal RIIJ is input into adder 26, the signals at different times are subjected to the addition.
Moreover, when the difference is 10-q at BKiiz clock data. out running phenomenon occur at a rate of 1 timing peo. 1.25 seconds. Thus, the data at the time is lost.
Therefore, it is necessary to match one clock with the other clock. In this case, receiving PCM
signal RIN is a signal which has already been sampled on the transmitting side and the receiving clock thereof already exists on the transmitting side. In order to receive received PCM signal RIN, the 13409fi8 receiving clock i.s needed. Thus, the receiving clock is used as a transmitting clock.
Receiving PCM signal RIN comes from a transmitting.terminal station through many repeater stations. Thus, some fitter is added to the received PCM signal RIIN through respective stations.
Therefore, received PCM signal RIN already includes large j ittE~r. Thus, if it is used as a transmitting clock it is transmitted through many relays before it reaches the other terminal station, and thereby increases the amount of fitter, greatly deteriorating the communication quality. Therefore, when a clock generator is provided in both terminal stations and it is intended to maintain the same communication quality, a:~ in the case where these clock generators are designed to~ synchronize accurately with each other, the distance which causes fitter becomes the distance of going and returning, namely twice the one-way distance. Therefore, the relay distance is limited to 1/2 the ordinary relay distance.
An echo canceler cancels echo signals included in transmii~ted signals, the echo signals being formed by signals advancing to a subscriber through hybrid transformer. 21 being turned back. The echo canceler _ ,8 _ 134Q9fi8 produces suitable replica echo signals based on received signals, and subtracts them from the signal being transmitted,. This performs a process of bridging a transmitted signal and a received signal, thereby causing a problem similar to the above case.
To solve the. above problems, a digital-signal clock-changing method is necessary. In this method, a digital PCD1 channel apparatus as shown in Fig. 3 operates D/A converter 24, A/D converter 23 and Precise balance circuit 29, in synchronization with a receiving clock. This enables a transmitting signal obtained from these~signals to again be synchronized with a transmitting clock generated by the clock generator of the own station. The transmitting signal is thereby produced as output signal SOUT.
In this case, it is preferable to achieve good communication quality and to be able to miniaturize the apparatus.
Fig. 4 show:; a block diagram of a conventional clock chancing method. In Fig. 4, the first clock system digital data 34 are converted to analog data by D/A converter 31 'which operates in accordance with the first clock 35. Then, after the analog data is converted to data which is continuous with time, _ 19 _ through analog to w pass filter 32, the output from low pass filter 32 is converted to the second clock system digital data 37 by A/D converter 33 which operates at the second clock 36, thereby achieving a clock chancing.
However, in the apparatus shown in Fig. 4, input digital data is reconverted to analog data by D/A
converter 31 and the analog data is again converted to digital data by A/D converter 33, thereby resulting in a production of a quantizing noise, and deteriorat~.ng the communication quality. There is a further problem, that the apparatus shown in Fig. 4 needs an analog low pass filter 32 which, unlike a digital circuit, cannot be miniaturized even if it is integrated..
Summary of the Invention The present invention is made in consideration of the above situation and its first object is to provide a high precision A/L) and D/A converter by combining a PCM.C~DEC of a low conversion precision and an inexpensive A/D and D/A, thereby providing a high precision .4/D and D/A converter and realizing a practical signal processing within the DSP. The 134~9fi8 second object of the present invention is to perform a clock change in a digital signal without using an analog si<~nal when the clock change of the digital output signal.i~; necessary, as a result of performing a signal processing realized by the high precision A/D
and D/A converter both on the receiving and transmitting sides and performing a signal processing synchronized with the same clock.
To achieve the above object, the present invention provides an A/D converting means for shifting an amp:Litude value of an analog input signal and individually performing a conversion of the analog input signal. This is done by using respective first and second A/D converters and arithmetically operating an average value of respective conversion results.
Thus, it provides higher conversion precision digital output signal than a single A/D converter. The first A/D converter systme of the A/D converter means comprises, for example, first amplifier 38, first companding A/D converter 39, and first linear converter 42, as shown in Fig. 5. The second A/D
converter system comprises, for example, a second amplifier 40, second companding A/D converter 41, and second linear converting unit 43, as shown in Fig. 5.

The above arithmetic operation of the average value can be conducted by an arithmetic operation unit ~ 44, for example, as shown in Fig. 5.
Next, the present invention individually converts digital input signals by first and second D/A
converter systems, detects a quantizing error caused by the first D/A converter system, adds the quantizing error to a. digital input signal input to the second D/A convsarter system and mixes the respective conversion results of the first and second D/A
converter systems in a predetermined ratio. Thus it provides a higher conversion precision analog output signal than a single D/A converter system. The: first D/A converter system in the D/A converter means comprises a first companding converting unit 45 and first companding D/A converter 49, for example, as shown in F'ig. 6,. and the second D/A converting system comprises second companding converting unit 46 and second corn pandi.ng D/A converter 50, as shown in Fig.
6' Quant:Lzing error from the first D/A converting system is detected by detecting unit 49, for example, as shown in Fig. 6 and is added to the second D/A
converter system by using noise adding unit 48. The respective conversion results of the first and second D/A converter systems are mixed in a predetermined ratio by the first and second amplifier 51 and 52 and adder 53, as shown in Fig. 6.
Further, the present invention provides a . digital-sictnal-c:Lock changing or transferring means by performing a hicth sampling of the first digital data system trains, detecting a timing difference between the first clock and the second clock, and producing second digital data synchronized with the second clock to an interpolation processing from data subjected to high sampling based on the timing difference. In the digital signal clock changing means, means for performing a high-sampling of the first digital data system train comprises data conversion circuit 63 and high sampling digital low-pass filter 64, for example, as shown in Fig. 13A. The means for detecting timing differences between the first clock and the second clock comprises timing difference detecting circuit 66,for example, as shown in Fig.l3A. Further, this means is disclosed in the circuit shown in Figs. 19, 24 and 25, for example. In addition means for performing the above interpolation processing comprises interpolation processing unit 65, for example, as shown in Fig. 13A, and more concretely, is disclosed as processes shown in Figs. 18 and 26.
Further, the present invention discloses that the above recited high-sampling digital low-pass filter 64 is divided into a plurality of blocks as shown in Fig.
13B and an output timing adjusting circuit relating to timing difference detecting circuit 66 as disclosed in Fig. 28.
The structure of the above invention is realized, for example, b~y two PCM.CODECs and one DSP as a coding/decoding apparatus for a digital PCM signal.
Namely, the A~~D converting means and the D/A
converting means can be realized by using a portion of a function of two PCM.CODECs and one DSP which perform 8-bit compa.nmding coding and decoding, and the digital signal clock changing means can be realized by using a function of the 1DSP.
Therefore a small inexpensive structure comprising two PCM.CODECs and one DSP can realize high-precision A/D and D/A converting processing.
Therefore, signal processing devices such as an attenuator, an equalizer and a balancing network, which are conventionally realized by an analog circuit, can be realized by digital signal processing using one DSP. In this case, to prevent a timing deviation between signals processed on the transmitting side and those processed on the receiving side, the above signal processing is conducted in synchronization with a receiving clock of a digital receiving signal received from an external line.
Therefore, it becomes necessary on the transmitting side connected t.o a line, to enable a transmission digital output signal synchronized with the receiving clock to be changed to be synchronized with a transmitting clock, and this processing is more easily realized by a digital signal clock changing means in the DSP.
As shown above, the present invention can perform high precision A/D and D/A conversion with ease by using a signal processing apparatus formed by an inexpensive PC'M.CODEC and a DSP. It can therefore perform with one DSP, a signal processing which conventionally necessitates a large scale analog circuit. In a<9dition, it can realize a digital-signal clock-changing means necessary for signal processing by using a signal processing in the same DSP. In this cage, the present invention realizes a timing difference detecting means within a digital signal clock changing means in an extremely simple ~ 340968 circuit, by extremely simple processing.
Therefore, the present invention can integrate an 'apparatus while maintaining a high communication quality, thereby extremely miniatuarizing the whole apparatus, and can realize an inexpensive, low-energy consuming,. highly reliable signal-processing apparatus.
First Embodiment Firstly, the first embodiment will be explained. This embodiment is cha~racter.ized in that the accuracy of A/D and D/A
conversion are improved by using two sets of PCM.CODECs based on 8-bit N-law companding.
Fig. 5 shows the basic structure of an A/D converting apparatus accordj.ng to the first embodiment of the present invention. In F~lg. 5, analog signal Ain is commonly applied to the first and second A/D converting systems. In the first A/D
converting system, the signal Ain is amplified kl times in first amplifier 38 and is converted to the first PCM code P1 by the first companding A/D converter 39. In the second A/D converting system, signal A:~n is .amplified k2 times in the second amplifier 40, and is further converted to the second PCM code P2 by the second companding A/D converter 41. k1 and k 2 are real numbers satisfying the relationship k1 x k2 =1.

At least first linear convertin g unit 42, second linear converting unit 43 and arithmetic operation unit 94 are formed in the DSP. First and second linear converting units 42 and 43 convert respective first= and second PCM codes P1 and P2 into first and second linear codes L1 and L2. Arithmetic operation unit 44 performs an arithmetic operation on these linear codes L1 and L2 to derive an average value (L1 +L2)/2, and this average value becomes digital conversion output DpUT. As will be recited later by :referring to Fig. 12, processes based on functions of the precise balance circuit, equalizer, and attenu~ator are applied to the digital conversion output.
Fig. 6 she>ws the basic structure of the D/A
converting apparatus relating to the first embodiment of this :lnveni=ion. In Fig. 6, after the above respective processes are performed in the DSP (later recited i:n Fig. 12) digital ;signal Din, input as a linear PCM code, is applied to first companding ~ 34o9sa conversion unit 95 and is converted to the first companding PCM code P3. The first companding PCM
code P3 is input to the first D/A converting system.
This system comprises first companding D/A converter 49 for converting code P3 to the first analog signal A1, and fir;~t amplifier 51 for amplifying the signal A1 k3 times.
At least second companding converting unit 46, detecting unit 47 and noise adding unit 48 are formed in the DSl? in addition to converting unit 45.
Detecting unit 47 detects a quantizing noise N in the first companding PCM code P3. Detecting unit 47 comprises linear converting unit 47-1 and subtracting uni t 47-2 in Fig. 6.
Quantizing noise N is applied to noise adding unit 48. l:t is then multiplied by k4 and added to digital sic3nal Din. In Fig. 6, noise adding unit 48 comprises ~~mplii:ying unit (gain k4) 48-1 and adding unit 48-2. The output of noise adding unit 48 is converted to thE~ second companding PCM code P4 by second comF>andind converting unit 46. The code P4 is input to the second D/A converting system. This system com prises the second companding D/A converter 50 which convert: code P4 to the second analog signal _ 28 _ A2, and second amplifier 52 which amplifies the signal A2 k5 times. The relations between k3, k4 and k5 are detE~rminE~d to satisfy the conditions k3 + k5 =
1, and k4 - k3/(1 - k3), where k3, k4 and k5 are all positive reel numbers.
Respeci:ive amplification outputs of the first and second ana7_og signals, A1 and A2, obtained by the above process are added at adder 53, thereby producing analog convE~rsion output Aout An operation of the first embodiment shown in Figs. 5 and 6 will be explained.
Firstly, the A/D converting apparatus of Fig. 5 is explainec9. Supposing that the amplification ratio k1 of the first. amplifier 38 satisfies k1 - k ' (therefore, the amplification ratio k2 of the second amplifier 40 s;~tisfies k2 -- 1/k) and that the amplitude of analog signal Ain is a. The signal Ain is amplified to provide ak and a/k, which are applied as input to corresponding companding A/D converters 39 and 41, thereby providing the first and second PCM
codes P1 and P2 of digital values. These PCM codes are subjected to companding and are not real numerical values. ThE~refore, the PCM codes cannot be a subject of a computation and they are modified. Therefore 134p968 _ 29 _ these code: are returned to linear codes L1 and L2 representing thEa real numerical value by linear converting units 92 and 43. In this state, arithmetic operation unit 93 performs an arithmetic operation to obtain an averagE~ value (L1 + L2)/2. As described in detail later, in addition to a group of 255 or 256 output values which may be output as 8 bit companding CODEC, an intermediate value within two adjacent output values may be produced from the average value, thereby re:~ultimg in an increase in the kinds of output values. This means an increase in the resolution of the A/D converter. The reason is that the linear codes. L1 and L2 differ from each other because of the multiplication ratio of k and 1/k and, if L1 is the samE~ value L as L2, then the value L is the output value and, if L1 deviates from L2, the intermediai:e value between L1 and L2 appears as the output value.
The above o Aeration will be explained in more detail by referring to an example.
In the A/D converter of Fig. 5, the amplification ratio k1 of the first amplifier 38 is set at K (=1.01 ), and the amplification ratio k2 of the second amplifier 40 is set. at 1/k(=1/1.01). An 13409fi8 explanation of this embodiment adopts a u-law as an example of a com~panding rule. Even in case of an A-law, the effect of the present invention does not differ.
Fig. 7 shows a relation between respective values under a general li-law. In Fig. 7, the range of the analog volt,~ge input (a column of linear input in the drawing) added to companding A/D converters 39 and 41 of Fig. 5 is set, for example, -8158 to +8158 and 28 (=256) times the output value (OUTPUT VALUE) are set within the input: analog voltage range. The unit of the analog input voltage is, for example, milli-volts.
In accordance with the respective value of the analog inputs (li.near inputs in the drawing), an 8-bit digital code is determined as a a-law PCM output, and it outputs from the A/D converter. In Fig. 7, to simply recite an explanation, only positive linear input is sYiown, only the complete fourth segment is recited and intermediate values in the other segments are omitted. Thc~ segment means a range of respective bent lines when a u-law characteristic is expressed by a plurality of bent lines.
An 8-bit digital code of the above u-law PCM
output is ;simply a symbol used for a classification 134~9fi8 and does not mean an actual amplitude value.
Therefore, the above u-law PCM output is converted to the corresponding digital value of 0 to 8031 (which corresponds to the output value (OUTPUT VALUE) in Fig.
7) by first and second linear converting units (u/L
converting units) 42 and 43 i.n the DSP of Fig. 5.
Thus, the digital. value has 19-bit accuracy.
As the first and second linear codes L1 and L2 of Fig. 5, numerical data corresponding to a.k and a/k appear, as explained above. For an 8-bit companding A/D converter, the kind of respective output level of the linear codes L1 and L2 are respectively merely of 255 or 256 types., However, the actual analog inputs are a continuous value within the range of -8158 to +8158, and the number of kinds of analog inputs is 16316 even when the integer portion only is considered,. Because of the difference between the kinds of output levels of first and second linear codes L1 and L2 and the continuous value of analog input, a quantiz:ing noise as described above occurs.
Generally :peaking as an evaluation item of an A/D
converter and a :D/A converter the above recited S/N
(in units of dB) is used. For example, for an 8-bit companding A/D (D/A) converter for a telephone signal, the output obtained by inputting a sine wave signal of 1010IIz to the A/D converter is input to the D/A
converter. The D/A converter provides output including a; signal component, namely, a signal of 1010Hz. This signal component, represented by an "S" frequency component other than the 1010 Hz included in the output from the D/A converter, is represented by N (noise). A large part of the noise comprises quantizing noise caused by representing a certain range oi: analog input by an output value formed by the central value of the analog input.
Therefore, a large S/N means a small quantizing noise and a small waveform distortion. In other words, to increase S/N it is necessary to decrease quantizing noise, and to decrease quantizing noise it is necessary t.o increase the output value from the A/D (D/A) converter and to thereby decrease the length of the quamtizing steps.
According to the embodiment shown in Fig. S, use of two sets of 8--bit companding A/D converters 39 and 41 enables the above output value to increase as shown below. Further, use of a commercially available PCM.CODEC enables. a signal processing apparatus to be realized at a lower cost than with one set of higher ~3409fi8 quantizing~ precision (or more than 8-bit) A/D
converters,, even if two sets of 8-bit companding A/D
converters 39 and 41, are utilized.
In Fic~. 5, the output value of the f first and second linear codes L1 and L2 are respectively D(a~k) and D ( a/k)., If 1~; is not determined as k=1 .01 , but as k =1 , the linear codes L1 and L2 naturally have the same output value. As is shown in the preferred embodiment, if k=1.01, the first amplification ratio 1 .01 is slightly different from the second amplification ratio 1 /1 .01. Thus, a k becomes different from a/k. If the difference between a k and a/k is small anti a k and a/k is within a range of respective rows shown in a column of a linear input shown in Fig. 7, the output value D (a~ k) is coincident with that of D (a/k). In contrast, if the difference .between a k and a/k is outside the range of repsecti.ve rows, the output D (a~ k) is different from that of D(a/k). Namely, where k~1 but is a value near 1 , or where one of them is entered into the adjacent range, the output value corresponding to the adjacent range is produced and D(a~ k)~D(a/k). In the former ( coincidence) an average value of ak and a/k, namely, 1/2 x a{(k+1/k)} is positioned near the center ~34o~s8 of the range of respective rows of the linear input shown in Fig. 7. In the latter ( non-coincidence) the above average value appears near the boundary between adjacent ranges of respective rows.
In the arithmetic operation unit 44 in Fig. 5, the average value of the first and second linear codes L1 and L2 is set at Dout =1 /2 ~(D(a ~ k)+D( a/k)}
through an arithmetic operation, and in the latter case explained above, the output Dout becomes an ~0 intermediat:e value between the output value of one row and that of its adjacent row. In the former case, namely, when a k and a /k are within the same range, L1 and L2 become the same, thereby enabling the average value of L'I and L2, or the output Dout to become the same value as this respective output value. The output value shown in the column of the output value (OUTPUT
VALUE) in Fig. 7 and a new output value mid-way between adjacent output values are obtained, thereby achieving the same result as a high resolution A/D
20 converter.
Fig. B shows the relationship among respective values in. an A/D converter and shows concrete numerical values of an amplitude a of analog signal Ain, output value a k of the ffirst amplifier 38, ~~4o~sa output value a/k of the second amplifier 40, D( a k) (the value of the first linear code L1), D( a/k) (the value of the second linear code L2), and 1/2{D(a~k) +
D(a/k)~ (d:igital conversion output Dout) with regard ' to the apparatus shown in Fig. 5. It should be noted in Fig. 8 that, as shown on the right side, the output values shown by Q1, Q2, Q3 and Q4 appear as new output values in addition to ordinary quantizing output values Q2', Q3' and Q4' of companding A/D converters 39 and 41. Their relationship is shown more comprehensively in ,Fig. 9. Respective ones of Q2', Q3' and Q4'', for example, in Fig. 9 correspond to those in Fig. 7. With regard to D(a~ k) and D(a/k), if a is positioned within a region A, quantizing output of the above two values is commonly Q3'. Thus, the digital conversion output Dout is also Q3', and if a is positioned in a region B, the respective quantizing outputs are divided into two parts Q4' and Q3'. Thus, the digit~~l conversion output Dout becomes an intermediate value, Q3. In a case where a is positioned in the region C, respective quantizing outputs are divided into Q3' and Q2'. Thus, the digital conversion output Dout becomes an intermediate value Q2.

1340968 ' As described above, conventionally, there are 255 kinds of output values, and in this embodiment the number of kinds of the output values doubles and the size of the quantizing steps (0) halves. Then, quantizing noise power (/.12/12) becomes 1/9 and S/N
increases t~y 6dB. When DSP processing is applied to the digital conversion output Dout, deterioration of S/N is suppressed to a minimum value.
In thia case, as shown in F'ig. 9, suppose that an upper value is obtained by subtracting 1/4 of a quantizing step value q from the value of the upper boundary (shown by a solid line) between two adjacent quantizing output values q of companding A/D
converters 39 and 41 (Fig. 5), and that a lower value is obtained by adding 1/4 of a quantizing step value q to the value o1. the lower boundary. These values then constitute new boundary values (i.e. decision values shown by the dotted line), and the width of a possible range of respective newly formed output 20 values become the same, which is the most preferable.
Thereby, an amplification ratio k can be calculated as follows.
k~=,1 + (quantizing step) / ( 4 x ( output value ) .
For a companding A/D conversion, the quantizing 134~968 step is made large in a region where the output value is large ( namel;,r, the quantizing noise is large).
Thus, the ratio of. (quantizing step / I ouput value) ) of the companding A/D conversion is generally closer to the constant value than that obtained by the linear A/D converter. If this ratio is constant, then the value of i~he above k can be determined.
However, <~s is clear from Fig. 7, the ratio of (quantizin<1 step / 'output value)) is not always constant. A part of the 8th segment has a value of 256/8031 (=3.180 and .a part of the second segment has a value of 4/33(=12$), and the difference between these values is large. Therefore, it is necessary to determine the most appropriate value experimentally. Therefore, according to the result of the experiment using u-law 8 bit companding A/D
converter, k=1.025 is the most appropriate value.
Next, an operation of the D/A converter in Fig. 6 will be Explained. In order to simplify the explanation, it: is supposed that the amplification ratio of the firat amplifier 51, is k3=2/3. Therefore as described above, k4=k3/(1--k3)=(2/3)/(1-2/3)=2, k5=1-k3=1/3. Under this condition, if the value of digital signal Din of Fig. 6 is S, Din is input to the first companding D/A converter 49 through the first companding converter 45 and is then converted to the first analog signal A1. Thereafter it is multiplied by 2/3 (=k3;1 by the first amplifier 51, the output of which is 2/3D (R). Then the first companding PCM code P3 is input to linear converting unit 47-1 and reconverted to a linear signal. Therefore, the output value (OUTPUT VALUE) D (8) corresponding to the digital signal Din (_~) on the input side can be recognized as a digital value. The difference between the value ~ of the digital signal Din and output value D(S) is arithmetically operated in subtracting unit 47-2. Then a volltage E corresponding to a quantizing noise N produced from companding conversion unit 45 through D/A conve:rter 49 can be obtained. Namely, E = Q - D ( ~ ) . .. ( 1 ) The above E is multiplied by 2(=k4) by amplifying unit 48-1 and is then added to input signal Din.
Thereafter it i.s input to the second companding conversion unit: 46. Namely, S + 2E is input to conversion unit 46 and is rewritten using the above equation ( 1 ) as follows.
R + 2E. = DIGS) + 3E ...(2) Where ~E I is smaller than 1/2 a quantizing step 134(1968 (expressed as q) corresponding to or closest to output value D(R) because, if the voltage E of the quantizing noise N is larger than 1/2 a quantizing step, D(S) becomes an adjacent different output value. As shown ' in Fig. 7, if D(Q) is an output value 359, ~ of a linear input is 351 to 366, and thus, the quantizing error is less than ~8. This is less than 1/2 a quantizing step 16 of a segment 4. Therefore 3 ~E~ in equation (2) is less than 3/2 times the nearest quantizing step q of D(S).
Value D(S + 2E) of the second analog signal A2 obtained through a process of the second D/A converter system of Din-~t:he second companding conversion unit 46 + D/A converter 50 is classified in accordance with the following conditions ('~ ~-1Q where +1..5q > 3E z 0.5 q:
D ( ~ ~~ 2E) - D (S) + q ...(3) ~ where +0..5q > 3E Z -0.5q:
D ( Q -E 2E) - D (I3) ...(4) ~ wherE~ -O.Sq > 3E ? -1 .5q:
I) ( (3 -E 2E) - D (f3) -q ... (5) D(S) +q is an output value adjacent to the upper side of the output value D (a), and D (!3) -q is the output value adjacent to the lower side of the output value D

13409fi8 ( Q). The output value is multiplied by 1 /3 (=k5) by the second amplifier 52 in Fig. 6, and is then added to the aforemeni=Toned output 2/3 D (Q) of the first D/A converter system in adder 53. Based on this output 2/3 D (Q) and the result of the above equations (3) - (5), the added output Aout is classified in accordance with 1=he following conditions 1~
1~ where +1.5q > 3E ? 0.5q:

2/3D((3) + 1/3{D(S) + q}=D(S) + q/3 ...(6) Q where +0.5q > 3E ? -0.5q:
2;/3D(S) + .1/3D(S) =D(~) ...(7) where -0.5q > 3E ? -1.5q:
~'./3D(li;l + 1/3{D((3) - q}=D((3) - q/3 ... (8) The relationships shown in the equations (6) -(8) are shown in Fig. 10. For a conventional structure in which only one set comprising a compandinc~ con«ersion unit and a companding D/A
converter i.s pro~aided, all the values of input digital signal Din within a range designated by region A of Fig. 10 is represented by an analog signal D (I3).
Therefore, if digital signal Din is positioned within region B, quant.izing error is small, but if it is in region C o~_- D, it becomes large. In contrast, in the above embodiment, quantizing error can be decreased as ~34o9s8 described below.
Condi lion ~) in the above equations ( 3 ) or ( 6 ) is rewritten as 0.5q ~ E ~ 0.5q/3. Namely, this shows a range of voltage E of a quantizing noise of value ~ of digital signal D_~n and representative value D(I3) under condition C). This shows that the value ~ of digital signal Din in F:ig. 6 is within region C in Fig. 10.
Namely, deviation of S from the value D(S) represents the value within the range is about 1/3 that of quantizing step q. In such a case, as shown in the aforementioned equations (3) and (6) the value of analog signal Ac~ut is obtained by adding q/3 to the representative value D(S). In other words, if the value ~ of digital signal Din in Fig. 6 falls within a range C of Fig. '10, the output of first companding D/A
converter 49 in Fig. 6 is D(~) and the output of second corn panding D/A converter 50 is D( g) + q as expressed in the above-recited equation (3).
Therefore, the respective outputs of first and second amplifiers 51 and 52 are 2/3D(a ) and 1 /3 {D( S) + q } and these outputs are added in adder 53, thereby producing analog signal Aout of {D(S) + q/3} as is clear from the equation (61 of Fig. 10. Conventionally, if the value ~ of digital input signal Din is within a range A in Fig. 10, analog signal Aout is expressed merely by D(g ). In t:he present embodiment, if S is positioned within a range C which is included in a range A, ~°~out '~an be expressed by {D( S) + q/3}, thereby reducing quantizing error included in S and Aout- As a result, the quanti.zing error between the analog signal Aout and the value ~S in the range C
becomes small.
In condition ~3, shown by the aforementioned '10 equations (5) or (8), the relationship is completely opposite t.o that of the above condition 1~ . The analog signal A~~ut obtained by subtracting q/3 from the representative value D (f3), and the quantizing error between analog signal Aout and the value ~ of the region D becomes small.
For condition ~, shown by the aforementioned equations (4) or (7), the value ~ is close to the representative value D (Q). This value is produced as analog ;signal Aout without modification.
20 As described above and shown in Fig. 6, the above quantizing noise produced from the first D/A
convertinc3 system comprising a route of Din -~ first compandin~~ converting unit 45 -~ first companding D/A
converting unit 49, is superimposed on an input signal ~3~o9sa of the second D/A converting system comprising the route of Din + second companding converting unit 46 second comp~anding D/A converting unit 50.
Therefore, the quantizing noise from the first D/A
converting system is almost cancelled and the second D/A converting system produces a maximum quantizing noise of q/2. At the output of adder 53, the output from the second ID/A converting system is multiplied by 1/3 (=k5) by second amplifier 52. Thus, the produced quantizing noise becomes q/6 at maximum, namely, 1/3 the conventional qu~ntizing noise.
In the embodiment shown in Fig. 6, the output value becomes 3 times that obtained with only an ordinary comp,anding D/A converter, and this embodiment can provide a companding D/A converter of an equivalent high resolution corresponding to, for example, ~~.5 buts (256 x 3 '_, 29'5).
The above operation will be explained in more detail by referring to an example. In an explanation of this embodiment, a a -law is adopted as a compandin~~ rules as in Fig. 5, and the effect of the present invention does not differ from this embodiment even if an A-law companding rule is adopted.
Figs. 11A and 11B show the value of respective portions of the D/A converting apparatus shown in Fig.
6 and correspond to Fig. 7 regarding the A/D
converting apparatus. Figs. 1 1 A and 1 1 B show amplitude 13 digital signal Din, first companding .PCM
code P3, value D (a) of analog signal A1 (digital expression), quantizing noise N (digital value), the value of two times voltage E of quantizing noise N
(digital v~~lue), a digital output from adder 48-2 ( Q
+2E), second cornpanding PCM code P4, second analog signal A2 and analog converting output Aout { =(2/3 x A1 ) + ( 1 /3 x A2 ) }, respectively, in Fig. 6. As shown in Figs. 11A and 11B, respective analog converting outputs Aout appear at equal intervals of 5.333 between respective analog converting outputs.
Companding D/A converters 49 and 50 in Fig. 6 completely correspond to companding A/D converters 39 and 41, and respective quantizing outputs appear at equal intervals of 16 between respective outputs for segment 4, for Example, as shown in the output value OUTPUT VaILUE) in Fig. 7. Therefore, according to Figs. 11A and '11B, the output intervals of analog converting output Aout can be divided into small steps which are 1/3 those of an ordinary D/A converter, and the number of output values thus becomes 3 times that 13409fi8 of an ordinary D/A converter, by combining D/A
converters 49 and S0.
In the above embodiment, the case of k3=2/3 is shown. Ho«ever, for k3=1/2, calculations similar to those of aforementioned equations (3) - (8) are conducted, and the number of output values from analog cormerting output Aout are double and are equal to those of a 9-bit companding D/A converter, although an 8-bit companding D/A converter is adopted.
For k~~=3/4, the number of output values becomes 9 times, and is equivalent to a 10-bit companding D/A
converter, although an 8-bit companding D/A converter is adopted..
Fig. 12 shows a detailed circuit diagram of the preferred structure of the A/D and D/A converting apparatuses according to the present invention. The preferred structure means that it can be constructed by using two sets comprising a commercially available DSP, a commercially available PCM.CODEC, and a few other elements. According to this structure, a practical, high-resolution A/D and D/A converter apparatus can be realized by merely adding an inexpensive and commercially available PCM.CODEC.
This can be done more efficiently than when a high 13~+09fi8 resolution A/D and D/A converting apparatus is constructed using the aforementioned Fig. 2 structure. A hybrid transformer, amplifier and coarse attenuator are omitted as shown in Fig. 12.
In Fi<a. 12, two companding A/D converters 39 and 91, as in Fig. 5, and two companding D/A converters 49 and 50, as in Fig. 6, are provided by two companding A/D convert=ers and two companding D/A converters being installed in first PCM.CODEC 54 and second PCM.CODEC
55 in which a pair of A/D and D/A converters is integrated. In. Fig. 12, arithmetic operation amplifier 56 provides an amplification ratio k1 (Fig.
5) by using registers R~ and R2 (k1=R2/R~) and registers R3 and R4 in the next stage form an amplifier ratio k2 (Fig. 5). If k1 and k2 are k and 1/k, respectively, as described above, k~R3/(R3 + R4) - 1/k, thereby determining the values of R3 and R4.
A similar analysis will be applied to an operational amplifier 57 of a D/A converting system and an amplification ratio k3 (Fig. 6) is determined as R7/R6, and k5 is determined as R7/R5. Thus, analog conversion output Aout is obtained from ((R7/R6) x A1}
+ {(R7/R5,1 x A2} (A1 and A2 are recited in Fig. 6).
In the previous example, it is assumed that k3=2/3 and k5=1/3, and in this example, it is determined that R6 =1.587 and R5=3R7.
The DSP comprises the above recited first and second linear converting units 42 and 93, an arithmetic; operation unit 44 (which calculates the average level) in Fig. 5, the first and second companding converting units 45 and 46, linear converting unit 47-1, subtracting unit 47-2, amplifying unit 48-1 and adding unit 48-2 as shown in Fig. 6. LS.ne 60 in Fig. 12 is a leak cancelling line for preventing signals from leaking into a line in a 2-wire - 4-wire converter (hybrid trans), not shown in Fig. 12.. DSP function units 58 and 59 respectively comprise a function of an equalizer (EQL) and a function of an a.ttenuator (ATT), for example. These lines, connected to DSP function units 58 and 59, are respectively connected to linear/u converting unit (L/u) 61 and u/7Linear converting unit (u/L) 62, and are thus c~~nnected to a transmission path.
As explained above, the first embodiment provides A/D and D/A conversion apparatuses which combine an A/D and a D/A converter with a DSP, and the high resolution input and output of an A/D and D/A
converter which is required by a DSP can be achieved 13409fi8 by merely adding inexpensive amplifiers (amplifiers 38 and 40 in Fig. 5 and amplifiers 51 and 52 in Fig.
6) by utili::ing an arithmetic operation function of the DSP without modifying the A/D and D/A converters.
The second ~mbodim~ent Next, t:he second embodiment of this invention will be explained. The present embodiment is characterized as a clock of a digital signal processed within a DSP changed, for example, from the first clock (receiving. clock) to the second clock (transmitting clock) with signals kept in digital form.
Figs. 13A and 13B are basic block diagrams of the second embodiment of the present invention. Fig. 13A
uses a high-sampling digital low pass filter and Fig.
13B uses a high-sampling digital low pass filter which is divided into a plurality of blocks.
As shown in Fig. 13A, data strings of the first clock pass data coinverting circuit 63, and the number of data per unit time is n (n> 1 , and is an integer) times the original data. The output of converting circuit 63 is input to interpolation processing unit 65 through nigh-sampling digital low pass filter 2 which operates at a sampling rate n times that of the ffirst clock.
Interpolation processing unit 65 forms and outputs conversion data synchronized with the second block by using an interpolation method, based on timing difference T between the first and second clocks. The timing difference is detected by timing difference detection circuit 66.
As she>wn in Fig. 13B, high-sampling digital low pass filt~ar 64 (Fig. 13A), which operates at a sampling speed n times that of the first clock, is divided into a plurality of blocks 67, 68 and 69. The ratio of the sampling speed between adjacent blocks is made an integer, and the last stage block 69 operates at a sampling speed n times that of the f first clock, and the sum of the loss characteristics of respective blocks 67, 68 and 69 is made the same as that of the original filter fi4 of Fig. 13A.
Data conver~~ion circuits 70 and 71 for outputting the same amplitude data whose number is equal to the ratio (1C2/~Z3) of the sampling speed between adjacent blocks with regard to one item of input data are provided between respective blocks of a high-sampling filter. Data conversion circuit 63' to which the 13409~g ~
- so -first clod; data trains are input, is set to produce the same arnplitu~de data whose number is equal to the ratio ~,1 =n~ R,2~R,3 of the sampling speed of the first stage block 67 to that of the first clock per unit time, as c~~mparE~d with the number of original data.
This will be explained later.
In Fig'. 13B, where the sampling rate of the first stage block 67 is the same as the rate of the first clock, namely, fa (~,1=1), then data conversion circuit 63' is not ;necessary.
The c~enera~l operation of the above basic structure will bE~ explained. Figs. 14A to 14C are time charts of a waveform of various portions of Fig. 13A.
Hereinafter, the frequencies of the first clock and the second clock will be designated as 8KHz.
In Fic~. 13A,, data conversion circuit 63 receives data values Sn, Sn+1~ Sn+2~ Sn+3w~ of a sine wave of, 3.004KHz ,for example, at time of the first clock tn~ tn+1' tn+2' tn+3~ ~~~ as shown in Fig. 14A. The number of data pE~r unit time is n times, for example, 8 times, that o1: the original data as shown in Fig.
14B. Then, the output of data conversion circuit 63 is applied to high-sampling digital low pass filter 64 which operates ai. a sampling speed of 64KHz, which is 8 times fa:~ter than the first clock. A cut frequency of the filter 64 is the same as that allowed for the data system train of the first clock and is (8/2)KHz -4KHz for voice signals. Therefore, the above filter 64 produces such a signal as shown in Fig. 14C.
The time interval of these signal trains becomes 1 /8 those of the signal synchronized with the first clock.
Even if we try to obtain the data values at the time of thE~ second clock Tn-1 , Tn, Tn+1' Tn+2' Tn+3' ..~ by using respective data values Sn, Sn+1' Sn+2 Sn+3' ~~~ at the times of the first clock tn, tn+1' tn+2' tn+3' ~~~ ~~Y Lagrange's interpolation method, the time interva:Ls between respective data are wide and the variations of the data values are large.
Thus, the data values at the time of the second clock Tn_~, Tn... are difficult to obtain. If the time interval oi~ the first clock is made 1/8 that of the signal synchronized with the first clock, as shown in ZO this embodiment, the time interval between respective data becomes narrow. This decreases the variation in data values within a time interval between two timings, for example, between adjacent timings, and enables the data values at the time of the second - s2 -clock, Tn-.~ , Tn, Tn+1 ~ Tn+2~ Tn+3~ ~~~ to be obtained.
As shown in Fig. 19C, the timing difference between the firat and second clocks is obtained by timing difference detection circuit 66, and is input to interpolation processing unit 6s. Interpolation processing unit 65 can obtain the data value F at a time of the second clock Tn+~ by using a period 'ra of the first clock, the difference DT between the time of the second clock Tn+~ and the 1/8 time ~0 interval which exceeds the time Tn+~, and the data values Fm-~ and Fm of the 1 /8 time intervals at both sides of the time of the second clock Tn+~, and also using the follo wing Lagrange's interpolation formula, F- (Fm. { ~ Ta~/n - ~T ) + Fm._~ ' ~T, ~ ~Ta/n~.
As described above, the data values F at times of the second clock Tn-~, Tn, Tn+1 ~ Tn+2~ Tn+3~ ~~~ are produced as. digital data values at the second clock.
According to the above approach, a digital signal is not converted to an analog signal. Thus, a 20 quantizing noise is not produced and the apparatus is subject to all digital processings, thereby being miniaturized as an integral circuit.
A high same>ling digital low pass filter 64 of Fig. 13A operate; at a repetition frequency of 8 times the sampling frequency of the original data .
Namel~~, as 8 data are input and 8 data are output during a repetition period of a sampling frequency of the original data, the amount of processing becomes 8 times that achieved when it operates at the sampling frequency c~f the original data.
If the order or degree of the high-sampling digital low pass; filter 69 is 6 and the order of the delay equalizer for suppressing the group delay distortion occurring in the filter is 2, thereby totally providing the 8 order filter, the equivalent order- number in respect of a processing amount is E~4.
A digital filter performs one calculation of a following ~~iffenence equation with regard to every second order.
yn=a xn + b a .yn-2 xn-1 + c xn-2 _.
d .yn-1 _ Thus, the num ber a multiplication is per period of 5 and 160 per period in the 69th order. Therefore, other progr~~m s are performed by the DSP in processes of more th,~n 220 conversion steps including a data processing.

Even if a high speed digital signal processing unit in which the processing time per step is 100ns, only 1250 steps at maximum can be used when the period is 125 u~; (8KHz), and if ,220 steps selected from among there 12_'>0 steps are assigned to a filter calculation in the clock changing method, a distribution of time to other processings decreases.
Thus, it i=~ not preferred.
Therefore, as shown in Fig. 13B, the filter is divided into a plurality of blocks and a process which can be performed at a relatively low sampling speed is processed by a filter of a low sampling speed, and the amount of processing may be greatly reduced.
A process in a delay equalizer is related to a pass band, and a frequency delay of more than the cutoff frequency, for example 4KHz, need not be considered. It can be conducted by filter block 67 which operates at the sampling speed of the original data BKHz.
Next, the cutof f frequency component f rom 4KHz to BKHz is performed by filter block 68 which operates at a sampling speed of l6KHz. A cutoff of a frequency component from 8 KHz to 32KHz is performed by filter block 69 in the last stage which operates at the same sampling speed, 69KHz, as that of the high-sampling ~34dg68 digital low pass filter 64 of Fig. 13A.
In this example, the sampling speed of the first stage block. 67 i;> the same as that of the first clock, and data conversion circuit 63' is not necessary.
Data conversion circuit 70 is for outputting two data of the same amplitude regarding input data on the input side of filter block 68. Data conversion circuit 71 is for outputting four data of the same amplitude regarding one item of input data on the input side of filter block 69.
As constructed.in the manner described above, respective blocks 67 and Ei9, having sampling frequencies of 8KEiz and 64KHz, are formed of a filter of the second order, and block 68, having a sampling frequency of 16K1;iz, is constructed of a filter of the fourth order. Then, the total number of multiplications per period becomes 5 x 1 + 5 x 2 x 2 +
5 x 2 x 4 =65. From the relationship of the order ratio with the sampling ratio, the number of multiplications for each second order is 5. This greatly reduces i~he amount of calculation.
In the apparatus constructed as shown in Fig.
13B, described above, the number of output data from filter block 69 is 8 times the original data and is ~ 34098 the same ass that of the filter of Fig. 13A. The interpolation processing unit 65 can perform a change from the l:irst clock to the second clock in the manner shown in P'ig. 13A.
The structure and operation of respective parts of Figs. 13,4 and 13B will now be explained in detail.
Fig. 15 shows a block diagram of data conversion circuit 63 of Fic~. 13A, Fig. 16 shows a block diagram of high-sampling digital low pass filter 64, Fig. 17 shows the amount of attenuation of the filter in Fig.
16, Fig. 18 shows.a flow chart of a program of interpolat:LOn processing unit 65 shown in Fig. 13A, and Fig. 19 shows a principle block diagram of timing difference detection circuit 66.
In the respective figures, 72 is a memory, 73 and 109 multip:Liers, 108 a 10-bit counter, 110 a 10-bit register, '111 a switch, 74 to 77 adders, 78 to 87 data delay memories, and 88 to 107 coefficient multipliers.
The data conversion circuit in Fig. 15 produces the same data 8 times per period. It receives, for example, 1 E.-bit .amplitude data at intervals of, for example, 8KEiz, and writes them in memory 72 in synchronization with the first clock, and produces the data 8 times per period by using a read clock obtained by modifying i:he first clock 8 times, using multiplier 73.
Fig. 16 shows an example of a high-sampling digital low-pass filter having a cut-off frequency of 3.8 KHz and comprising four sections, each containing a two-order digital filter. Six orders of the above filter construction cut off the frequency in the 4 to 60KHz band. The other 2 orders form a delay equalizer for equalizing group delay time distortion.
The whole filter operates at a sampling speed of 64KHz and performs 8 filter calculations per period of 8KHz.
The attenuat=ion characteristic is shown in Fig.
17. The gain at around 3.4KHz is 2 - 3dB because the RZ/NRZ correction is performed at this point, as an input si<3na1 is subjected to NRZ processing.
The filter may be a large scale transversal filter.
An interpolation processing is shown in the operation flow clhart of Fig. 18. When, for example, the same data is input 8 times for i (as shown in a Fig. 14C) at. a period of first clock, m of Ta ~ m/8 (m=1 to 8) i.s sequentially increased from 1 at step S1 ~ 340968 '-try comparing time difference T between the first clock and the second clock. When the sign of /1-r _ r~ ~n,/8 _ T becomes positive, the c,ornparison processing is stopped, and the difference t1T between time Tn+1 of the second clock: and the time of 1/8 time interval which exceeds Tn+~, and the value of m are obtained.
In Fig. 14C, it is understood that m=5.
At step S2, the data value F of time Tn+1 of the second clock is obtained from data values Fm-1 and Fm when m=4 and m=!5, based on the following Lagrange interpolation formula, F = CFm { (Ta/n) - DT) +Fm-1~ ~T~ : (Ta/n).
As described above, the data value can be obtained ai: the time of the second clock Tn-~, Tn, Tn+1 ~ Tn+2~ Tn+3~' '~~ as shown in Fig. 14A.
Fig. 19 shows the basic structure of the time difference detecting circuit. The embodiment will be explained :in detail by referring to the third and fourth embo~~iments.
The time difference detecting circuit of Fig. 19 multiplies the first clock by 210 using multiplier 109. To provide' input data to 10-bit counter 108, it is reset at a rise of the first clock. Thus, its count valuE~ shows a position in time obtained by _ 59 _ equally di~riding the period of the first clock by 210=1024. Thus :if count value is, for example, the 512, the tune shown to be exactly in the middle is of the first clock.
Therefore, at a timing of the second clock, switch 111 is turned on to obtain the value of counter 108 into 10-bit register 110, and to thereby obtain time difference T between the first clock and the second cloc)c, at a resolution obtained by dividing a period by 1 024.
Next, it is explained where the clock changing method of the present invention is applied to the PCM
channel apparatus shown in Fig. 12.
Fig. 20 shows a block diagram of a digital PCM
'- channel apE~aratus based on the second embodiment.
Parts designated by the same reference numbers as those in the prior art device shown in Fig. 3 and the base structure of the second embodiment shown in Fig.
13A perform the sa me functions.
In Fig" 20, receiving clock RCLK reproduced by receiving timing reproducing circuit 115 from received PCM signal ;SIN, a,nd transmitting clock SCLK produced by transmitting clock generator 114 of its own station, exist a;s a clock timing. Receiving clock 134A'968 RCLK is in put to receiving register 116, D/A converter 24, A/D converter 23, DSP 118 and transmitting and receiving timing difference detecting circuit 66, and most of the functions operate based on receiving clock RCLK. On i=he other hand, transmitting clock SCLK is input to transmitting register 113 and transmitting and receiv»ng timing difference detecting circuit 66.
Therefore, in the circuit of Fig. 20, input signal SIN from a subscriber is picked up by receiving clock RCLK, and receiving PCM signal RIN from the other station is written into receiving register 116.
The receiving PCIH signal RIN is read out by receiving clock RCLK and is converted from a PCM signal of a a -law companding rule to 16-bit linear data, for example, by u,/L converter 117, and is input to receiving level setting ~equalizer 28. Transmitting level setting~ equalizer 27 on the transmitting side and receiving :Level setting~equalizer 28 on the receiving side perform respective corresponding processes. Precision balancing circuit 29 bridging transmitting and receiving system performs a process on receiving clock RCLK, thereby preventing .the aforementioned problem from being produced by a clock shif t.

134p9fig Output signal SOUT should be output on transmissi~~n of clock SCLK. Thus, the above recited clock changing process is, conducted by the above recited d~ita conversion circuit 63, high sampling ' digital low pass filter 64, interpolation processing unit 65 and (transmitting and receiving) timing difference: detecting circuit 66 with regard to an output data system of transmitting level setting' equalizer :?7. Thf~ signal is thus converted so that it has an amplitude whose timing matches that of transmitting clo~~k SCLK. It is then converted from a linear signal to a PCM signal according to a u-law companding~ rule by L/u converter 112, and written into a transmitting register. Data are read out from this register on transmission of clock SCLK, and transmitted in a fitter-free state to a multiplication unit, not shown, as output signal SOUT.
In the above construction, data conversion circuit 63, high sampling digital low pass filter 64, and interpolation processing unit 65 are digital, and can thus be integrated and miniaturized as digital signal processor (DSP) 118 together with other digital circuits. As (transmitting and receiving ) timing difference detecting circuit 66 is also digital, it '34.pg68 _ can be integrated and miniaturized as interface LSI119 together with other digital circuits. Obviously other methods may be uaed for dividing the circuit shown in Fig. 20 for. the purpose of an integration. In Fig.
20, A/D converter 23 and D/A converter 29 are constructed normally and if they are constructed as shown in the first embodiment of Fig. 12, they provide a great effect.
Next, the structure of a circuit for dividing a high-sampling digital low pass filter into several sections to decrease the number of arithmetic operations will be explained in detail.
Fig. 21 shows the structure of the high-sampling digital blocks of Fig. 13B divided into several ' sections. Fig. 22 shows the amount of attenuation of respective sections shown in Fig. 21, where (4~ correspond to filter blocks - ~ in Fig. 21.
Fig. 23 shows the whole attenuation amount of a filter of Fig. 21.
In Fig. 21 , 1 20 to 1 23 designate adders, 1 29 to 135 data delay mE~mories, and 136 to 154 coefficient multipliers.
Filter block ~ in Fig. 21 is a delay equalizer and is related only to a passing band, and delay 134fl968 characteri~;tics at a frequency higher than 4KHz in the cutting-off range are not questioned. Thus, it operates at: the ;sampling speed (BKHz) of the original data, and the data conversion circuit ( 63' in Fig.
13B) is not: required in the initial-stage.
Filter block (2~ cuts off frequency components from 4KHz to BKHz and operates at a sampling speed of l6KHz. Inthis case, the data conversion circuit (as shown in F'ig. 1.38) for outputting two pieces of the data of th~~ same amplitude in response of one piece of input d~~ta, is required on the input side.
Fi lter block (3) cuts of f f requency components from BKIIz to 16KIIz and operates at a sampling speed of 32KHz. In this. case, the data conversion circuit (shown in Fig. 13B) for outputting two pieces of data of the same amplitude in response to one piece of input data, is also required on the input side.
Filter block ~ cuts off frequency components from l6KHz to 3;zKHz and operates at a sampling speed 20 of 64KHz. In this case also, the data conversion circuit for outputting two pieces of data of the same amplitude in response to one piece of input data is required on the input side.
The number of data output from filter block is 8 times that of the original data for the filter shown in Fi.g. 1 6. Filter block ~ thereby performs a change from first clock to second clock using the interpolation. processing unit ( 65 in Fig. 13B).
In this case, the number of multiplications per period in f filter block is 5 x 1 , as the number of coefficient multipliers is 5. The number~of multiplicat:ions per period in filter block n is 8 x 2 as the number of coefficient multipliers is 8 and the sampling speed is l6KHz. The number of multiplicat:ions per period in filter block ~ is 3 x 4, as the number of coefficient multipliers is 3 and the sampling speed is 32KHz. The number of multiplications per period in filter block ~ is 3 x 8, as the number of coefficient multipliers is 3 and the sampling speed is 64KHz. Thus the total number of multiplications per period is 57. It will be understood that this is much less than 160 in case of the filter shown in Fig. 16 As described above, in the second embodiment it is possible to .change the data system trains of the first clock to the data system trains of the second clock using the digital form of data kept, thereby eliminating the quantizing noise which causes a problem in the prior art example shown in Fig. 4. In the present invention, communication quality is not lowered and this embodiment can be greatly miniaturized by :integration.
This embodiment can be integrated and miniaturized togE~ther with other digital circuits, and is made inexpensive.
The Third E;mbodinnent The third embodiment will now be explained. This embodiment. describes in detail timing difference detecting c:ircuii= 66, shown in Figs. 13A and 20 in the second embodiment, and also describes the structure~of transmitting register 113 shown in Fig. 20.
The presenit embodiment is based on the basic structure shown in Fig. 19. According to the principle shown in Fig. l9 and described above, a counter is made operative after 10-bit counter 108 is reset by the first clock (called receiving clock RCLK
hereinaftE~r). The content of the above counter is latched in 10-bit register 110 at the rising edge of the second clock (called transmitting clock SCLK
hereinafter), thereby detecting a timing difference r.
According to the above pr inciple, time when the above latch is conducted at a rising edge of transmitting clock SCLK, for example, a timing difference i is produced. When T is input to interpolation processing unit 65 (in Fig. 1 3A or Fig.
20) in sign,~l processor 118, which operates according to receivin<1 clock RCLK, the time is not constant from the viewpoLnt of signal processor 118. Namely, the timing difference z is input to the beginning or end of the interpolation process (shown in Fig. 18).
Therefore, a buffer circuit is required for a time adjustment.
When t:he period of transrnitting clock SCLK is slightly shorter than that of receiving clock RCLK, the timing difference has to be detected twice during a period of RCL1K. Conversely, when the period of RCLK is sl.ightl_y shorter than that of SCLK, the rising edge of SCLK does not occur within the period of RCLK.
When the pE:riod of transmitting clock SCLK is slightly shifted from that of receiving clock RCLK
there exist: three cases, in which the number of input data per period is 0, 1, and 2. In addition, the time of occurrence of the input data is not constant.
Therefore, a buffer circuit is required between transmitting and receiving timing difference detecting circuit 66 and =signal processor 118. The present embodiment. discloses a detailed circuit for transmitting and :receiving timing difference detecting circuit 66, including a buffer circuit.
Fig. 24 shows a detailed circuit structure for transmitting and receiving timing difference detecting circuit 66 within the data PCM channel apparatus in the second embodiment shown in Fig. 20.
In Ficl. 24 ~, -bit counter 1 55, latch 1 56 and multiplier 157 are respectively the same as 10-bit counter 10l3 (R=10), 10-bit latch 110 and multiplier 1 09 in Fig. 1 9. The f first clock and the second clock respectively correspond to receiving clock RCLK and transmitting clock SCLK.
When viewed from the signal processor side (118 in Fig. 20) the time at which timing difference data t is produced :From latch 156 is not constant as described above. Thus, a case can occur in which data of the previous period has not yet been processed, when the process of obtaining data of the present period based on receiving clock RCLK is occurring. Thercsfore, two buffer circuits 159 and 160 are provided in parallel as shown in Fig. 24.

Switches SW1 - SW6 are provided on the input side, and are switched depending on whether the cycle number of receiving clock F:CLK is odd or even. Therefore, when data from latch 156 is written into one of buffer . circuits 159 and 160, the other is connected to the signal pro~~esson, thereby enabling data to be read out. Signals obtained by dividing the frequency of receiving ~~lock RCLK into 1/2 the frequency of the receiving clock by frequency divider 158 is used as a control signal for switching an even number/odd number cycle.
As described above, when the transmitting period clock SCLK is slightly shorter than that of receiving clock RCLK, the timing difference must be detected twice during one period of RCLK, and before completing processing of the data of the previous period, the following data may be input. Therefore, respective buffer circuits 159 and 160 have a two-stage structure comprising respective memories ~1, ~2, 161 and 162, and the content of these memories is selected b;r selector 164.
In the above two-stage structure, data corresponding t~o the address pointer is required to designate how many pieces of data are input per - ~34pg68.-period, and input data number memory 163 for storing the data is provided in respective buffers. As described above, where the period of receiving clock RCLK is slightly shorter than that of transmitting clock SCLK, the rising edge of SCLK is not positioned within a period of RCLK, and during such period, signal processor 118 in Fig. 20 cannot perform a process in interpolation processing unit 65. To make this judgment, the above input data number memory.163 is necessary. Memory 163 is reset by a control circuit, not shown, at the immediately preceding timing, every time the memory is connected to the latch circuit.
Signal processing unit 118 in Fig. 20 performs the following operation in correspondence with transmitting and receiving timing difference detecting circuit 6E~ (Fig. 20) shown in detail in Fig. 24.
Firstly high-sampling low pass filter 64 operates continuous'Ly. Next, interpolation processing unit 65 obtains a timinct difference T from transmitting and receiving timing difference detecting circuit 66 at every period of respective receiving clocks RCLK,and performs the fo:l lowing processes. Namely, when the contents of input data number memory 163 in the currently selected buf fer circuit ( 1 59 or 1 60 ) in rig. 29 is observed to be 0, it is unnecessary to output tr<~nsmitting output signal SOUT and an interpolation processing is not. conducted. When the number of input data is more than 1, they are input sequentially from the corresponding memory 161 or 162 through an operation of selector 164. Then, interpolation processings are conducted, the number being the same as that of data, thereby producing output signal SOUT.
Next, an opcsrat.ion of transmitting register 113 in Fig. 20, corresponding to the above timing difference detecting processing and interpolation processing will be explained.
Output. signal SOUT is arithmetically operated and produced by signal processing unit 118, which operates in synchronization with receiving clock RCLK.
Therefore, signal processing unit 118 produces an output almost in synchoronization with receiving clock RCLK. As ~~lready described, output signal SOUT should be transmitted outwardly in synchronization with transmitting clock SCLK. Thus, a buffer circuit is required f:or time adjustment of output signal SOUT.
This is a function of transmitting register 113 in Fig. 20. The condition required for a register is as follows.
Data input time from signal processing unit 118 to transmitting register 113 is independent of the output time of output signal SOUT from the register.
The periods of receiving clock RCLK and transmitting clock SCLK are slightly different, and they are always moving relative to each other. Thus, over a relatively long period, they inevitably sometimes coincide. I:n this case, while data is being transmitted outward from transmitting register 113, a write process is conducted in the register, thereby damaging transmission data. Therefore, while output signal SOUT is output externally from transmitting register 113, data should be prevented from being transmittE:d from signal processor unit 118 to the register 113.
The number of output data from signal processor unit 118 is 0, 1, or 2 per period. As to output timing, when two data are output per period they are continuou sly output without a large time difference.
However, when a zero-data period is interposed between two two-data periods, the next data will be produced after two periods have passed. Therefore it _ ~2 _ is necessary to adjust the timing to output data at a time interval that matches transmitting clock SCLK.
In order t.o satisfy the latter condition, transmitting register 113 in Fig. 24 comprises a plurality of registers which are not described in detail. Further, a judging circuit for determining which data. are output of the data stored in said plurality of rE~gisters, is also provided. This judging circuit may make a judgment, using the number of data received from signal processing unit 118, and the register number from which data are output in the previous period, as a parameter. Therefore a counter is provided for counting the number of received data.
In order to satisfy the former condition, a control circuit for preventing input data from entering a counter when the counter is reset, or when the result of counting is being transferred, is provided in transmitting register 113.
A detailed circuit relating to transmitting register 1'13 will be explained in the following fourth embodiment.
The Fourth Embodimen The fourth embodiment will now be explained.

134096a This embodiment describes in detail (transmitting and receiving) timing difference detecting circuit 66 in Figs. 13A and 20, and also recites interpolation processing unit 65 and transmitting register 113 in Fig. 20. In this embodiment, an operation relation between the first clock (receiving clock RCLK) and the second clock (transmitting clock SCLK) with regard to transmitting and receiving timing difference detecting circuit 66 is reversed to that of the third embodiment, thereby making the circuit structure simpler than in the.third embodiment.
Fig. 25 shows a block diagram of transmitting and receiving timing difference detecting circuit 66 and Fig. 26 snows an operation f low of signal processor 118 in Fig. 20 i.n the second embodiment.
In Fig. 25, the system clock of the second clock produced i.n the data PCM channel apparatus in Fig. 20 is frequency-divided by frequency divider 165 to provide 1~'2L tiimes the frequency of the second system clock, thereby producing the second clock of transmitting clock SCLK. This portion corresponds to transmitting clock generator 114 in Fig. 20. As is opposite to the apparatuses in Figs. 19 and 24, the references clock, namely, receiving clock RCLK, in signal pro~~essing unit 118 is used as a latch signal for latch circuit 167 in Fig. 25, and the second clock of the system clock synchronized with SCLK is used as a counting operation clock for L-bit counter 166.
gy enabling an operation of latch circuit 167 to be synchronized with receiving clock RCLK, an input time of timing difference data to signal processing unit 118 is determined to have the same relationship as signal procE~ssing unit 118, which operates in synchronization with. RCLK.
Another feature of this embodiment is that interpolai:ion processing unit 65 (Fig. 20), which operates as shown in Fig. 26, determines the number of interpolation data to be operated wihin a period based on receiving clock RCLK as follows. As the period of transmitting clock SCLK differs by a maximum of 10-4 from that of the receiving clock, a timing difference between the transmitting clock and the receiving clock 20 varies wii:h period, gradually increasing or gradually decreasing. Whcare the number of data per period with reference to RCLK is 0 or more-or-less 2, the value of the timing difference between two adjacent periods changes greatly. Interpolation processing unit 65 uses the se characteristics and can recognize the number of .interpolation data to be calculated within a period from a variation between a timing difference of the present period and a timing difference of the previous ~~eriod.
As constructed above, a buffer circuit becomes unnecessa:cy in timing difference detecting circuit, thereby enabling the circuit scale to be greatly reduced.
An operation of transmitting and receiving timing difference detecting circuit 66 and an interpolation process in interpolation processing unit 65 will be explained in more detail with regard to the fourth embodimeni~, shown in Figs. 25 and 26.
In F~~g. 25, a system clock with a frequency 2L
times that of transmitting clock SCLK is input to L-bit counter 166. for a count operation. For example, if L=10 <~.nd the frequency of SCLK is 8KEiz, the frequency of the system clock becomes 8.192 MHz. In this case counter 166 indicates a count value from 0 to 2L-1. This count value is returned to 0 in accordance with a period of transmitting clock SCLK, thereby being reset at every period of transmitting clock SCLK.

When vthe count value is latched at a rising edge of receiving clock RCLK, the value of the clock is a timing difference based on transmitting clock SCLK

when the period. of 2L.
transmitting clock SCLK is Counter 166 can latch the count value without stopping. Thus, the counter is always reset by SCLK
as described above.
The 7Latch data is transmitted to an input register, not shown, in signal processing unit 118 in Fig. 20, by adding an L-bit transmitting clock to latch circuit 167. immediately after the latch operation is completed. Therefore, the time from a latch operation to a transmission is very small and is conducted at a predetermined timing within a respective period, based on receiving clock RCLK. The above transmission operation is thereby conducted in synchronization with receiving clock RCLK.
On the other hand, signal processing unit 118 operates based on receiving clock RCLK, as described above. This means that the difference between the time at which various processes are conducted in signal processing unit 118 and the time at which receiving clock RCLK rises, for example, is constant.
Therefore, the period from the time at which timing 13~096g _ 77 _ difference data is transmitted from latch circuit 167 to signal processing unit 118 to the time at which the timing difference data is actually used, becomes constant. When the length of this period is less than the corresponding period based on transmitting clock SCLK, there is no unused data remaining in an input register when data is transferred from latch circuit 167 to an input= register in signal processing unit 118. Therefore, a buffer circuit is unnecessary.
The o;perati.on of the present invention shown in Figs. 25 and 26 is explained with reference to the timing chart shown in Figs. 27A and 27B.
In Figs. 27A and 27B, the abscissa represents time. In (1~ in Figs. 27A and 27B, t0, t1 , t2, ...are rising edge points of receiving clock RCLK and in ~~ in Figs. 27A and 27B, T0, T1, T2, ... are rising points of transmitting clock SCLK. .
Plot ' ~' synchoronized with timing t0, t1 , t2, ... of receiving clock RCLK among the plots shown in in Fig. 27A is an original item of data synchronized with receiving clock RCLK input to data conversion circuit 63 in Fig. 20. The other plots ' ~' represent an output of high sampling low pass filter 64 of Fig.
20 and correspond to the second embodiment of Fig.

_ 78 _ 14C. In Fig. 14C'., the data are highly-sampled 8 times per period, but in Figs. 27A and 27B, it is highly-sampled 4 times per period to enable a brief explanation. Further in ~ in the figure, plots 'o' ~ represented by S0, S1, S2, ... synchronized with timings T0, T1, T2, ... of transmitting clock SCLK are signal values to be outputted as output signal SOUT
after they are subjected to an interpolation process in interpolation processing unit 65 in Fig. 20 and are changed to transmitting clock SCLK.
Fig. ;Z7A shows the case where the period length (S period) of transmitting clock SCLK is larger than the period. lengi=h (R period) of receiving clock RCLK.
As the difference in period length between SCLK and RCLK is 10-4 at maximum, the timing difference between y and ~ is exaggerated for easy understanding.
L-bit counter clock 166 in Fig. 25 is synchronized with receiving clock SCLK, so the designates value of the counter is 0 at respective timings of tn( n=0, 1 , 2, ... ). At t0, t1 , t2, ... the count value is latched and almost simultaneously transmitted to signal processing unit 118 (Fig. 20).
The count value at this time, namely the timing difference between transmitting clock SCLK and receiving clock RCLK with transmitting clock SCLK made as a reference, is designated by two lines when a latch is performed, as shown by the upward-pointing arrow.
As shown in~4~in Fig. 27A, the timing difference decreases with time until it reaches 0, becomes a maximum at the beginning of the next period, and again gradually decreases. In such a period shown in T1 -T2 or T6 - T7, the arrow shows that two count values are transmitted per period with reference to the period of transmitting clock SCLK. However, from the viewpoint of signal processing unit 118 for receiving a transmi~.sion signal (signal transmitting unit 118 being synchronized with receiving clock RCLK), only a single interpolation process of Fig. 26 is conducted.
In this case the timing difference (count value) at t0 or t6 is very snnall and the timing difference at t1 or t7 is almost equal to the length of one period.
Based on these characteristics it is determined whether the interpolation processing is conducted or not, as described later.
In 5Q in Fic~. 27A, a time when an output signal is output fr~nm output register RO in signal processing unit 118 to register R1 in an external timing ~~4pgfi8 adjusting ~~ircuit (the same as transmitting register 113 in Fic~. 20) is designated by a row mark. An output timing adjusting circuit will be explained later. In Fig. 27A an output signal SOUT at T5 of transmitting clock SCLK is transmitted to signal processing unit 118 after a timing difference between TS and t5 is detected at t5, and an interpolation calculation is conducted to provide S5. This S5 is output to ,gin output timing adjusting circuit at t5,5 (an intermediate time between t5 and t6) after 0.5 of a period. Simi:Larl.y, SOUT at T6 of SCLK is obtained as S6 by detecting a timing difference between T6 and t6 at t6 to transfer the timing difference to signal processing unit118, and a calculation of an . interpolation is conducted, thereby providing S6. S6 is output to an output timing adjusting circuit at t6,5 after 0.5 of a period. On the other hand, the timing difference between T7 and t8 is detected at t8 and SOUT at timing T7 of SCLK is subjected to an interpolation calculation, thereby enabling S~ to be obtained. S7 is then output to an output timing adjusting circuit at t8,5 after 0.5 of a period.
As is~ clea:r from the above, transmitting clock SCLK, cor~:esponding to a timing difference equal to - 8, -almost one period length detected at t1 or t7, does not exist. TherE~fore the output signal SOUT (Fig. 20) need not he output. In Fig. 27A, while transmitting clock SCLK changE~s from T1 to T10 receiving clock RCLK
changes from t0 to t11. Therefore, the above fact means that the output number of output signal SOUT
per unit time is less than that of receiving PCM
signal RIN (Fig. 20), as S period > R period.
Therefore Ll~e trend of timing difference is made to correspond to an output operation of output signal SOIJT from signal processing unit 118 to an output tuning adjusting circuit. Then it is clear that "from the viewpoint of a timing difference determine~~. by a rise of transmitting clock SCLK to a rise of rf:ceivi.ng clock RCLK and a period based on receiving clock RCLK, output signal SOUT should not be output to an output timing adjusting circuit in a period when the timing' difference of the previous period is almo~;t 0 and the timing difference of the present period is about the length of a period". This corresponds to the fact that the interpolation process i;; conducted only once per period at the same timing. The above control is realized according to the opera t: ion f:Low chart of Fig. 26.

Next, Fig. :?7B shows the case where the length of the period (R) of receiving clock RCLK is larger than the length of period (SCLK) of the transmitting clock. In this case, also, for easy understanding, the timing difference between(1~ and U is exaggerated.
Shown in ~), Fig. 27B, the timing difference increases with time until it reaches a length equal to a period, becomes 0 at the beginning of the next period, and again gradually increases. This operation is repeated.
Next output signal SOUT, at T5 of transmitting clock SCLK, is transferred to signal processing unit 118 when the timing difference between TS and t5 is detected at t5 and provided as S5 through an interpolation calculation. It is output to an output timing a~~justing circuit at t5.5 (intermediate between t~~ and t6) after 0.5 of a period. Next, SOUT, at a timing of T6 of SCLK, is transferred to signal processing unit 118 when the timing difference between T6 and t6 is detected at t6, and then provided as S6 through am interpolation calculation. It is then output to an output timing adjusting circuit at t6.5 after 0.5 of a period.
On t:he other hand respective output signals SOUT

are considered at T7 and T8 of SCLK. In this case it can be considered as similar to the case of T5 and T6.
When a timing difference between T7 and t7 is detected at t7,, SOUT at T7 is output to an output timing adjusting circuit as S7 at t7_5 after 0.5 of a period. However in Fig. 278, the counter which starts to count at T7 is returned to 0 at T8. Thus, the timing di!Eference between T7 and t7 is substantially equal to that between T8 and t7, thereby transmitting the value of the timing difference to signal processinct unit 118., Therefore, the output-to-output value of i~he timing adjusting circuit at t7.5 becomes an output signal S8 at the timing T8 of transmitting clock SCL,K. In this case an output S7 at a time corresponding to T7 becomes insufficient.
To compensate for the insufficient output, the present embodiment outputs signal S7 corresponding to T7 to an output timing adjusting circuit before t7,5.
The timing difference value, in this case , is equal to the timing difference between T7 and t7, and can be considered as substantially a period length, because t:he difference between receiving clock RCLK
and transmitting clock SCLK is only about 10-4.
Therefore, when the timing difference trend is made to correspond to thE~ number of signals output from signal processing unit 118 to an output timing adjusting circuit, it is clear that "from the viewpoint of a tinning difl:ercric~e determined by a rise of transmitting clock SCL~: to a rise of receiving clock RCLK and a period relating to a receiving clock RChK, in a period in which the tirnin~l difference of the previous Period i , almost nyr~~l tw a r»riori an~3 t-h~ timing c3iff~rc~nco of the present. period is almost 0, the transmitting signal should be outputted to an output timing adjusting circuit twice and the first output is calculated by making the time difference equal to a period and the second output is calculated by making the time difference equal to 0."
By utilizing the above fact, in this embodiment, the process shown by the operation flow chart in Fig.
26 is carried out at interpolation processing unit 65 in signal processing unit 118 in Fig. 20. The problem of the number of an output signal and the amplitude thereof can be easily correlated when the output signal is applied to an output timing adjusting circuit (=transmitting register 113) from signal processing unit 113.
In F~.g. 26,. the timing difference of the present - 8s -period designated by Tx and the timing difference of the previous period is designated by r b. The length of one pe~_iod t>ased on transmitting clock SCLK is determined as 2L -1 by using a bit length L of a counter. The operation of Fig. 26 is shown as follows.
Interpolation processing unit 6s in Fig. 20 starts to operate at timings t0, t1, t2,... based on receiving clock RCLK, for example, and high-sampling low-pass filter 64 obtains highly sampled processing data of the previous period at these timings. For example, as shown in Fig. 27A, process data (shown by plot' ~' ) in ~ in the same figure are between t4 - t5 at a timing of t:s.
Next, the timing difference data Tx read from transmitting and receiving timing difference detecting circuit 66 (Fig. 20) is written into signal processing unit 118 (Fig. 20), and more particularly into an input register not shown (S1 of Fig. 26).
If ~-b=0 and Tx=~2L-1, the transmitting signal is not outpui~ during the period (S1 -' S2 -~ S3--~ S1 2 in Fig.
26). As described above, this corresponds to a process at a timing t1 or t7 in~ in Fig. 27A.
On the other hand if T b =, 2L-1 and Tx ~_, 0, the 134096a output signal is output twice during the period (S1 ~+ S2 + S~I + S9 -'~ S1 0 + S11 in Fig. 26). For the f first timing, ~~ x - 2L-1 and this is expressed as T=2L-1-'rx by using a taming difference T upon changing the period of receiving clock RCLK to the reference, thereby providing T =0. As is understood trom Fig.
19C, the output, value is no other than F0, thereby enabling the value to be output. For the second timing, ~rx=0 and T=2L-1. In this case the output value becomes F'm, thereby enabling the value to be output. .4s de~;cribed above, this corresponds to a process at: a tuning of t2 or t7 in 1 in Fig. 27B.
Except for the above case, the process advances to follow a route S1 + S2 + S3 + S5 or S1 + S2 + S4 -~ SS.
T=2L-1-Tx is calculated at S5, S6 and S7, and the interpolation processing shown in the second embodiment'. of F'ig. 18 is conducted. The output value obtained at S8 is output as a amplitude value of output signal SOUT. At step S12, the timing difference T x in the present period is changed to the timing difference Tb in the previous timing and used for a process in the following period.
As ~~escribed above, in this embodiment, (transmitting and receiving) timing difference ~~t~pg6~
,_ detecting circuit 66 is constructed such that the timing dif:Eerence is detected using the second clock (transmit:ting clock SCLK) as the reference.
Interpolation processing unit 64 within signal processing unit 118 executes the process shown in an operation f: low chart of Fig. 26. Therefore, by adding an extremely simple circuit structure and a simple logical judgment shown in Fig. 26, important data for changing .3 clock, namely, the timing difference between transmitting clock SCLK and receiving clock RCLK and t:he control of the number of data output per period, can be completely input to a signal processing unit.
Next, an output timing adjusting circuit will be explained.
As d<~scribed above, the amplitude of output signal SOUT is processed by high-sampling low-pass filter 63 in signal processing unit 118 and interpolation processing unit 65 in Fig. 20, to have a value corresponding to a timing of a transmitting clock SCLK.. In contrast, the output timing adjusting circuit dE~scribE~d below receives, as an input signal, an output signal train from signal processing unit 118 at irregular time intervals, as shown in~~ in Z34096~
Figs. 27A and ;Z7B. It thereby performs a time adjustment on the signals and outputs them to an external line at: equal intervals synchronized with transmitting clock SCLK as shown ini,~ in Figs. 27A and 27B. The circuit: corresponds to transmitting register 113 in the second embodiment of Fig. 20.
The rc~ctanc~les shown in ~ in Figs. 27A and 27B
indicate the tames at which the data is output from signal processing unit 118 to an output timing adjusting circuit. The position of the rectangle is not exact but allows some tolerance, as it is the output from signal processing unit 118. The output from signal processing unit 118 is usually produced at an intermc~diate~ position of receiving clock RCLK, based on the receiving clock. As shown in SOin Fig.
27A, in most of the periods, although it is irregular, the interval of output from signal processing unit 118 is almost equal to that of receiving clock RCLK, and the gap is largE~ only when there is no output signal and only when two outputs are produced per period, for example, after t7 in Fig. 27A and after t7 in Fig.
27B. Alth~~ugh in most periods, the output intervals are set equal, they are synchronized with receiving clock RCLK and not with transmitting clock SCLK.

_ 89 _ Therefore, :Lt is necessary to produce the output at an accurate timing of transmitting clock SCLK as shown in ~~ in Fig. 27n. Thus, the ,provision of the output timing adjusting circuit is meaningful.
Fig. 28 shows the structure of an output timing adjusting circuit for satisfying the above requirement. The circuit is provided in place of transmitting register 113 in the second embodiment in Fig. 20.
In Fio~. 28, register RO within signal processing unit 118 :is the output register and the result obtained b~~ a calculation in interpolation processing unit 65 (Fig. 20) in signal processing unit 118 is entered into thE: output register. Then, data output demand pu:Lse 1'19 for demanding the output to an external circuit is output from signal processing unit 118. When the output timing adjusting circuit is able to receive data, data transferring clock generator 169 outputs transferring clock 181, whose number is equal to the bit length of register R1 , to which the data is transferred. In accordance with this clock, the content o:E register RO is output to register R1 within an output timing adjusting circuit. Where input data is not allowed in data transmitting time adjusting unit lEiB, data transferring clock generator 169 is sups>ressed from producing transferring clock 181, thereby enabling the data output from signal processing unit 118 to be delayed. However, when the data is held in register R0, the process stops at a timing when the next data is output to register RO in signal processing unit 118. Therefore, it is unnecessary to hold the data in register RO for a long perio<3.
The operation of the output timing adjusting circuit shown in Fig. 28 is sum marized as follows. An output signal i~; transferred from RO to a circuit in which reg.ister~; R1 and R2 are cascade-connected.
After the signal is transferred from register RO to register R1, selector 178 selects which of the signals stored in registers R1 and R2 is to be used as an output signal, and the output is parallelly transferrE~d to register R3. The signals in register R3 are out~~ut as series data output 187. On the other hand, transmitting clock SCLK is input to transmitting synchronizing pulse output unit 177, and output therefrom as a transmitting synchronized pulse SYNC.
The above series data output 187 and synchronizing pulse SYNC are rnultiplexed and thereafter output to a 13409fig line as output signal SOUT (Fig. 20).
On the other hand, for a control signal, as described above, data output demand pulse 179 is entered into data transferring time (timing) adjusting unit 168 from signal processing unit 118. The circuit receives transmitting clock SCLK and forms a transfer prohibition pulse synchronized with transferring clock SCLK" Data transfer time adjusting unit 168 outputs transfer designating pulse 180 to data transfer c:Lock generator 169 immediately after data output demand pulse 179 is input. Therefore, data transfer clock generator 169 generates transfer clock 181. On the other hand, the above transfer prohibition pulse has a width in a time range determinecl by the width of the transfer prohibition pulse. If data output demand pulse 179 is input from signal processing unit 118 in this time range, data transfer time adjusting unit 168 does not produce a transfer designating pulse 180 until it passes the above timE~ range and transfer clock 181 is thereby delayed. Namely, a signal input from signal processing unit 118 is kept waiting. When transfer clock 179 is added to registers R0, R1, and R2, the data is transferred in accordance with the route of register SRO -~ register R1 -> register R2. of ter completion of transfer, data transfer end pulse generator 170 produces data transfer end pulse 182 such that select signal generator 169 (explained later) can count the number of transfer inputs within a period.
Select signal generator 171 performs the following operation in a time range in which the transfer prohibii:ion pulse becomes active.
Namely, the number of signal inputs during the previous period is read into counter 172, and select signal 186 from judging circuit 175 is fed back to its own judging circuit 175. Therefore, which signals stored in regisi:er R1 or R2 are to be transferred to register R3, .is fed back to judging circuit 175 itself. Following this process, judging circuit 175 operates and select signal 1 86 is subj ected to an arithmetic operation to determine the direction of selector 178 for the present period. Judging circuit 175 is in~.tia:Lized in synchronization with judging circuit initialization pulse 183 from judging circuit operation designation pulse generator 174, which operates based on transmitting clock SCLK.
Next, in order to count the number of signal 1340y68 inputs for the next period, counter 172 is cleared by counter clE~ar signal 184 from counter clear signal generator 173. .Simultaneously, parallel load pulse 185 from parallel load pulse generator 176 paralelly transfers <~ither of signals stored in register R1 or R2 to regi:~ter R3 in accordance with a direction of selector 1T8. 'the signals transferred to register R3 are transferred in parallel and thereafter, although not shown in the drawing, a clock pulse is applied to the clock terminal and output externally along with transmitting synchronizing pulse SYNC.
The time chart of the above operation will be shown in Fi.g. 29.
179 of Fi.g. 29 designates data output demand pulse outputs from signal processing unit 118. Their time interval is almost equal to the length of the period of receiving clock RCLK (R period).
On the other hand, a transfer prohibition pulse is general=ed in synchronization with transmitting clock SCLR: in data transfer time adjusting unit 168.
The pulse width must be sufficient to complete three processes comprising a series transfer operation by transfer clock 181, an operation of judging circuit by judging circuit initialization pulse 183 and parallel transfer to register R1/R2 from parallel load pulse 185. Generally, as the frequency of transmitting clock SCLK differs slightly from that of receiving clock RCLK, in, most cases, as shown in I or II in Fig.
29, data output demand pulse 179 does not overlap with transfer prohibition pulse even if R >S or S > R.
However, at a certain probability, they may overlap as shown in II:I in F'ig. 29. In the case of I or II, data transfer clock generator 169 immediately produces data clock 181 <ind performs a transfer of signals. Then transfer end pulse 182 for designating the completion of transfer is produced from data transfer end pulse generator 170. On the other hand, when data output demand pul;~e 179 is overlapped on transfer prohibition pulse, transfer clock 181 is output after transfer prohibition pulsE~ becomes inactive as shown in 181 in Fig. 29. :Cf there is no transfer prohibition pulse, data transfer starts right after data output demand pulse 179. During transfer of data through a route register RO -~' register R1 -~ register R2 parallel transfer t:o a route register R1 , R2 -~ register R3 is completed. In this case the content of register R3 is not always guaranteed.
A transfer prohibition pulse adjusts the signal 134o96a input time from signal processing unit 118 and prevents the transfer time from register R1/R2 to register R.3 from overlapping with the transfer time from signal processing unit 118 to register R1/R2.
'This prevents a signal breakage, and also prevents transfer end pulse 182 in Fig. 29 from colliding with judgment initiating pulse 183 or counter clear signal 184. Thus, the transfer prohibition pulse is very important for exactly determining the number of the input signals i.n a pre-period.
Next, select signal generating circuit 171 for operating selector 178 is explained. To match an actual IC, the rE~lationship between the sign of select signal 186 and respective registers is set as follows:
Select= Signa Register connected to Register R
0 Register R1 'I ~ Register R2 The numbers of signal inputs for a pre-period are 0, 1 , :? as dE~scribed above, and they are combined with a code (0, 1 ) of select signal 186 for the pre-period, thereby providing six combinations. For these six combinations, a judgment circuit inputs the following codes of select signal 186 to selector 178.

--~- _ i o j 2 1 In thE~ above table, A represents a select signal for a pre-period, B a number of a signal input for a pre-period, and C a select signal (output) for the present period. A select signal 186 of 0 means that the signal is transferred from register R1 to register R3, and a select signal 186 of 1 means that the signal is transferred from register R2 to register R3.
Where the input signal in the pre-period occurs once a period (S period) based on transmitting clock SCLK (in the tlhird and fourth rows of the above table), the coni~ents of both registers R1 and R2 are renewed once by the input. Without changing a code of the selector signal, the same register signal as in the previous period is output, thereby providing a continuous signal output.
Next, when signal input for the previous S period is 0 (in the first and second rows of the table) the 134Q9fi8 contents of the register are unchanged. Therefore, when the se:Lect signal for the current period is the same as thai:. for the previous period, the same signal as for the ~>revious period is output. Thus, when the select signal for the previous period is "1", it is changed to "0" in the current period. When the select signal for the previous period is "0", no new contents are contained in the register, which follows "0"
content in the register 1. Thus 0 is retained unchanged. In this case the same signal is produced twice, thereby causing a distortion in the output signal waveform. However, this occurs only once and then the apparatus operates in its normal state.
Thus, no p~_oblems occur.
When the input of the S period occurs twice for the previous period (shown in the fifth and sixth rows of that table)" the contents of the register are renewed twice. Therefore, if the select signal is not changed, the signal to be obtained becomes a new signal which is skipped by one from the signal output for the previous period. In this case, if the select signal is 0 for the previous period, it is changed to 1 in the current period and a signal of the correct order is transferred to register 3. If the select 1340968:
_ 98 _ signal for the previous period is 1, the signal which is older than that in register 2 is not stored, thus maintaining the aelect signal for the present period at 1 period. In this case, signals which are skipped by 1 are output. This phenomenon occurs once at most until the apparatus begins to operate in its normal state.
The operation of the timing adjustment circuit is explained by referring to Fi.g. 27n. Signals in respective registers R1 and R2 are designated by 6 and 7. These signal values, corresponding to respectivE~ signal values S0, S1 , S2, ..., can be obtained at timings T0, T1, T2, ... based on transmitting clock SCLK, in the process data shown in t_2~ of Fig. :~7A. For example, in~ of Fig. 27A, S5 is maintained from t5.5 to t6.5. This means that the output corresponding to a timing of TS based on transmitting clock SCLK is stored in register R1 from t5.5 to tE.s. As shown in O in the Fig. 27A, the signal S4 ~~orresponding to T4 is stored in register R2 for the same period.
Further, when the period unit (S period) synchronized with transmitting clock SCLK from TS to T6 is con~;idered in Fig. 27A, the previous output is ~ 340968 ;
_ 99 _ the signal S3 in register R2 in ~ in the same figure (selector signal is 1 ). From ~~~ and U, as an input occurs once for the previous period, the signal in register R;~, namely, signal SQ corresponding to a timing T4, is output at the timing T6. Similarly, the signal S4 i.n the register R2 is used for a previous output in the S period T6 to T7, and the number of inputs is one. Therefore, the signal in a register R-" namely, the signal corresponding to T5, is output at T7.
Next, for the.S period T7 to T8 no input exists. Tree content of register R1 does not change when the signal S6 corresponding to T6 is maintained, and the content of the register R2 does not change when the signal SS corresponding to TS is maintained. Select signal generator 171 in Fig. 28 judges that. no input signal exists, thereby changing the select signal to 0 and outputting signal S6 corresponding to the signal in register R1 , namely, signal S6 corresponding to T6 at T8.
Further, in. the case of an S period T8 to T9 a signal output occurs twice. The signal S7 corresponding t:o a timing T7 is stored in register R2 at a time 'r9~ In this case, select signal generator 1340968 ,.

171 changes the select signal to 1 by judging two input signals and previous select signal 1, thereby producing a signal in register R2 , namely, signal S7 corresponding ,to 'f7.
As described above, the output from register R3 is sequent:iall;y and correctly obtained. The above explanation app:Lies to the case of S period > R period in Fig. 27A, but the same explanation can be applied to the case of R period > S period in Fig. 278.
The judging circuit 175 shown in Fig. 28 for realizing rthe logic shown in the above table can be made by using a small scale circuit comprising a digital comparator operating together with counter 172 for counting the number of the signal input.
In thE~ fourth embodiment, as the output from a counter synchronized with transmitting clock SCLK is latched ire by receiving clock RCLK to detect the timing difference between them, (transmitting and receiving) the timing difference detecting circuit does not need a buffer circuit (register). Further, the control circuit is greatly simplified, the circuit scale is miniaturized and the operation is accurate.
As the transfer prohibition pulse is introduced, 134096$
- , o, -the output timing adjusting circuit simplifies the control circuit and ensures reliable operation, enabling a combination of selector signal and registers R~ and R2 to reduce the number of 'registers, i=hereby effectively suppressing the circuit scale.
As de;~crib~ed above, the greatest problem encountered in realizing a digital PCM channel apparatus, is that the receiving clock RCLK is not synchronized W lth transmitting clock SCLK, and conversion From the former system to the latter system is difficult. From the viewpoint of the scale of hardware and sof tware it is possible to provide most suitable resolution, and this embodiment facilitates the manufacture of the digital PCM channel apparatus in LSIs. The invention, can therefore realize the best digital PC'.M channel apparatus in respect of noise, power canaumption, reliability and cost.

Claims (7)

1. A digital signal processing apparatus for use in a digital signal clock changing apparatus for converting a first digital data train synchronized with a first clock, to a second digital data train synchronized with a second clock, comprising:
means for performing a high frequency sampling of the first digital data train to produce a sampled first digital data train;
timing difference detecting means for detecting a timing difference between the first clock and the second clock;
interpolation means for interpolating the sampled first digital data train based on the timing difference to produce an interpolation outputs; and means for producing the second digital data train in synchronization with the second clock based on the interpolation output of said means for interpolating.

2. A signal processing system for use in a digital signal clock changing apparatus for converting a first digital data system train synchronous with a first clock, and a second digital data system train synchronous with a second clock, comprising:
first digital data system train converting means for converting the first digital data system train to a converted data train having n times more data than the first digital data system train per unit time, where n is a natural number greater than one;
a high-sampling digital low-pass filter for performing a high sampling on the converted data train at a speed n times that of the first clock to produce a sampled data train;
timing difference detecting means for detecting a timing difference between the first clock and the second clock;
interpolation means for interpolating the sampled data train based on the timing difference obtained from said timing difference detecting means to provide amplitude data; and output timing adjusting means for synchronizing the amplitude data with the second clock to provide the second digital data system train.

3. A signal processing system according to claim 2, wherein:
said high-sampling digital low pass filter has loss characteristics and comprises an interlaced line of blocks and intermediate data converting means, each of said blocks of the interlaced line of blocks has a sampling speed of an integral ratio of sampling speeds of first and second adjacent blocks, such that a last block of said interlaced line of blocks operates at a sampling speed n times that of the first clock, and a sum of loss characteristics of each of said blocks is equal to the loss characteristics of said high-sampling digital low pass filter;

said intermediate data converting means receives data from the first adjacent block and outputs data of a same amplitude to the second adjacent block;
said interlaced lane of blocks and intermediate data converting means are provided in a number equal to the integral ratio of the sampling speeds of the first and second adjacent blocks; and said first digital data system train converting means receives the first digital data system train and outputs the converted data train at the same amplitude as the first digital data system train and in a number equal to a ratio of a sampling speed of a first block of said interlaced line of blocks and of a speed of the first clock.

4. A signal processing system according to claim 2 wherein:
said timing difference detecting means comprises:
counter means for counting L bits synchronized with the second clock at a system clock frequency of 2L times the frequency of the second clock, the maximum value being (2L-1), where L is an integer greater than one, and latch means for latching the count value of said counter means in synchronization with the first clock; and said interpolation means comprises:
means for detecting the count value latched in said latch means at every period of synchronization with the first clock, as a phase difference between the second clock and the first clock, and means for performing an arithmetic operation on the amplitude data based on the timing difference and the sampled data train from said high-sampling digital low pass filter.

5. A signal processing system according to claim 2, wherein:
said timing difference detecting means comprises:
~-bit counting means for counting ~-bits synchronized with the first clock at a system clock frequency of 2~ times a frequency of the first clock, the maximum value being (2~-1), latching means for latching a count value of said counting means in synchronization with the second clock, and buffer means for temporarily storing an output from said latching means; and said interpolation means comprises means for detecting a phase difference between the first clock and the second clock as the count value temporarily stored in said buffer means at every period synchronized with the first clock to produce amplitude data based on the phase difference and the output of said high-sampling digital low pass filter.

6. A signal processing system according to claim 5 wherein at every period which is synchronous with the first clock:
in a first ease, where the phase difference in a previous period is near 0 and the phase difference at a present period is near a period of the second clock, said interpolation means does not produce the amplitude data in the present period, in a second case, where the phase difference in the previous period is near the period of the second clock, and the phase difference in the present period is near 0, said interpolation means at the present period produces the amplitude data corresponding to a first value of the present period selected from the sampled data train from said high-sampling digital low-pass filter as the second digital data train and amplitude data corresponding to the last value of the present period as two continuous-amplitude data, and in a third case, other than the above first and second cases, said interpolation means produces the amplitude data by interpolating the output of said high-sampling digital low-pass filter based on the phase difference.

7. A signal processing system according to claim 6, wherein said output timing adjust ing means comprises first temporary storing means connected to an output terminal of said interpolation means;
second temporary storing means connected to cascade with the output side of said first temporary storing means;
transfer control means for transferring said amplitude data outputted from said interpolation means to said first temporary storing means, and transferring amplitude data stored in the first temporary storing means to the second temporary storing means;

data transfer time adjusting means for receiving an output demand of the amplitude data from said interpolation means operating at a period synchronized with the first clock, for fudging whether an input timing of the output demand overlaps with a predetermined prohibition time in the period which is synchronized with the second clock, for instructing said transfer control means to transfer said amplitude data when the output demand timing is not overlapped with the prohibition time and, if the output demand timing overlaps the predetermined prohibition time, instructing said transfer control means to transfer the amplitude data after the predetermined prohibition time ends;
selection means for selecting said amplitude data stored in either of said first or second temporary storing means;
third temporary storing means for storing amplitude data from said selection means and conducting an interference operation with an external line;
output control means for controlling the amplitude data from said third temporary storing means in synchronization with the second clock;
selection control means for controlling said selection means in synchronization with respective periods based on the second clock; and counting means for counting the number of inputs of amplitude data from said interpolation means at every period, based on the second clock; and said selection control means for judging selection data for the present period from an instantaneous count value obtained from said counting means in synchronization with said respective periods, and selection data output from this selection control means itself at the previous period, thereby being output to said selection means for controlling of said selection means.