CA1317042C - Apparatus and method for loading coordinate registers for use with a graphics subsystem utilizing an index register - Google Patents

Abstract

ABSTRACT

Apparatus and method for using an index register which Gycles modulo 4 for loading registers which contain coordinates of four vertices of quadrilateral objects, including degenerate quadrilateral objects, namely a point, a line and a triangle, which are to be displayed by a graphics display subsystem. In this manner, a software command need only define the minimum number of X,Y coordinate pairs to define the object, i.e., one coordinate pair for a point, two coordinate pairs for a line, three coordinate pairs for a triangle and two coordinate pairs for a rectangle (by defining opposite corners). Additionally, by using an index register according to the present invention, objects can be efficiently replicated.

Description

~3~ 70~2 SUM~Y OF THE ~7ENTlON

The present in vention is directed to an apparatus and method for using an index register which cycles from 0, 1, 2 and 3 ~or loading registers which contain coordinates of ~our vertices of quadrilateral objec~s, including de~senerate quadrilateral objects, namely a point, a line and a triangle, which are to be displayed by a graphics display subsystem. In this manner, a software command need only define ~he minimum number of X,Y coordinate pairs to define the object, i.e., one coordinate pair for a point, two coordinate pairs ~r a line, three coordinate pairs for a triangle and two coordinate pairs for a rectangle (by defining opposite corners).
0 The present invention, by use of an inde~ register also performs relative addressing which provides an efficient mechanism for displaying duplicates of objects. Relative addressing is best described by way of example as follows. The three vertices of a triangle may be defined as Xo, Yo, Xl, Yl and X2,Y2. To duplicate ~his object 50 times at different locations on the graphics display, it would be necessary to store 150 pairs of X,Y coordinates. Using relative addressLng~ one vertex is def~ned as the origin, Xo,Yo, and the second and third vertices are defilled as offsets from the previous vertex, i.e., ~xol~Ayol and l~xl2~yl2~ Where ~Xab or ~Yab means the difference between X~ and X~ or Ya and Yb respectively. To duplicate the object 50 times, all that needs ~o be stored are the two offset pairs and a new Xo,Yo ~or each duplicate (i.e. 50 object origins).

The present invelltion will be described with reference to a graphics subsystem in which comparisons made between coordinates and a clip window necessary to pe*onn clipping are performed in hardwa~e. The 13~7~l~2 1 present invention forms part of an apparatus which performs clipping of images to be displayed on a video display in hardware whenever possible, leaving for software only those images, or portions of images which cannot be reliably clipped using the graphics subsystem of the present invention.

Accordingly, in one aspect the present invention resides in an apparatus for loading four pairs of object coordinate registers with coordinates of an object to be displayed by a graph.ics subsystem, said object beirlg one of a quadrilateral to be drawn and a block image to be moved, said apparatus including loading means for loading said object coordinate registers with said object coordinates;

a) loading control means coupled to an indexing register which cycles from 0, 1, 2 and 3, said loading control means for generating a set of control signals which, based upon the value in said indexing register enable predetermined ones of said object coordinate registers to receive object coordinates received by an input means;
b) said input means coupled to said loading control means and said object coordinate registers for receiving from a source external to said apparatus, said object coordinates, and for storing said received coordinates in said object coordinate registers under control of said loading control means and said indexing register, ~'`'"'` .

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~3~70~2 l whereby said object to be displayed is defined by a number of coordinates to uniquely define said object.

In another aspect the present invention resides in an apparatus for loading four pairs of registers with object coordinates of an object to be displayed by a graphics subsystem, said object being one of a quadrilateral to be drawn and a block image to be moved, said apparatus having a clip window with predetermined top, bottom, right and left clip coordinates, and a test window with predetermined X and Y offsets from said top and bottom clip coordinates, and from said right and left clip coordinates, said object coordinates, said clip coordinates and said o~fsets for use in calculations for performing clipping of the object prior to said objects display, said apparatus including loading means for loading i) four pairs of obj;ect coordinate registers with said object coordinates, ii) a plurality of clip coordinate registers with said clip coordinates, and iii) a plurality of offset registers ~ith said predetermined 0 offset wherein said loading means comprises:
a) loading control means coupled to an indexing ~register which cycles from 0, 1, 2 and 3, said loading control means for generating a set of control signals which, based upon the value in said indexing register, enable predetermined ones Oe said object coordinate registers to receive object coordinates received by an input means;
b) said input means coupled to said loading -2a-13~ 7~2 1 control means, said object coordinate registers and said clip coordinate registers for receiving from a source external to said apparatus, said object coordinates and said clip coordinate registers, and for storing said received coordinates in said object coordinate registers and said clip coordinate registers under control of said loading control means and said indexing register, whereby said object to be displayed is defined by a number of coordinates to uniquely define said object.

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BRIEF DES(: RIPllON OF THE DRAW~GS

FlGUE~E 1 is a block overview diagram of a graphics subsys~em for a work station according to the present invention.

FlGURE 2 is a block diagram of the coordina~e staging section of the invented graphics subsystem.

FlGURE 3 is a detailed block diagram of adder 31 and multiplexor 35.

. FlGURE 4 is a detailed block diagram of XIY coordinate registers 37.

FIGURF. 5 is a detailed block diagram of clip coordinate registers 39.

FlGURE 6 is a detailed block diagrarrl of raster o~set register 41.

FIGURE 7 is a detailed block diagram of text window control 45.

FIGURE 8 is a detailed block diagram of comparison logic and result storage 47.
FIGURE 9 is a table showing relative timings ~or loading control state machine 35 and comparisons performed by comp~rison logic and result storage 47.

20~IGURE 10 is a truth table utilizing companson results for ehe X0 coordinate.

FIGURES lla and llb are a truth table utilizing comparisons between each of the four X vertices and each of the ~our Y vertices.

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13~7~2 ~IGIJRES 12a-12d define a truth table util-7.ing comparisons between , the four X and the four Y vertices and the clipping boundaries.

FIGURE 13 defines a tluth ~able utili7.ing comparisons between ~he ~our X and the four Y vertices and the test window boundaries .

FlGURE 14 defines a truth ~able showing the direction in which to draw objects or pe~orm blits.

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',: ' : , 13~70~2 DEl'AILED DESCRIPI'ION~OF THE INVENTION

The present invention is directed to a graphics subsystem of as engineering workstation.

The coordinate staging and coordinate cornparison lo~ic blocks (see Figure l) are provided to provide the necessary storage and cornparison inforrnation required for the SUppOlt of arbitra~y quadrilateral rendering with clipping, as well as Block Image Transfers (BLIT) with clipping. ln both cases, it is necessary to specify four XIY coordinate pairs and to specify the clipping window boundaries.
0 To support quadrilateral rendering implies the availability of four vertices which will define the quadrilateral. The disclosed embodiment of the invention puts very few restrictions on these vertices. They are stored in four register pairs (a register pair consists of one register for ~he X
coordinate and one register for the Y coordinate) and are re~erenced with 5 the vertex numbers 0 thru 3 It is implied that vertex 0 is connected to vertex 1, ~ertex 1 to vertex 2, vertex 2 to vertex 3, and vertex 3 ~o verte~
O. No connection is intended between vertices 0 and 2, or verticesl and 3 for instance. The coordinate staging and comparison logic form the initial stages of a pipeline that will eventually accomplish the rendesing of the 20 specified quadrilateral into the display memory. The subsequent pipeline stages ~equire information concen~ing ~he relatlonship of each adjacent vertex to its neighbors (i.e. for vertex l; Xl vs X0, Yl vs Y0, Xl vs X2, and Yl vs Y2). This infonrlation is needed to properly supply ~he functional addressing bloclk: with a series of trapez~ids that when composited,

2 5 ~3~71~2 accurately represent the origirlal quadrilateral. The decomposition of the arbitrary quadrilateral is accomplished by the coordinate sequencing logic.

Additionally, in order to suppor~ the clipping of the quadrilateral to the clipping boundaries in subsequent pipeline stages, the relationship of the vertices to the appropriate clippLng boundaries is required. This means for example all X vertices compared to both the minimum X clip boundary as well as to the ma~imum X clip boundary. A similar set of comparisons is required ~or the Y verlices as well. In some cases, these comparisons can indicate whether or not ~ o~ect has any visible portions (non-clipped) at all. By identifying the objects that will not be visible in advance, ~he utilization of the subsequent pipeline stages ca n be a~roided since no visible pi~cels will ever be identified for wri~ing ~o the display memc)ry. This represents a performance advantage in that the rendering of the quadrilateral can be considered to have occurred immediately once the clipping information has been analy~ed.

The preferred embodiment of the graphics system being described utilizes 16~bit 2's complement math when determining the pixel's associated with a line segment. This math involves taking the difference of 20 the two X and two Y vertices of the line s~gment. In order to avoid mathematical overflow, the numeric range of the X and Y vertex values must be restrieted to be representable in 15 bits ox be between -214 and (214 - 1~. Ln support of this, a check of the numeric ~ange of the vertices is made by the coordinate comparison logic.

The support of BLlTs also requires 4 vertices -two specify the opposite corners of a source (SRC) rPctangle and two specifying the .

"`` . 1317~2 opposite corners of a destination (DEST) reetangle. The intent of the BLIT
operation is to copy the pL~cels contained in the SRC rectangle to the DEST
rectangle. In the current embodiment, the upper left eorner of the SRC
rectangle is stored in vertex 0 while the lower right SRC corner is in vertex 5 1. Similarly, the upper left DEST corner is in vertex 2 and the lower right in vertex 3. In order to properly copy the SRC to the DEST, care must be taken in the event the two rectangles overlap. When this occurs, the order in which pi~cels are copied is constrained if the correct result is to be obtained. This is a well known problem to persons skilled in the art. The 0 information required to properly determine the pi~el copying constraints involve comparison of the SRC rectangle boundaries to the DEST rectangle boundaries. This is needed both for the X and the Y coordinates involved.

Additionally, to support clipping of both the SRC and DEST rectangles in subsequent pipel~ne stages, the relationship of the SRC and DEST vertices to the appropriate clipping boundaries is requ;red. Once again, this may indicate that either the SRC or DEST rectangl~e are totally obscured (non-visible) and may negate the need to utilize the subsequent pipel~ne stages.
Thls represents a performance advantage in that the execution of the BLIT
2 0 can be considered ~o have occurred immediately once the clipping information has been analyzed.

The coordinate staging con~rol logic supports multiple ways for the coordinate values to be acquired. Correspondingly, ~he coordinate comparison logic maintains the necessary comparison infonnation 2 5 regardless of the manner in which the coordina~e values are provided. The different methods for coordinate acquisition can be summari~ed as:
absolute, inde~ced, and relative. The specific method used is determined by ..

' ~3~70~2 1 the address of the register that the CPU uses to identify the regis~er(s) to be loaded. An absolute coordinate value is loaded by stonng the actual value supplied by the CPU into the addressed register. This method of loading is used for loading of the clipping boundary registers and the 5 raster offset registers as will be described below, as well as individual coordinate registers. The second method, inde~ed, is used to efficiently load multiple coordinates with the s~me values. In this case, the CPU
supplied value is first added to the appropriate raster offset register (either raster o~fset X or Y) before being made available for storage in one o or more coordinate registers. The addition of the raster offset provides a means of offsetting the X/Y address space provided by the CPU to a different area of the display memory.

The indexed loading mechanism utilizes a two-bit inde~ to guide itself and identify how many and which coordinate registers to load during any given cycle. It is this mechanism that allows the CPU to specify only one X/Y pair to identify the degenerate quadrilateral - a point, or two X/Y
pairs for a line, or three X/Y pairs for a triangle. When one of the aforementioned degenerate quadrilaterals is loaded into the four vertex 20 registers, one or more vertices may be repeated. This is necessary so that subsequent stages of the pipeline can always inte~pret the object defined as a quadrilateral (eYen though degenerate) and not treat as a specia1 case all lower order object~ (i.e., point, line, tnangle). The indexed loading scheme also allows ~or only the opposite comers of a rectangle to be 2 5 entered to properly define all iFour corners of the corresponding quadrilateral .

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The last loading method, relative, is used to allow the CPU to just specify the difference between the last coordinate entered and the intended new coordinate value. In this case a CPU supplied delta or offset is added to the previously loaded coordinate before being loading into one 5 or more registers. The 2-bit index is used to identify the las~ coordinate entered [verte~ (index-l~ mod 43 for the necessary addition plus identifies which register or registers need to be loaded as in the indexed loading case.

, In the end result, the CPU is ~ee to choose to load the coordinate registers in any manner suppOned. When the operation, either a quadrilateral rendering or BLIT, is actually requested (after the coordinates have already been loaded~ the current state of the four vertices are util~zed direct1y without regard to how they were acquired.
This provi~es the utmost in flexibilit~ for the CPU.

Figure 1 is an overview of a graphics subsystem in which the present invention may be utilized. Bus interface logic l l is connected through address, data and control buses to a central processing unit (not shown).
The functional components of the graphics subsystem are data pa~h and 20 memory interface 13, coordinate staging sec~ion lS, coordinate sequencing section 17, functional addressing block 19, mask generation block 21 and linear address generator 23.

Data path and memory interface 13 update a frame buf~er (not 2 5 shown) which is a memory which stores graphical informa~ion to be displayed on a video display such as a CRT. That is, data which is loaded into the frame buffer is accessed by video circuitry which converts the g `` 13~7~2 data to appropriate electrical signals which, in turn, turn individual pixels of the ~ideo display on and off. The data from bus interface logic is modified by mask generation block 21 and linear address generator 23 based upon processing performed by coordinate staging section 15~
5 coordinate sequencing section 17 and functional addressing stage 19.
Functional addressing stage 19 also accornplishes a portion of the clipping necessary to fit particular graphic objects to the clip window in which ~hey are to be displayed, and then transfers the signals to mask generation stage 21 which arranges the information info sixteen pixel portions that 0 traverse from the beginning to the end of the visible object for each scan line and are used for addressing the data path and memory interface stage 13.

The mask generation signals are also fumished to linear address 5 generator 23 which ~ransla~es the addresses provided by the mask generation stage 21 into signals for linearly addressing the frame buffer for trans~r to the output display. One embodiment of data pa~h and memory interface hlock 13 may be found in copending Canadian Patent applicationsSerial No. 600,289 filed May 19, 1989, No. 601,067 fil~d May 24, 1989 and NoO 600~158 filed May 19, 1989. An embod iment of coord inate sequenc ing log ic 17 is d isclosed in co-pending Canadian application Serial No. 611,654 filed September 15, 1989. An embodiment of functional addressing block 19 is disclosed in co-pending Serial Nos. bll,651 and 611"652 both filed September 15, 1989. An embodiment of linear address generator 23 is disclosed in co pending application Serial No. 60~,703 filed August 29, 1989.
The present invention is di~ected to circuitry in coordinate staging block 15 which performs certain operations based upon its inputs, the specifics of which will be described below wi~h reference to figures 2-14 generatlng ~3~7~2 1 information in the nature of control signals to enable a graphics subsystem to perfo~n arbitrary quadrilateral rendering with clipping and block image tTansfers (BLII s) wi~h clipping. Tlhus, the present invention is directed to specific circuitry within coordinate staging section 15.

Lmplementation of the various timing and control signals needed for the proper operation of the ~oregoing functional blocks comprising a video display subsystem are well known to persons skilled in the art and, there~ore, will no~ be described herein except as necessary for a proper 0 unde~standing of the invention.

Referring now to figure 2, a block overview diagrarn of coordinate staging section 15 is shown. Coordinate staging section 15 comprises adder 31, loading control state machine 33, multiplexer 35, Xlr coord~nate regisiers 37, clip coordinate registers 39, raster offset registers 41, index 5 logic 43, test window control logic 45, comparison logic and result storage 47, comparison control sta~e machine 49, and status generation logic 51.

Be~re setting forth the specifics of the present invention, a brief description of the manner in which objects are represented follows lo aid 2 n the understanding of the manner in which the present invention is implemented .

XY pairs of vertices ~epresent vi~eo display coordinates. For a typical display, X ranges between 0-1151 and Y ranges between 0-899.
Each X coordinate and each Y coordinate is stored in a separate 32 bit 2s register or a pair of 16 bit registers. Although 16 bits are more than adequate to store tbe largest screen coordinate (i.e., up to 65535 or -3276g to +32767), 32 bits of infolmation are stored because it is the data type ;
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: , , 'i ~ ~ , ~3~ 2 most prevalent in graphics software and provides a large enough range to handle most real life objects which may sparl areas much larger than the video display.

Quadrilateral objects are represented as combinations of four pairs of vertices (Xo,Yo), (Xl,Y~ X2,Y2), and (X3,Y3). If an object is a point, then all ~our pairs of vertices are the same or three points repeated. If an object is a line, then two of the four (or three of the four) pairs of vertices are replicated. If an objec~ is a triangle, then one pair of ver~ices out of the0 four,pairs is replicated. If an object is a quadrilateral then all four pairs are distinct. Objects (i.e., point, line, triangle or quadrilateral) are most efficiently defined using the minimum number of unique vertices necessa~r to completely define ~he object, i.e., for a point 1, for a line - 2, for a triangle - 3, for a quadrilateral - 4 and for a res~angle - 2 (opposite corners).
If a block image transfer (BLI~) operation is to be performed, ~hen the four X/Y registers have the following interpretation and are loaded accordingly:

X0 - X coordinate for upper left corner of the source block.
YO - Y coordinate for upper lef~ corner of the source block.

Xl - X coordinate for lower right comer of the source block.

Y1 - Y coordinate for lower right corner of the source block.
2s X2 - X coordinate for upper lef~ corner of the destination block.

Y2 - Y coordinate fo~ upper left comer of the destination block.

~7~2 X3 - X coordinate i~or lower right corner of ~he destination block.

Y3 - Y coordinate for ilower right corner of the destination block.

Images to be displayed on a display such as a CRT are formed as 5 discrete pi~ceis which are stored i~i a random access memory (RAM) known as a frarne buffer in one or more planes (or bits), the number of planes typically being eight for a color system. Data s~ored in the frame buffer is addressed by a pair of coordinates, X and Y, where an X,Y pair identifies a particular pixel in all planes, X being the row and Y being the colllmn. A
0 pixel is defined by a single bie from each plane. Thus, if eight planes are utilized, each displayed pixel is de~ined by eight bits in the frame buffer.
In this manner, one bit of a pixel can be used to specify whether it is on or off, with the remaining seven bits specifying the color of the pixel, or all eight pL~els can be used to specify the color, with one of the colors being 5 the same as the background color of the display to turn the pixel off.

The present invention lies mainly in its implementation of loading control state machine 33 which controls the operation of an index register in index logic 43. In this connec~ion, with respect to the other functional 20 blocks shown in Figure 2, their operation and ~mplementation will be described only in such detail as is necessary for a proper understanding of the present inven~ion.

25 4~dder 31 and MUX 35 Adder 31 is a l6 or 32-bit 2's complement binary adder having two inputs, namely DataIrl from bus inter~ace logic 1 l which represen~s - l 3 - ~

~3~ ~0~2 incoming data ~rom the CPU and an input fronn MUX 35 which is a multipl~xer which selects one of a set of inputs from raster offset registers 47, XIY coordinate registers 379 or clip coordinate registers 39. The input ~om MUX 35 is selected by signals generated by loading contr~l state 5 machine 33 as described below.

The details of adder 31 and multiple~or 35 will now be described with reference ~o Figure 3. In Figure 3, adder 31 is shown as a 16 bit adder. In this connectiorl, although a 32 bit adder could be used since Dataln in the prefe~Ted embodiment is 32 bits, in order to save space on the integrated circuit in which the invention is implemented and since timing requirements of the pipeline utilized by the present invention are satisfied by a two step add, the following description will ~e directed to a 16 bit adder. The differences for utilizing a 32 bit adder will be apparent 5 to those skilled in the art and, therefore, will not be described.

Multiplexor 35 is actually a pair of multiplexors 35a and 35b and a third multiplexor 36 which is used to input the high order and low order 16 bits from DataIn. Multiplexor 35a and 35b receive the high order and low order 16 b;ts respectively from seven 32 bit inputs as follows: one 16 20 bit input (sign extended to 32-bits) from raster o~fset registers 41, ~our 32 bit inputs from XIY coordinate registers 37 and two 1~ bit inputs (sign ex~ended to 32-bits) from clip coordinate registers 39. The outputs from multiplexors 35a and 35b are sombined ~o form the signal DataOut (~or providing read access to these register values to the CPU) and are also 2 5 input to a third multiplexor 40 which passes the output from multiplexor 35a whenever the high order bits from Xo-X3 or Yo-Y3 are being accessed;
otherwise multiplexor 40 selects the output from multiple~or 35b. The 13170~

output from multiple~or 40 is one input to logic gate 42 which either passes the 16 bit output from mul~iplexor 40 or passes 16 bits of zeros. ln this connection, zeros are ~orced by logic gate 42 whenever the bits of DataIn are passed by multiplexor 36 ~or directly loading (absolute.loading) 5 into a register within raster offset registers 47, X/Y coordinate registers 37, or clip coordinate registers 39. Also shown in Figure 3 are logic circuits 44 and 46 which perfonn the following function. When a low order 16-bit add is taking place, ANI) gate 44 has its output ~orced to a low providing a carry-ln of a "O" to the adder 31. The carry out of this add is saved in flip 0 flop 46. I~e output of flip flop 46 is gated by AND gate 44 to the carry in of adder 31 during the addition of the upper 16-bits. This combination provides a 2 cycle 32-bit add equivalent to a sin~gle cycle 32 bit add.

The operation of adder 31, raster offset registers 41, X/Y coordinate registers 37, clip coordinate registers 39, test window control 45 and companson lQgiC and ~esult storage 47 are coordinated by loading control state machine 33 and comparison logic state machine 49 which causes the aforesaid ~unctional blocks to operate so that the data is flowing in a pipeline. Thus, although not all control lines ~rom loading control state machine 33 and comparison logic state machirle 49 are shown, ~he details will be readily apparent to those skilled in the art from the description of loading control state machitse 33 and comparison logic state machine 49 below .

X/Y Coordinate Re~isters 37 X/Y coordinate registers 37 is, referring to Figure 4, a set of 16-bit registers which store the (Xo,Yo~-(X3,Y3) vertices of an object to be drawn.

~3~ 7~L2 One 16-bit register is used to store the upper 16 bits of each X coordinaie and ano~her 16-bit register is used to the store the lower 16 bits of each X
coordinate. Similarly, another 16-bit register holds the upper 16 bi~s of each Y coordinate and another 16-bit register holds the lower 16 bits of 5 each Y coordinate. These registers are shown in Figure ~ as XOL
representing the lower ~6 bits of ~he Xo coordinate and XOU representing upper 16 bits of the Xo coordinate. Registers XlL-X3L and XlU-X3U
represent the lower and upper 16 bits of the Xl-X3 coordinates respectfully. Similarly registers YOL-Y3L and YOU-Y3U store the lower 0 and upper 16 bits of the Yo-Y3 coordinates of ~he obJect. References to XO,YO e~c. mean the 32 bit Y~lue stored in the corresponding register pair, i.e., XOU,XOL and YOU,YOL.

Each pair of registers, (XOL,YOL)-(X3L,Y3L) are coupled to a multiplexer pair which are used to select ei~her the correspond~ng X or Y
register. For e~ample, registers XOL and YOL are coupled to multiplexers 61a and 61b. Loading control state machine 33 generates a signal which directs multiplexer 61a to select the input from register XOL or YOL
depending upon the whether the X coordinates are to be operated upon or 20 the Y coordinates are to be operated upon. Each of mul~iplexers 62a and 62b - 64a and 64b operate in the same manner respectiYely for data from register pairs (XlL,YlL~-(X3L,Y3L). The outputs from multiplexers 61a-64a go to multiple~er 35b, while the outputs from multiplexers 61b-64b go to comparison logic and result storage 47.
Blocks 67, 69, 71, and 73 labeled All O's All l's are each logic circuitry which checks the upper 18-bits oiE its corresponding X,Y
coordinate pair for all zeros or all ones. Si~teen of the bits come from the 13:~70~2 registers (XOU,YOU)-(X3U,Y3U) with the seventeenth and eighteenth bits coming from the high order ~wo bits of the corresponding register in the grouping (XOL,YOL-X3L,Y3L). The seventeenth and eighteen~h bit input is not shown in Figure 4 to avoid unnecessarily cluttering the figure. .The 5 register pairs (XOU,YOU~-(X3U,Y31J) are input into multiplexers 75-78 respectively which select either the X coordinate or Y coordinate in the same manner as multiplexer pairs 61a,61b-~a,64b. The outputs from multiplexers 75-78 go to multiplexer 35a. One of the 4-bits output i~rom each of logic blocks Ç7-73 are each a "1" if the upper 18-bits of its 0 corresponding register are all zeros or all ones, otherwise each of the 4-bits .
is zero. The four 4bit outputs from blocks 67-73 are input into status generation logic ~1.

Çlip Coordinate ReL~isters 39 Clip coordinate registers, as shown in Figure S comprises four registers, XClipMin, XClipMax, YClipMin, YCli]pMax and multiplexors 81a, 81b, 83a and 83b. The values XClipMin, XClipMa~, YClipMin, YClipMas, which are stored in the aforesaid registers with the same name, respectively define ~he left, right, top and bottom of the currently active 20 willdow. These values a~e generated by the CPU and ~e input to adder 31 which adds O to these values for loading the registers XClipMin, XClipMax, YClipMin, and YClipMax as described above. Multiplexors 81a and 83a on the one hand, and multiplexors 81b and 83b on the other, select XClipMin arld XClipMax or YClipMin and YClipMa~c, depending on control signals 2 5 generated by loading control state machine 33 and comparison control sta~e machine 49 respectively. The values from multiplexors 81a and 83a are sen~ ~o multiplexor 35, while the values from multiplexors 81b and - 13~ 2 83b are sent to comparison logic and result storage 47 and test window control 45.

Raster Offset Registers 41 Raster offset registers 41, as shown in Figure 6 comprises two registers, XRasO~f, YRasOff, and multiplexor 53. The values XRasOff and YRasOff, which are stored in the aforesaid registers with the same name, respectively define the X and Y offset to be added (when desired) to DataIn before storage ~nto each of the four sets of X,Y coordinates ~ X/Y
0 coordinate registers 37. These values are generated by the CPU for storage in XRasOff and YRasOff. Multiplexor 53 selects XRasOff or YRasOff depending on control signals generated by loading control state machine 33. The value selected by multiplexor 53 is sent to multiplexor 35.

5 Test Wmdow Control 45 Test window control 45 will now be described with reference ~o Figure 7. The CPU generates the values ~estXVal and testYVal which offset a predetermirled dis~ance, i.e. number of pixels, above and below (for testYVal) and to the right and left (for testX~lal) of the currently active 20 clipping window. That is, for a given window on a display, there is a ~X
and ~Y which define a test window surrounding the real clip window. The purpose of this test window is to eliminate, whenever it is beneficial to do so, the need for the hardware to calculate the location of objects or portions of the objects which are outside the clipping window. Deta~ls 25 concerning the use of the test window are described in copending Canadian application Serial No. 612, 526 filec9 Sep~ember 22, 198g.

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13~70~2 The ~bit values testXVal and testYVal are stored in the 4-bit registers testX and testY respectively. Multiplexer 91 selects olle of ~he registers testX or testY depending upon whether the X coordinates or the Y
coordinates are being operated upon as determined by the signal MUX
5 Enable generated by the loading control state machine 33. The output of multiple~er 91 is input into decrementor 93 ~nd incrementor 95.
Decrementor 93 has as a second input the value XClipMin or YClipMin and incre m entor 95 has as a second input the value XClipMax or YClipMax, again dependmg upon whether X or Y coordinates are being operated upon 0 as determined by the signal MUX Enable generated by the loading control state snachine 33. The outputs generated by decrementor 93 and incrementor 95 will be referred to as XTestMin, YTestMin and XTestMax, YTestMax respectively. Decrementor 91 creates the values XTestMin and YTestMin by subtracting from XClipMin and YClipMin a value equal to 2 5 raised to (testX-1) and (testY-l) power respectively. Similarly, incrementor 93 creates the values XTestMax and YTestMax by adding to XClipMax and YClipMax a value equal to 2 raised to the (testX-l) and (testY-1~ power respectively. (i.e., 2(testX-l) or 2(testY -1)).

20 Loadin~ Control State Machine 33 and lndex ~Q~ic 43 Loading control state machine 33 generates the control signals, MUX
Enable, Inde~c and Register ~nable. MUX Enable is a set of control signals, one of which causes tne various multiplexors in raster offset ~egisters 41, X/Y coordinate registers 37 and clip coordinate registers 39 to select their 25 respective X inputs or Y inputs; a second of which causes multiplexor 35 to select one of the inputs from raster offset registers 41, X/Y coordinate registers 37 or clip coordinate registers 39. Index is a single control signal .

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~3~7~2 which causes an inde~ register in inde~ logic 43 to increment by 1 between for each of the values n, 1 and 2, and if the value is 3, to reset to 0 (modulo 4). Register Enable is a set of control signals, one for each of the registers in raster offset registers 41, X/Y coordinate registers 37 and elip 5 coordinate ~egisters 39, enabling each such Tegister to load the 16 bit value on the line from adder 31.

The operation of load control state machine 33 and index iogic 43 will now be described by way of an example from which the implementation details should be apparent. As noted above, images to be drawn are defined as being made of one or more objects haYing four pairs of vertices, (Xo,Yo3 - (X3,Y3~. Objects may be points, lines, triangles, rectangles or quadrilaterals. For points, the four pairs of ver~ices are identical ~or lines, there are only two pairs of unique vertices. Four sided 5 quadrilaterals have four unique vertices. A rectangle represents a special case of ~guadrilaeeral wherein there are only two unique X eoordinates and two unique Y coordinates (rectangles can be defined by a pair of vertices defining diagonally opposite corners). For triangles, there are only three pairs of unique vertices.
The index ~alu¢ specifies which registers to enable based upon the type of object being defined. F~r proper operation, Y values precede X
values. E~cept for rectangles, the index ~egister is incremented a*er the X
values have been loaded in the appropriate registers. For rectangles, the index register is incremented after both X and Y values. ~In this connection, 25 the following table sets forth for each type of olbject, the X registers which are enabled for each index register value. Although not shown, the enabled Y registers would correspond to the enabled X registers.

~ - \
1 3170~2 TABLE I
Index Value At Time Of Load Qbject Type O ~ 1 2 _3 point XO,Xl,~.2,X3 Xl,X2,X3,X0 X~,X3,XO,X1 X3,XO,Xl,X2 line XO,Xl,X2 Xl~X2,X3 X2,X3,X0 X3,XO,Xl quadrilateral X0 X1 X2 X3 rectangle XO,Xl Xl,X2 X2,X3 X3,X0 An importa;lt point that can be seen in Table I is that the coordinate pointed to by the inde~ register is always written. The type of write (point, line, triangle, etc.) indicates how many subsequent registers (modulo 4) will also be written. For example, if the index is 2, at the time a line X write is received, then three registers will be written, namely X2, (X2 ~ 1) modulo 4 and (X2 + 2j modulo 4 or X2, X3 and X0. A quadrilateral write to Y would only affect Y2.

Examples 1-3 b¢low will explain the role of the index register when defining an object. Each line of the example indicates the intended wri~e operation, the index register~ value utilized by the loading control state machine to govern the loading of the coordinate registers, the values slored in the coordinate registers after the write, and the index Yalue af~er 20 the write cycle coneludes. The mnemonics ~for the write commands are PntX or PntY to indicate a point write, L~neX or LineY for a line write, TriX
and TriY for a triaulgle write, QuadX and QuadY ~or a quadrilateral write, and RectX and RectY ~or a ~ectangle write operation. The actual write ~pera~ion identified by each write command is actually a multi-clock cycle . -.
'- '. . :

1317~

operation as will be dessribed later. For these examples though, the execution time of the command is of no relevance.

As a means of clarifying the interpretation of these examples, the iEirst one will be described. From this description the interpretation of Examples 2 and 3 should be readily apparent.

At the time the PntY(6) command is received, all coordinate registers contain the value "0" and the inde~c is equal to "l". The PntY(6) command says that a point of ~alue 6 should be loaded into the Y coordinate 0 registers. Since the index is a 1, Table I indicates that the incoming value ~6~ should be stored into Yl, Y2, Y3 and Y0. The next con~nand received, PntX(3), then says to load the point 3 into Xl, X2, X3 and X0. As is the case after all inde~ed X coordinate writes, the index is incremented (modulo 4) at the end of the wAte cycle. The nex~ write conmand is a LineY(9). The 5 index for this load is 2 and Table 1 ~ndicates the loading of 9 into Y2, Y3 and Y0. The final wAte c~mmand for this example is LineX(7). Table I
indicates the loading of 7 into X2, X3 and X0 after which the index regis~er is again incremented. The final state of the s,oordinate registers identify two unique vertices (3 vertices at (7, 9) ~nd one at (3, 6)). Geometrically, 20 this is a line with endpoints at (7, 9) and (3, 6) as was intended.

.

- 2 ~ -~3~70~2 Exarnple 1 Specifying a line (3, 6) ~7, 9) Index Index Before After Command X0 X1 X2 X3 Y0 Y1 Y2 Y3Write Write - O O O O O ~ O 0 01 01 write PntY(6) 0 0 0 0 6 6 6 6 01 01 5write PntX(3) 3 3 3 3 6 6 6 6 0 1 0 2 write LineY(9) 3 3 3 3 9 6 9 9 0 2 0 2 write LineX(7) 7 3 7 7 9 6 9 9 0 2 0 3 Example 2 Specifying a ~riangle (1,5) (9,3) (4,6) Index lndex Be~ore After ~ommand XO_X1 X2 X3 yO Y1 Y2 Y3 Write Write write TriY(5) 7 3 7 7 5 6 9 5 0 3 0 3 write TriX~ 1 ) I 3 7 1 5 6 9 5 0 3 0 0 write TriY(3) 1 3 7 1 3 3 9 5 0 0 0 0 . write TriX(9) 9 9 7 1 3 3 9 5 0 0 01 write TriY(6) 9 9 7 1 3 6 6 5 01 01 write TriX(4) 9 4 4 1 3 6 6 5 0 1 û 2 Example 3 Specifying a Rectangle (0,7) (8,7) (8,1) (0,1) Index Index B efore A ft er Command X0 ~1 X2 X3 Y0 Yl Y2 Y3Write Write - 9 4 4 1 3 S 6 5 ~ 0 2 write RectY~1) 9 4 4 1 3 6 1 1 0 ~ 0 3 write RectX(0) 0 4 4 0 3 6 1 1 0 3 0 0 write RectY(7) 0 4 4 0 7 7 1 1 0 0 0 1 write RectX(8) 0 ~ 8 0 7 7 1 1 0 1 0 2 ''''. : ', . ' ~ ' ' :
. ' '' . ' ' '' ' ' " ' '' ' ' -` 1317~2 Although in e~ample 1, the inde~ register is arbitrarily 1 when the first coordinate is received9 the index register in index logic 43 may be initialized based upon a value placed on DataIn if instructed by the CPU.
(It is worth noting, however, that proper operation of this invention is 5 totally independent of the initial value of ihe index register when a loading sequence is initiated.). It is also assumed in this example that XRasOff and YRasOff contain the value 0 so as not to obscure the operation of this circuitry.

, Loading control state machine 33 in conjunction with comparison logic state machine 49 controls a pipelining scheme which in addition to loading the various registers described above, also controls the selection of registers and corresponding multiplexors necessary for the proper operation of comparison logic and result storage 47 and status generation logic 51. Additionally, when it is desired to not u~ilize the raster offset capability of the present invention, it is necessary to force the addition of O's to the incoming data for storage into the X and Y coordinate registers prior to performing the comparisons performed by comparison logic and result storage 47.
In this connection, the MUX Enable, and Register Enable con~rol signals generated by loading control state machine 33 and comparison logic state machine 49 may be ascertained from the timing sequence table set forth in Figure 9 and the following list showing the order of processing per~oImed by coordinate staging sectivn l S for each entered Y coordinate.

1. Receive Y coordinate on DataIn ``" ~L317~2 2. Add the low order 16 bits of ehe received Y coordinate to:
a) YRasOff (lower 16-bits) or b) the low order 16 bits of YOL-Y3L pointed to by (index-l) or c) û's 5 3. Add the high order 16 bits of the received Y coordinate to:
a) YRasOff (sign extended upper 16-bits) or b) ~he high order 16 bits of Y0H-Y3H pointed to by (index-l) or c) 0's and compare the result of step 2 to the other Y coordinates 4. ~ Compare the result of step 2 to YClipMin~ YTestMin, YClipMax, and 0 YTestMax and e~nine the upper 18 bi~s of the result of steps 2 and 3 for all l's and all 0's.

In seeps 2 and 3 above, the choices a), b) or c~ are made as follows.
For non-relative writes to an indexed register (PNl[, LINE, TRI, QUAD, RECT) choice a) is selected. For a relative write to an indexed register (RELPNT, 5 R:ELL~E, RELTRI, RELQUAD, RELRECT) choice b) is selected. All other writes se~ect cboice cj. The load~ng of an X coord~nate follows the same flow.

With the ~oregoing restrictions and definitions in mind, and assuming 20 that the inde~ register value in inde~ logic 43 is '01' and registers (X0,Y0) -(X3,Y3) as described above with re~erence to Figure 4 are all 0, the following sequence of events takes place to load the registers so as to define a line having endpoints whose ~,Y coordinates are (3,6) (7,9) as in Example 1.
At clock cycle 0, the command write PntY(6) places the value 6 on DataIn, and causes the register address input to loadlng control sta~e ^` 13~7~2 machine 33 to contain a value indicating that ~he incoming data is a Y
point. .At clock cycle 1 (and referring to Figure 3), multiplexor 36 is instructed to select the low order 16 bits on DataIn and multiplexors 35 (i.e., multiplexors 35a and 35b~ ~Lnd 40 and logic gate 42 are instructed to 5 pass the lower 16 bits of YRasOff. Thus, during clock cycle 1, adder 31 adds the outputs ~rom multiplexor 36 and logic gate 42 and places the ~esult at its ~utput. At the end of clock cycle 1, ~egisters YOL-Y3L are enabled and loaded with the value from adder 31, i.e., 6 representing the low order bits of the value 6 that was on DataIn. At clock cycle 2, 0 multiplexor 36 is instructed to select the high order 16 bits on DataIn and multiplexors 35 and 40 and logic gate 42 are instructed to pass the sign e~tended upper 16 bits of YlRasOff. Thus, dunng clock cycle 2, adder 31 adds the outputs ~rom multiplexor 36 and logic gate 42 andl places the result at i~s output. At the end of clock cycle 2, registers YOH-Y3H are 5 enabled and loaded with the value from the output of adder 31. At cycle

3, the command write PntX(3) places the value 3 on DataIn, and causes the register address input to loading control state machine 33 to contain a Yalue indicating that the ineoming data is an X point. Also at clock cycle 3, multiplexor 36 is instructed to select the low order 16 bits on DataIn and 20 multiplexors 3S and 40 and logic gate 42 are instructed to pass the lower 16 bits of XRasOff. During clock cycle 3, adder 31 adds the outputs ~rom tnultiplexor 36 and logic gate 42 and places the result at its output. At the end o clock cycle 3, registers XOL-X3L are enabled and loaded with the ~alue from adder 31, i.e., 3 representing the low order bits of the value 3 25 that was on Da~aIn. At clock cycle 4, multiplexor 36 is instructed to select the hi8h order 16 bits on Dataln and multiple~ors 35 and 40 and logic gate 42 are instructed to pass the sign e~tended upper 16 ~its of XRasOf~. At ~3~71~2 clock cycle 4, adder 31 adds the outputs from multiplexor 36 and logic gate 42 and places the result at its output. During clock cycle 4, registers XOH-X3H are enabled and l~aded ~vith the value ~rom the output of adder 31, and the index register is incremented. At clock cycle S, the command 5 write LineY(9) places the value 9 on Dataln, and causes the register address input to loading control state machine 33 to contain a value indicating that the incoming data is a Y line. At clock cycle 5, mu1tiplexor 36 is instructed to select the low order 16 bits on DataIn and multiplexors 35 and 40 and logic gate 42 a~e instructed to pass the lower 16 bits of 0 YRasO~f. During clock cycle 5, adder 31 adds the outputs from multiplexor 36 and logic gate 42 and places the result at its ou~tput. At the end of clock cycle 5, registers Y2L, Y3L and YOL are enabled and loaded with the value from adder 31, i.e., 9 represen~ing the low order bits of the value 9 that was on Dataln. At clock cycle 61 multiplexor 36 is instructed to select the 5 high order 16 bits on DataIn and multiplexors 35 and 40 and logic gate 42 are instructed to pass the sign e~tended upper 16 bits of YRasOff. At clock cycle 6, adder 31 adds the outputs from multiplexor 36 and logic gate 42 and places the result at its output. During cloch; cycle 6, registers Y2H, Y3H
and YOH are snabled and loaded with the value from the output of adder 20 31. At clock cycle 7, the command write LineX(7) places the value 7 on DataIn, and causes the register address input ~o loading control state machine 33 to contain a value indicating that the incoming data is an X
line. In a like manner registers X2L, X3L and XOL are eventually enabled to load the value 7 ~fter which the index register is incremented from 2 to 2s 3 as shown above. Loading X/Y coord~ate registers for other objects follows the same pipeline scheme described above. E~amples for triangles 131 7~2 and rectangles are given in examples 2 and 3 above. In a similar manner, quadrilateral objects are also loaded.

Raster offset registers 41 and clip coordinate registers 39 are loaded Ln a similar manner as X/Y coordinate registers 37 as described above, however, logic gate 42 is instructed t~ force O's for each add cycle. (i.e., absolute loading) The present invention, by use of the inde~ register in index logic 43 also perfonns relative addressing which provides an efficient mechanism 0 for displaying duplicates of objects. Relative addressing is best described by way of an example as follows. The three vertices of a triangle may be defined as (Xo,Yo), (Xl,Yl) and (X2,Y2~. To duplicate this object 50 times at different locations on the display, it would be necessary to store lS0 pairs of X,Y coordinates. Using relative addressing, one vertex is defined as 5 the origin (Xo,Yo), and the second and third vertices are defined as offsets from the previous vertex, i.e., ~Xol,~Yol and ~X23,~Y23. To duplicate the object S0 times, all that needs to be stored are the two offset pairs and a new Xo,Yo for each duplicate (i.e. ~ifty object origins plus two offset pairs total) .

Tbis can be accomplished in the present in~rention by fi~st storing the origin coordinate pair vertex in one of the register pairs within X/Y
coordinate registers 37 using an indexed loading style (i.e., PntY, PntX).
The two offset ve~tices are subsequently stored relative to the ~rertex 25 pointed to by the current value oiE the index register. This is accomplished by selecting the vertex pointed to by (index -1) to be added to DataIn pnor to register loading. The vertex referenced by ~index -1) is -2~-.

---`` 1317~

guaranteed to have been loaded on the previous indexed write irrespective of the type of write (PNT, LINE, etc.) and is, therefore, the vertex from which the relative offset applies.

Comp~rison lo~ic and result storage lo~ic 47 Comparison logic and result storage logic 47 will now be described with reference to Figures 7 and B. Comparison logic and result storage logic 47 compnses multiplexors 101, 103, lOS, 107 and 109 (see Figure 7), and comparators 121-124, multiplexors 131-146 and registers Rl-R44 o (see Figure 8~.

Registers Rl-lR44 store the results OI the operation of ct~mparators 121-124 as shown i~n Table II:
TABLE II
R1 XO:XClipMin R23 YO:YClipM~n R2 XO:XTestMin R24 YO:YTestMin R3 XO:XClipMax R25 YO:YIClipMax R4 XO:XTestMax R26 YO:YTestMax R5 Xl :XClipM~n R27 Y1 :YIClipMial R6 X1 :XTestMin R28 Yl:YTestMin R7 Xl:XClipMa~ R29 Yl:YIClipMax R8 Xl.XTestMax R30 Yl:YTestMax ~9 X2:XClipMin R31 Y2:YClipMill R10 X2:XI estMin R32 Y2:YTestMin R11 X2:XClil)Ma~ R33 Y2:YClipMax R12 X2:XTestMax R34 Y2:YTestMax R13 X3:XClipMin R35: Y3:YClipMin R14 X3:XTestMill R36 Y3:YTestMin R15 ~3:XClipMa~c R37 Y3:YClipMa R16 X3:XTestMax R38 Y3:YTestMa~
R17 XO:Xl R39 YO:YI
R18 XO:X2 R40 YO:Y2 R19 XO:X3 R41 YO:Y3 R20 Xl:X2 R42 Yl:Y2 ~..

~`" 1317~

R21 Xl :X3 3R~3 Yl :Y3 R22 X2:X3 R44 Y2:Y3 In Table II, e~cep~ing for the comparisons ~nvolving X~lipMin/Max, YClipMin/Max, XTestMin/Ma~, and YTestMin/Max which store a one bit 5 result, the indicated register stores a two bit result of a comparison between the two indicated values. lf the value on the left of the colon is greate~ than ~he value to the right of the colon, the binary value stored in the corresponding register is '10'; if the value on the le~t of the coion is less than the value to the right of the colon, the binary value seored in the 0 corresponding register is '01'; if the ~wo values are equal, the binary value stored in the corresponding register is '00'. For XClipMin, YClipMin, XTestMin, and YTestMin, if the coord~nate value compared is less, a '1' is stored, otherwise, a 'O' is stored. For XClipMa~ and YClipMa~, XTestMax, YTestMax if the value compared is greater, a '1' is stored, otherwise, a 'O' is 5 stored.

The inputs to multiplexors 101, 103, 105, 107 and 109 are from X/Y
coordinate registers 37, namely XOL,YOL - X31"Y3L, clip coordinate registers 39, namely XClipMin,YClipMin and XClipMax,YClipMax and test 20 window control 45, namely XTestMin, YTestMin, XTestMa~ and'YTestMax.
Of course, at any one time, the inputs to multiplexors 101, 103, 105, 107 and 109 are eithet X values or Y values as described above, based upon a l~IUX Enable signal generated by comparison control state machine 49.

Comparator 121 compares multiplexor 101 output and multiplexor 25 109 output. Similarly, comparators 122-124 compare multiplexor 103, 105 and 107 outputs on the one hand and multiplexor 109 output on the other. The outputs from comparators 121-124 are input to multiplexors ~3~70~

131-146 which direct the appropriate data to registers Rl-R44 to be loaded as follows.

The output from comparator 121 is connected to multiplexors 131-135, 13g and 143 which are used to load registers Rl, R2, R3, R~, R~, R9, R13, R17, R18, and R19, for X values and registers R23, R24, R25, R26, R27, R31, R35, R39, R40, and R41 for Y values as shown in Figure 8 and Table 11 below. In Table III, A, B, C,and D refer to comparators 121, 122, 123 and 1 24 respectiveiy.
0The output from comparator 122 is connected to multiplexors 132, 135, 136, 137, 138, 140, and 144 which are used tv load registers R2, RS, R6, R7, R8, R10, R14, R17, R20, and R21 for X values and registers R24, R27, R28, R29, R3û, R32, R36, R39, R42 and R43 for Y values as shown in Figure 8 and Table III.
The output from comparator 123 is connected to multiplexors 133, 137, 139, 140, 142, and 145 which are used to load registers R3, R7, R9, R10, R12, R15, R18, R20 and R22 for X values and registers R25, R29, R31, R32,, R34, R37, R40, R42, and R44 for Y vallles as shown in ~igure 8 and 2 0 I`able III.

The output from comparator 124 is connected to multiplexors 134, 138, 142, 143, 144~ 145 and 146 which are used to load registers R4, R8, R12, R13, R14, RlS, R16, Rl9, R21, and R22 for X values and registers R26, R30, R34, R35, R36, R37, R38, R41, R43 and R44 for Y values as shown in 25 Figure 8 and Table III.

The comparisons done and s~ored are those required by coordinate sequencing block 17 and functional address~g block 19 in order to properly execute supported operations (DRAW, also known as quadrilateral rendering, or BLIT) and perfomn proper clipping.

Comparison Control State Machine 42 Comparison control state machine 49 is logic which enables the Yarious comparators, multiplexors and registers in comparison logic and result storage 47. A truth table for absolute 10ading of the coordinate and 0 clipping registers by the compaIison control state machine 49 is shown in Table III for clock cycles O and 1, with comparators 121-124 referenced A, B, C and D respectively. Table III sets ~orth the output of each comparator 121-124 for each of the inputs XOL-X3L, XClipMin, XClipMa~c, XTestMin and XTestMax. In this connection, although Figure 8 shows that the outputs of 5 multiple~ors 101, 103, 105 and 107 are input into one side of comparators 121-124, with the output of comparatol 109 being input into the other side. For consistency, it is necessary to store the comparisons of XOL to XlL, XlL to X2L and X2L to X3L etc., rather ~han the other way around (e.g., XlL to XOL). For this ~eason, when the column labeled reverse is 20 "yes," the outputs ~om con parators 121-124 are reversed. This is handled by the right input of multiple~ors 131-146. The output from the irsdicated comparators 121-124 are directly input to the left side of the indicated multiple~or 131-146. The right multiplexor input receive the bit output from the indicated comparator in reverse bit order. Thust the column labeled reverse becomes the truth table for the MUX selec~ line lines for multiple~ors 131-146 for absolute coordinate loads.

`` ~3~7~2 TABI,E III

COMP~T03~ COh~PARlSONRI~VE~iE CYaE
WRlT~ TO XO
B XOL:XlL YES O
C XOL:X2L YES O
D XOL:X3L YES O
A XOL:XClipMin YE~ 1 B XOl,:XTestMinYES
C XOL:XClipMax YES
D XOL:XTestMa~cYE~ 1 WRlTE TO X 1 A XlL:XOL ~ O
C XlL:X21, YE~ O
lo D XlL:X3L YE~ O
A XlL:XClipMin YES
B XlL:XTestMin YE~ 1 C XlI,:XClipMa~YES
D XlL:XTestMax YES

A X2L:X(:L N~ O
B X2L:XlL N~ a D X2L:X3L YE~ O
A X2L:XClipM~n YE~ 1 B X2L:XTestMin YE~ 1 C X2L:XClipMax YE~ 1 D X2L:~TestMa~ YES 1 A X3L:XOL N~ O
B X3L:XlL N~ O
C X3L:X2L ND O
A X3L:XClipMin ~
B X3L:XTestMin YES
C X3L:XClipMa~
2 s D X3L:XTestMa~cY~iS 1 - ~ 3 ~ 2 CO~PARAIY)R COMPARlSON REVERSE~ cYn F, WRl~E TO XClipMin A~ XClipMin:XOL ~) O
B XClipMin:XlL NO O
C XClipMin:X2L Nl~ O
D XClipMin:X3L Nt) O
A XTestMin:XOL Nl~ 1 B XTestMin:XlL NO
C XTestMin:X2L N~ 1 D XTestl~,qin:X3L N~ 1 WRrrlE TO XClipMa~
A XClipMax:XOL N~ O
,B XClipMa~:XlL Nl:) O
C XClipMax:X2L NO O
D XClipMa~:X3L N[~ O
A XTestMax:XûL NQ
B XTestMa~:XlL ~) C Xl~stMax:X2L NO
D XTestMax:X3L N~ 1 The resul~s of Table 111 are repeated in a similar manner for YOL-Y3L, YClipMin, YClipMax, YTestMin and YTest:Max. Figure 9 shows the relative timings of the signals on DataIn, the register loading performed by raster offset registers 4l, XIY coordinate registers 37, clip coordinate registers 39 and comparison logic and result storage 47.

The comparison control state machine supports the indexed loading scheme as previously discussed u~ilizing both ~he index register value associated with a ~rite cycle and Table IV. Since the register pointed to by the index ~egister value is always written irrespective of the type of 2s inde~ed write, the appropriate Mux Enables for MUXes lOl, lO3, lOS and 107 are selected by the comparison control state machine assuming a s~ngle register wr;te to that coordinate. For example, if a rectangle wnte to ;' ' ' 31 3 ~ r~ O ~ 2 X with an index of 3 is received, ~he comparison logic will operate as if an explicit write to X3 was received and do comparisons X3L vs (XOL, XlL, X2L, XClipM~n, XClip~ , XTestMin, Xl`estMax~ as is required. Ihe dif~erence between an absolute loading of a register and an indexed (or 5 relative indexed) load is that in the indexed case, more than one coordinate storage register in 47 may be enabled to receive the comparison results and the multiplexor selects for multiple~ors 131-146 are generated aecording to Table IV instead of Table IIl.

. In the previous e~ample of a rectangle X write with an index of 3, comparison registers ~refer to Table II or Figure ~) R1-R3, R13-R16, R17-Rl9, and R21-R22 are written. The following registers pairs will store the same indi~idual comparison results: (R17, R21), (R18, R22), (Rl, R13), (R2, R14), (R3, R15), and (R4, R16).

TABLE IY

COMPARAIY~R COMPARISON TYPE REVERSE INDEX
B XO:Xl PNT y e s C XO:X2 PNT y e s D XO:X3 PNT yes C Xl:X2 PNI yes D Xl:X3 PN~ yes D X2:X3 PNT y e s B XO:Xl. LINE yes O
C XO:X2 LINE y e s O
D XO:X3 LlINE y e s O
C Xl:X2 LINE yes O
D ~l:X3 LINE yes O
D X2:X3 LINE y e s O

~ ~7Q~2`

CO~ARATOR COMPARISONTYPE R:~ERSE INDE~
A X0:Xl LINE n o k X0:X2 LINE n o A X0:X3 LINE n o C Xl:X2 LINE yes D Xl:X3 LINE yes D X2:X3 LINE y e s A X0:Xl L~ yes 2 C XO:X2 LIN~ y e s 2 D X0:X3 LIME y e s 2 B Xl:X2 LINE n o 2 B Xl:X3 L~E no 2 C X2:X3 L~E y e s 2 A X0:Xl L~E yes 3 C ~ X2 LINE y e s 3 D :%;0:X3 L~ y e s 3 C Xl:X2 LINE yes 3 D Xl:X3 LINE yes 3 C X2:X3 L~E n o 3 B ~:Xl T~CT y e s 0 C XO:X2 TRI/RBCT y e s O
D X0~ TRVRECT yes 0 C Xl :X~TRI/RECT y e s 0 D Xl:X3 TRVRECT yes 0 A X0:Xl .TRURECT n o A XO:X2 TRI/RECI ~ n o C Xl:X2 TRIJRECT~ yes D Xl:X3:TRI~RECT yes D X2:X3 TRI/R~CT y e s 1~ XO:X2 ~ RECT n o 2 ~ XO;X3 TRVR~T n o B ~1 :X2 ~VRECT n o 2 B Xl:X3 TRVRECI no 2 2 s D X2:X3 TRI/RECT y e s 2 -3~- :
.

' ' ~

'.: ' ~ , .
.

13~7~

COMPARATOR COMPARLSONl~E REVERSE INDE5 B X0:X1TRVE~ECT y e s 3 C X0:X2 TRURECT y e s 3 D ~0:X3 TRVRECT y e s 3 B Xl:X3 .TRl/RECT no 3 C X2:X3TRItRECT n o 3 B X0:X1 QUAD y e s O
C X0:X2 ~lJAD y e s 0 D X0:X3 QUAD y e s O
A ~0:Xl Q~JAD n o C Xl:X2 ~UAD y e s D Xl:X3 ~AD yes A X0:X2 QUAD n o 2 B Xl:X2 Q~JAD no 2 D X2:X3 QUAD y e s 2 A X0:X3 QUAD no 3 B Xl:X3 QUAD no 3 C X2:X3 QUAD n o 3 Status Generation Lo~ic 51 Status generation logic 51 generates the control signals HW/SW, Up/~R-to-L and HID/~IS. HW/SW is a 2 bit signal indica~ing whether the operaeion will be done by the hardware of the present invention or by soflware. Up/~-to-L iB a 2 bit signal indicating whether operation should bs :processed top to bottom. bottom to top, ~ight to left or left to right.
HIDMS is a two bit signal ~indicating whethèr the object to be drawn is hidden, i.e.~ behind the acti~e clip~ window or visible. To generate these ~signals,~status gene~ation logie 51;reGeives as inpu~s the registe-s Rl-R22 ~or X coordinates ~egisters R23-R44 for Y coordinates and the four 4 bit signals indicating~ths~urpeF 18 bits ars all l's and all 0's from-XIY

` ~3~7~

1 coordinate registers 37. The manner in which statlls generation logic generates the foregoing control signals will be explained with reference to Figures 10-14 which are t~uth tables ~or the logic performed ~y status generation logic S 1. The logic circuitry necessary to implement the truth 5 tables of Figures 10-14 is well within the capabilities of persons skilled in the relevant art.

Figure lO is a truth table utilizing comparison results for the XO
coordinate (XOI, and XOH). Truth tables utilizing compa~ison results for the Xl-X~ and YO-Y3 coordinates by substituting those coordinates and using YClipMin, YClipMax9 YTestMin and YTestMa~ in place of XClipMin, XClipMax, XIestMin and XTestl!lax ~or the Y coordinates. The left side of the table are the inputs and the right side are the outputs. In the table, the symbol "-" is a don't care; O and !O n eans the bus bit values are all l's 5 or not all l's respectively (from X/Y coord~nate registers 37); and Z and !Z
means the bus bit values are all O's or not all O's respectively (from X/Y
coordinate registers 37). "XO ~Inside 214" means the 32 bit XO coordinate is representable in 15 bits; "XO inside clip" means XO is on or inside the clip window X boundaries; "XO inside ~est" means XO is on or inside the test 20 window X boundaries. The outputs "XO < XClipMin", "XO < XTest~", "XQ >
X~lipMa~", and "XO > XIes~Ma~" are fedback and used as inputs. To ~orm the outputs, t~e ~nputs on a horizontal line are ANDed together and the outputs in a cs~lumn are ORed together. Thus, for example, refelTing to the ~irst two lines of Figure 10, if XO[31] (i.e., its sign bit) is O AND XO[30:14]
25 (i.e., its high order bits 14-30) are all O's, OR X0~31] is 1 AND XO[30:14~ are all l's, then XO is inside 214. Similarly, refernng to the last line of Figure lL317~2 10, if XO < XTestMin is 0 (i.e. false) AND X0 > XTestMax is 0, then X0 is inside the test wLndow.

Figures 1 la and 1 Ib are a truth table utilizing comparisons between 5 each of the four X vertices and each of the four 'Y vertices. As was the case with Figure 10, the values on a horizontal input line are ANDed together with the result being a logical 1 (~rue) or 0 (~alse) and the indicated outputs (except for top, bottom, right and left) are formed by ORing its corresponding column. The ou~puts top, bottom, right and le~t which are 0 shown as 0, 1, 2 or 3 are interpreted as follows. The value 0, 1, 2 or 3 speci~les which coordinate of X0-X3 or Y0-Y3 is the largest (top), smallest (bottom), rightmost (right) and leftmost (left). The symbols <,>,E,L and G
the input side indicate that the specified comparison result is less than, greater than, eqllal to, less than or equal to and greater than or equal to 5 respectively .
Al~hough the meaning of the outputs is defined by the ~able, the following sets forth in words w hat each indicated output means:

illegal - means that if a honzontal line is drawn through the object de~ined by the four pairs of vertices, it would cross two or more edges. An obJect which fonns a bow tie is an example of an object that would cause illegal to be true.
ho~iz-means all four vertices have the s~ne Y value.

2 5 vert-means all four vertices have the same X value.
rect-means the object defined by the four coordina~es forms a rectangle.

~317~2 line-means the object defined by the four coordinates forms a line.

EQ_OI means vertex 0 equals vertex 1. (defines the same point) EQ_12 means verte~ 1 equals vertex ~. (def~nes the same point) EQ_23 means vertex ~ equals vertex 3. (def~nes the same p~int) EQ_30 means vertex 3 equals vertex 0. (defines the same point) Figures 12a-12d define a truth table utilizing comparisons between the ~our X and the four Y vertices and the clipping bourldaries. The inputs top, bottom, right and left are from the truth table of Figures 1 la-l lb.
When the outputs lop visible, bottom visible, right visible and left visible are 1 (i.e. true), the object defined by the four coordinate pairs is inside the clip window. When surround clip is 1, the object is outside but 5 surrounding the clip window. Hidden is applicable only for quadrilaterals and indicates that all four vertices are all right, left, top or bottom of the clip window. Hidden 01 (re~ers to BLIT SRC rectangle) and hidden_23 (re~ers to BLIT DEST rectangle) have a sirnilar meaning for BLITs.

Figure 13 defines a truth table utilizing comparisons between the 20 four X and the four Y .rertices and the test window boundaries. The outputs "top within test" and "bottom within test", when true, mean that edge of the object is within fhe top or bottom boundaries of the test window, respecti~rely.

Figure 14 defines a truth table showing the direction in which to draw objects or per~rm BLITs in order t~ minimize page crossings and processing of clipped pi~Lels by generating the signals bli~ r-to-l, blil up, 13~0~2 1 draw r-to-l and draw up. These signals cornprise the signal Drawing Direction shown in Figure 2. Further details regardmg this aspect of the ~vention may be found in copending Canadian applicati.on ~eriat No. 612,525 fil~d Septemher 22, 19~9.
Based upon the truth tables of l~igures 10-14, status generation logic 51 generates the signals HW, SW, HID and VIS shown in Figure ~ as follows:

For quadrilateral objects-HW - hidden OR
0 surround clip OR
(NOT hidden AND
NOT illegal AND
all vertices are inside 214 AND
(all vertices are inside test OR
(line AND at least one endpoint is inside test) OR
(X0-X3 are inside test AND the top or bottom vertex is inside test) OR
rect).

SW = NOT HW.

HID = hidden ~o VlS = NOT hidden For BLITs-HW - hid_23 OR
(hid_01 AND BLll SRC_CHK=10) OR
(NOT hid_01 AND
2 5 BLlT SRC_CHK=10 AND
NOT hid_23 AND

- 4 1 -.

~3~ 7~2 the source rectangle is inside 214 AND the destination rectangle is inside 214) OR
(BI,lT_SRC_~-~l AND
NOT hid_23 AND
the source rectangle is inside 2l4 AND
~he destination rectangle is inside 214) where BLlT_SRC_C~ is a two bit value from the CPIJ which is set to 'l0' when it is desired to consider the relationship of the source rectangle to the clipping window. This is necessary because the various graphics software which may utili~e the present invention are inconsistent as to their treatment of the SRC rectangle and the clipping boundaries. For this reason, the preferred embodirnent has left BLlT SRC rectangle clip checking as a software selectable option (BLll-SRT-CHK~01 disables SRC
clip check, BLIT-SRC-C:HK=l0 enables SRC clip check).

5 SW = NOT HW.

H~D = hid_23 VIS = NOT hid_23 The preferred embodiment of the current invention has utili~ed a ~!
clock cycle coord~ate load stage ~llowed by a 2 clock cycle comparison stage. Whereas these two stages can be overlapped as described, the overall la~ency is 3 clock cycles, with new input receivable (or new results availa~lej every other clock cycle (i.e. 2 clock cycle throughput). The 2 examples have also shown coordinate staging logic 15 receiving data at the ~astest possible rate given ehis preferred embodiment. It ~hould be appreciated, however, to someone skilled in the art that the circuitry described will handle any slower (less frequen~) rate of data arriva1. lt ' ''~

~3~7 ~2 should also be çvident that at the e~pense of additional logic, a shorter overall latency and a shorter throughput are possible as simple extensions of the present inven~ion.

' ; ~20 :
:

.

Claims (6)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for loading four pairs of object coordinate registers with coordinates of an object to be displayed by a graphics subsystem, said object being one of a quadrilateral to be drawn and a block image to be moved, said apparatus including loading means for loading said object coordinate registers with said object coordinates;
a) loading control means coupled to an indexing register which cycles from 0, 1, 2 and 3, said loading control means for generating a set of control signals which, based upon the value in said indexing register, enable predetermined ones of said object coordinate registers to receive object coordinates received by an input means;
b) said input means coupled to said loading control means and said object coordinate registers for receiving from a source external to said apparatus, said object coordinates, and for storing said received coordinates in said object coordinate registers under control of said loading control means and said indexing register, whereby said object to be displayed is defined by a number of coordinates to uniquely define said object.

2. The apparatus defined by claim 1 wherein said input means comprises: .
means coupled to said external source and said object coordinate registers for placing a value received from said external source on a bus coupled to said object coordinate registers.

3. An apparatus for loading four pairs of registers with object coordinates of an object to be displayed by a graphics subsystem, said object being one of a quadrilateral to be drawn and a block image to be moved, said apparatus having a clip window with predetermined top, bottom, right and left clip coordinates, and a test window with predetermined X and y offsets from said top and bottom clip coordinates, and from said right and left clip coordinates, said object coordinates, said clip coordinates and said offsets for use in calculations for performing clipping of the object prior to said objects display, said apparatus including loading means for loading i) four pairs of object coordinate registers with said object coordinates, ii) a plurality of clip coordinate registers with said clip coordinates, and iii) a plurality of offset registers with said predetermined offset;
wherein said loading means comprises:
a) loading control means coupled to an indexing register which cycles from 0, 1, 2 and 3, said loading control means for generating a set of control signals which based upon the value in said indexing register, enable predetermined ones of said object coordinate registers to receive object coordinates received by an input means;
b) said input means coupled to said loading control means, said object coordinate registers and said clip coordinate registers for receiving from a source external to said apparatus, said object coordinates and said clip coordinates, and for storing said received coordinates in said object coordinate registers and said clip coordinate registers under control of said loading control means and said indexing register, whereby said object to be displayed is defined by a number of coordinates to uniquely define said object.

4. The apparatus defined by claim 3 wherein said input means comprises:
means coupled to said external source for placing a value received from said external source on a bus coupled to said object coordinate registers and said clip coordinate registers.

5. The apparatus defined by claim 3 further comprising a plurality of raster offset registers coupled to said bus, said raster offset registers being loaded under control of said loading control means.

6. The apparatus defined by claim 5 wherein said input means comprises:
adder means coupled to said external source for adding to a value received from said external source a value in a predetermined one of said plurality of raster offset registers, and placing the sum on a bus coupled to said object coordinate registers and said clip coordinate registers.