CA1303227C - Synchronizing signal automatic selecting circuit - Google Patents
Synchronizing signal automatic selecting circuitInfo
- Publication number
- CA1303227C CA1303227C CA000573370A CA573370A CA1303227C CA 1303227 C CA1303227 C CA 1303227C CA 000573370 A CA000573370 A CA 000573370A CA 573370 A CA573370 A CA 573370A CA 1303227 C CA1303227 C CA 1303227C
- Authority
- CA
- Canada
- Prior art keywords
- synchronizing signal
- signal
- horizontal
- vertical synchronizing
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/715—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using frame interline transfer [FIT]
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronizing For Television (AREA)
- Controls And Circuits For Display Device (AREA)
- Processing Of Color Television Signals (AREA)
- Television Systems (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A synchronizing signal automatic selecting circuit comprises a signal inverter for inverting synchronizing signal from synchronizing signal separating circuit, a synchronizing signal detector for detecting synchronizing signal when synchronizing signal is input to horizontal, horizontal/vertical synchronizing signal input terminal and ground output signal of the signal inverter, a polarity detecting circuit for detecting the synchronizing signal polarity of the horizontal and horizontal/vertical synchronizing signal input terminal and a vertical synchronizing signal separator for separating the vertical synchronizing signal from output signal of a transistor.
The circuit is designed to select automatically with priority the synchronizing signal when the composite video signal and the synchronizing signal are input at the same time to a monitor used for a peripheral equipment of a computer. It is not necessary to change the switch separately.
A synchronizing signal automatic selecting circuit comprises a signal inverter for inverting synchronizing signal from synchronizing signal separating circuit, a synchronizing signal detector for detecting synchronizing signal when synchronizing signal is input to horizontal, horizontal/vertical synchronizing signal input terminal and ground output signal of the signal inverter, a polarity detecting circuit for detecting the synchronizing signal polarity of the horizontal and horizontal/vertical synchronizing signal input terminal and a vertical synchronizing signal separator for separating the vertical synchronizing signal from output signal of a transistor.
The circuit is designed to select automatically with priority the synchronizing signal when the composite video signal and the synchronizing signal are input at the same time to a monitor used for a peripheral equipment of a computer. It is not necessary to change the switch separately.
Description
~3~322~
SYNCHRONIZING SIGNAL AUTOMATIC SELECTING CIRCUIT
The present invention relates to a synchronizing signal selecting circuit which can select one of various synchronizing signals when various synchronizing ~ignals are input to a monitor u~ed for peripheral e~uipment of a computer. More particularly the invention relates to a synchronizing signal automatic selecting circuit designed to select the synchronizing signal with priority where a composite video signal and a synchronizing signal are input to the monitor at the same time.
The conventional synchronizing signal selecting cirauit is designed -to select one synchronizing signal according to the selection o two switche~. When the switches are short-circuited to a pair of f irst fixed terminals on one side, horiæontal and vertical synchronizing ~ignal~ inputted to a color signal input terminal and then ~ynchronized and separated at the synahronizing signal separating circuit are inputtedr respectively, to the horizontal ~ynchronizing ~ignal proce~sing aircuit and the vertical synchronizing signal processing circuit through the switches. When the switches are short-circuited to a pair o~ second fixed terminals the horizonkal and vertical synchronizing signals inputted to the synchronizing ~ignal inputted terminals are inputted, respectively, to the horizontal synchronizing ~ignal processing circuit and the vertical synchronizing signal processing circuit through the switches. When the ~witches are short-circuited to a pair of third fixed terminals on the other side, the horizontal and vertical synchronizing ~ignals inputted to the horizontal and vertical ~ynchronizing signals input terminal and synchronized and separated at the ~ynchronizing signal separating circuit are inputted to the horizontal synchronizing signal processing circuit and the yertical synchronizing signal processing circuit through the switches. The conventional circuit thu~ has a di~advantage in that the user must A ~
~9 3~3227 select the synchronizing signal by changing the two ~witches one by one.
Therefore the present invention seeks to provide a synchronizing signal ~electing circuit for selecting automatically the synchronizing signal without changing the switc~l.
Accordingly, in a first aspect, the invention provides a synchronizing signal automatic selecting circuit having a -~
horizontal and horizontal/vertical synchronizing signal terminal HHV which circuit is coupled to a horizontal ~ynchronizing signal processing circuit, a vertical synchronizing signal processing circuit, and vertical synchroniæing ~ignal input terminal V comprising a ~ynchronizing signal separating circuit for separating a synchroni2ing signal from color ~ignals or a color signal, a signal inverter means for invert.ing the ~ynchronizing signal output from ~aid synchronizing signal separating circuit, a ~ynchronizing signal detecting element for detecting the synchronizing ~ignal when the synchronizing signal is inputted to the horizontal and horizontal/vertical synchronizing signal input terminal HHV
and grounding the output signal of said signal inverte.r mean~, a polarity detecting means for detecting the synchronizing ~ignal polarity of said hor.izontal and horizontal/vertical synchronizing signal input at said terminal ~HV, an exclusive OR-gate for combining the output signal of said polarity detecting means and the synchronizing ~ignal of the horizontal and horizontal/vertical synchronizing ~ignal input terminal, a fir~t transistor for inverting the output signal of said exclusive OR-gate or the output ~ignal of the ~ignal inverted mean~ and applying it to the horizontal synchronizing signal processing circuitl a vertical synchronizing signal separator means for separating the vertical synchronizing signal from the output ~ignal of said first transistor, a ~econd transistor for inverting ~3~7 the output ~ignal of said vertical`synchronizing signal separator means and an excluæive OR-gate for combining the output signal of said second transistor and the vertical synchronizing signal of the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
In a second aspect, the invention is a synchronizing signal automatic selecting circuit having a horizontal and horizontal/vertical synchronizing signal terminal which circuit is coupled to a horizontal and vertical synchronizing signal processing circuit comprising a synchronizing signal separating circuit for separating a synchronizing signal from color signals or a color signal input, a signal inverter means for inverting the synchronizing signal output from said synchronizing signal separating aircuit, a synchronizing signal detecting means for detecting the synahronizing signal when the ~ynchronizing signal is inputted to the horizontal and horizontal/vertical ~ynchroniæing s.ignal input terminal and disabling the output ~ignal of said signal inverter means, a polarity detecting means for detecting the synchronizing signal polaxity o~ said horizontal and horizontal/vertical synchronizing signal input, irst combining means for combining tbe output signal oi said polarity detecting 2S means and the synchronizing signal of the horizontal and horizontal/vertical synchronizing signal input terminal, a first inverting means for inverting the output æignal of said first combining means or the output signal of the signal inverter means and applying it to the horizontal synchronizing signal processing circuit, a vertical synchronizing signal ~eparator means for separating the vertical synchronizing signal if present from the output signal of said first inverting means r a second inverting means for inverting the output signal of said vertical synchronizing signal separator, and a second combining means for combining the output signal of æ~id second inverting means and the vertical synchronizing signal at ~3z~7 the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
In a further aspect, the invention is a synchronizing ~ignal automatic selecting circuit for separating a synchronizing signal from one of (a) color signals or a color signal at an input terminal G, (b) a horizontal and horizontal/vertical synchronizing signal at an input terminal ~V, or ~c~ a vertical synchronizing signal at an input terminal V, comprising a synchronizing signal separating circuit connected to the terminal G, ~ignal inverter means connected to and for inverting the synchronizing signal output from said synchronizing signal separating circuit, synchronizing signal detecting means connected to the terminal HHV for detecting when a æynchronizing ~ignal iæ inputted and disabling the output signal of said signal inverter means, polarity detecting means conneted to and for detecting the ~ignal polarity of ~ignals at input terminal HHV, first logical means for logically combining the output signal of said polarity detecting mean4 and the synchronizing ~ignal at input terminal HHV, first inverter means ~or applying the output signal of æaid first logiaal means or the output ~ignal of the ~ignal inverter mean~ to a horizontal synchronizing signal proces~ing circuit, vertical synchronizing signal separator means for separating the vertical synchronizing æignal if present from the output signal of said first inverter means, ~econd inverter means connected to the output of ~aid vertical synchronizing signal ~eparator means, second logical mean3 for logically combining the output signal of said second inverter means and a signal at input terminal V, and mean~ for connecting the output of the ~econd logical meanæ to a vertical synchronizing ~ignal processing circuit, The present invention and the prior art will now be A
~.311~22~7 de~cribed in detail with reference to the accompanying drawings, in which:
FIG. 1 is a conventional y.nchronizing signal selecting circuit, FIG. 2 is a synchronizing signal automatic selecting circuit according to the present invention, FIGS~ 3 to 5 are wave-form views of each part of FIG.
SYNCHRONIZING SIGNAL AUTOMATIC SELECTING CIRCUIT
The present invention relates to a synchronizing signal selecting circuit which can select one of various synchronizing signals when various synchronizing ~ignals are input to a monitor u~ed for peripheral e~uipment of a computer. More particularly the invention relates to a synchronizing signal automatic selecting circuit designed to select the synchronizing signal with priority where a composite video signal and a synchronizing signal are input to the monitor at the same time.
The conventional synchronizing signal selecting cirauit is designed -to select one synchronizing signal according to the selection o two switche~. When the switches are short-circuited to a pair of f irst fixed terminals on one side, horiæontal and vertical synchronizing ~ignal~ inputted to a color signal input terminal and then ~ynchronized and separated at the synahronizing signal separating circuit are inputtedr respectively, to the horizontal ~ynchronizing ~ignal proce~sing aircuit and the vertical synchronizing signal processing circuit through the switches. When the switches are short-circuited to a pair o~ second fixed terminals the horizonkal and vertical synchronizing signals inputted to the synchronizing ~ignal inputted terminals are inputted, respectively, to the horizontal synchronizing ~ignal processing circuit and the vertical synchronizing signal processing circuit through the switches. When the ~witches are short-circuited to a pair of third fixed terminals on the other side, the horizontal and vertical synchronizing ~ignals inputted to the horizontal and vertical ~ynchronizing signals input terminal and synchronized and separated at the ~ynchronizing signal separating circuit are inputted to the horizontal synchronizing signal processing circuit and the yertical synchronizing signal processing circuit through the switches. The conventional circuit thu~ has a di~advantage in that the user must A ~
~9 3~3227 select the synchronizing signal by changing the two ~witches one by one.
Therefore the present invention seeks to provide a synchronizing signal ~electing circuit for selecting automatically the synchronizing signal without changing the switc~l.
Accordingly, in a first aspect, the invention provides a synchronizing signal automatic selecting circuit having a -~
horizontal and horizontal/vertical synchronizing signal terminal HHV which circuit is coupled to a horizontal ~ynchronizing signal processing circuit, a vertical synchronizing signal processing circuit, and vertical synchroniæing ~ignal input terminal V comprising a ~ynchronizing signal separating circuit for separating a synchroni2ing signal from color ~ignals or a color signal, a signal inverter means for invert.ing the ~ynchronizing signal output from ~aid synchronizing signal separating circuit, a ~ynchronizing signal detecting element for detecting the synchronizing ~ignal when the synchronizing signal is inputted to the horizontal and horizontal/vertical synchronizing signal input terminal HHV
and grounding the output signal of said signal inverte.r mean~, a polarity detecting means for detecting the synchronizing ~ignal polarity of said hor.izontal and horizontal/vertical synchronizing signal input at said terminal ~HV, an exclusive OR-gate for combining the output signal of said polarity detecting means and the synchronizing ~ignal of the horizontal and horizontal/vertical synchronizing ~ignal input terminal, a fir~t transistor for inverting the output signal of said exclusive OR-gate or the output ~ignal of the ~ignal inverted mean~ and applying it to the horizontal synchronizing signal processing circuitl a vertical synchronizing signal separator means for separating the vertical synchronizing signal from the output ~ignal of said first transistor, a ~econd transistor for inverting ~3~7 the output ~ignal of said vertical`synchronizing signal separator means and an excluæive OR-gate for combining the output signal of said second transistor and the vertical synchronizing signal of the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
In a second aspect, the invention is a synchronizing signal automatic selecting circuit having a horizontal and horizontal/vertical synchronizing signal terminal which circuit is coupled to a horizontal and vertical synchronizing signal processing circuit comprising a synchronizing signal separating circuit for separating a synchronizing signal from color signals or a color signal input, a signal inverter means for inverting the synchronizing signal output from said synchronizing signal separating aircuit, a synchronizing signal detecting means for detecting the synahronizing signal when the ~ynchronizing signal is inputted to the horizontal and horizontal/vertical ~ynchroniæing s.ignal input terminal and disabling the output ~ignal of said signal inverter means, a polarity detecting means for detecting the synchronizing signal polaxity o~ said horizontal and horizontal/vertical synchronizing signal input, irst combining means for combining tbe output signal oi said polarity detecting 2S means and the synchronizing signal of the horizontal and horizontal/vertical synchronizing signal input terminal, a first inverting means for inverting the output æignal of said first combining means or the output signal of the signal inverter means and applying it to the horizontal synchronizing signal processing circuit, a vertical synchronizing signal ~eparator means for separating the vertical synchronizing signal if present from the output signal of said first inverting means r a second inverting means for inverting the output signal of said vertical synchronizing signal separator, and a second combining means for combining the output signal of æ~id second inverting means and the vertical synchronizing signal at ~3z~7 the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
In a further aspect, the invention is a synchronizing ~ignal automatic selecting circuit for separating a synchronizing signal from one of (a) color signals or a color signal at an input terminal G, (b) a horizontal and horizontal/vertical synchronizing signal at an input terminal ~V, or ~c~ a vertical synchronizing signal at an input terminal V, comprising a synchronizing signal separating circuit connected to the terminal G, ~ignal inverter means connected to and for inverting the synchronizing signal output from said synchronizing signal separating circuit, synchronizing signal detecting means connected to the terminal HHV for detecting when a æynchronizing ~ignal iæ inputted and disabling the output signal of said signal inverter means, polarity detecting means conneted to and for detecting the ~ignal polarity of ~ignals at input terminal HHV, first logical means for logically combining the output signal of said polarity detecting mean4 and the synchronizing ~ignal at input terminal HHV, first inverter means ~or applying the output signal of æaid first logiaal means or the output ~ignal of the ~ignal inverter mean~ to a horizontal synchronizing signal proces~ing circuit, vertical synchronizing signal separator means for separating the vertical synchronizing æignal if present from the output signal of said first inverter means, ~econd inverter means connected to the output of ~aid vertical synchronizing signal ~eparator means, second logical mean3 for logically combining the output signal of said second inverter means and a signal at input terminal V, and mean~ for connecting the output of the ~econd logical meanæ to a vertical synchronizing ~ignal processing circuit, The present invention and the prior art will now be A
~.311~22~7 de~cribed in detail with reference to the accompanying drawings, in which:
FIG. 1 is a conventional y.nchronizing signal selecting circuit, FIG. 2 is a synchronizing signal automatic selecting circuit according to the present invention, FIGS~ 3 to 5 are wave-form views of each part of FIG.
2.
FIG. 1 shows the prior art. As shown the conventional æynchronizing signal selecting circui~ is de~igned to select one synchronizing signal according to the æelection of switches SWl,SW2. When switches SWl,SW2 are short-circuited to fixed terminals al,a2 on one side, horizontal and vertical synchronizing signals inputted to a color ~ignal input terminal G and then synchronized and separated at the synchronizing signal separating circuit 2 are inputted, respectively, to the horizontal synchronizing ~ignal processing circuit 3 and the vertical synchronizing signal processing circuit 4 through the ~witches SW1,SW2.
When switche~ SWl,SW2 are short-circuited to the intermediate fixed terminals bl,b2, the horizontal and vertical synchronizing signals inputted to the synchronizing si~nal input terminals H, V are inputted~
re~pectively, to the horizontal synchronizing signal processing circuit 3 and the vertical synchronizing signal proces~ing circuit 4 through switches SWl, SW2. When ~witches SWl, SW2 are short-circuited to the fixed terminals Cl, C2 on the other side~ the horizontal and vertical synchronixing signals inputted to the horizontal and vertical synchronizing ~ignals input terminal ~V and synchronized and separated at the synchronizing ~ignal separating circuit 5 are inputted to the horizontal synchronizing signal processing circuit 3 and the vertical synchronizing signal processing circuit 4 through switches 5Wl,SW2. Therefore, the conventional circuit has the disadvantage in that the user must select the synchronizing . ~ .
~303~27 signal by changing the switches SW1, SW2 one by one~
FIG. 2 is a synchronizing signal automatic selection circuit according to the present invention. As shown in FIG. 2, the output side of a synchronizing signal separating circuit 2 connected to a color signal input terminal G is connected to the base of a transistor TR1 through a resîstor R2. A signal inverter 6 consists of an exclusive OR-gate EXOK1 and a resistor Rl. Horizontal and horizontal/vertical synchronizing signal input terminal HHV
is connected to the connecting point of the output side of the signal inverter 6 and the resi~tor R2 through a synchronizing signal detecting circuit 8. Circuit 8 consists of capacitor~ C3,C4, diodes Dl,D2, resi~tors Rg,Rg and transistor TR3. The horizontal and horizontal/vertical synchronizing signal input terminal HHV is also connected to one side input terminal of the exclusive OR-~ate EXOR3 and, at the same time, to the other side input terminal of the exclu~ive OR-gate EXOR3 through a polarity detecting circuit 9. T~e output terminal of the exclusive OR-gate EXOR3 is connected to the base of the tran~istor TRl through the re~iætor Rll. The collector of the transistor TR1 is connected to the input terminal of the horizontal synchronizing signal processing circuit 3. The resistor R3 is connected to the power terminal Vcc and, at the same time, to the base of the transistor TR2 through the vertical ~ynchronizing ~ignal separator 7 consisting of resistors R4, Rs and capacitors Cl,C2.
The collector of the transistor TR2 is connected to one input terminal of the exclusive OR-gate EXOR2. The resistor R6 i~ connected to the power terminal Vcc. The vertical synchronizing signal input terminal V is connected to the other input terminal of the exclu~ive OR-gate EXOR2 and the output terminal of the exclusive ORgate EXOR2 is connected to the input terminal of the vertical synchronizing signal processing circuit 4. The resistor R3 is connected to the power terminal Vcc. The drawings show A
~.3~23227 color signal input terminals R and B and a video processing circuit 1.
The operation and effect of the present invention as de~cribed above will now be de~cribed in more detail with reference to the wave~form views of FIGS. 3 to 5.
Aæ the power ~ource is supplied to the power terminal Vcc, and the color si~nal ~which is a co~posite video signal) is inputted to the color signal input terminals R,B,G, the color signal is inputted to the video processing circuit l and processed there4 ~t this moment the color signal inputted to the color signal input terminal G is inputted to the synchronizing signal separating circuit 2.
The synchronizing æignal of the color signals is thus outputted as shown in FIG. 3~A). The output synchronizing signal is inverted in, and outputted from, the signal inverter 6 as shown in FIG. 3(B).
When no synchronizing ~ignal is .inputted to the horizontal 10 and horizontal/vertical synahronizing signal input terminal HHV, the transistor TR3 of the synchronizing signal det~c~ing element 8 turnæ to O~F, and a high level ~ignal is outputted to the collector thereof and no synchronizing signal polarity being detected from the polarity detecting circu.it 9, a low level signal is outputted to the output terminal ~o that low level signals are output aontinuously to the output terminal of the exclusive OR~gate EXOR3. Accordingly the æynchronizing signal output from the signal inverter 6 is applied to the base of the transistor TR1 through the resi~tor R2 so that the synchronizing signal is inverted and output to the collector as shown in FIG. 3(C).
As described above, the synchroni~ing signal output to the collector of the transistor TR1 is applied to, and processed in, the horizontal synchronizing signal proceæsing circuit 3. Since the synchronizing signal is applied to the vertical synchronizing signal separator 7, rA~ .
the vertical synchronizing signal is separated as shown in FIG. 3~D), and applied to the base of the transistor TR2.
Accordingly the synchronizing signal applied to the base of the transistor TR2 is inverted as shown in FIG. 3(B). The synchronized signal is outputted to the collector thereof and applied to the other input terminal of the exclusive OR-gate EXOR2. When no vertical synchronizing signal is, at this moment, inputted to the vertical synchronizing signal input terminal V, a low level signal is applied to the other input terminal of the exclusive OR-gate EXOR2 as shown in FIG. 3~F). Thu~ the vertical synchronizing ~ignal applied to the o-ther input terminal of the exclusive OR-gate EXOR2 i~ inverted and outputted as shown in FIG. 3~G).
This vertical synchronizing signal is applied to, and processed in, the vertical synchronizing signal processing circuit 4.
Meanwhile the vert.ical synchronizing sigrlal and horiz-ontal synchronizing signal, separated as shown in FIG. 4(A) and 4~B), are inputted to the vertical ~ynchronizing signal input terminal V and the horizontal and horizontal/vertical ~ynchronizing signal input terminal H~V, respectively. The hori~ontal ~ynchronizing signal is full wave rectified at the capa~itor~ C3,C4 and diodes Dl,D~ of the ~ynchronizing signal detecting element 8 and then applied to the base of the transistor TR3 so that the transi~tor TR3 become~ ON-state. Consequently at this moment the synchronizing signal outputted from the signal inverter 6 flows to ground through the transi~tor TR3. Since the horizontal ~ynchronizing signal is applied to one input terminal of the exclusive OR-gate EXO~3, and at the ~ame time the polarity of said horizontal ~ynchronizing signal is de$ected from the polarity detecting circuit 9, a high Ievel signal is applied to the other input terminal of the exclusive O~-gate EXOR3 as shown in FIG~ 4~C). Accordingly the horizontal synchronizing signal applied to the one input terminal of the exclusive OR-gate EXOR3 is inverted at and outputted from the output terminal of said exclusive ,~
~3(~3ZX7 9 _ OR-gate EXOR3 as shown in FIG. 4tD), This output ~ignal is applied to the ba~e of transistor TR1 through the resiætor R11 so that the horizontal synchronizing signal i~
outputted fro~ the collector thereof as shown in FIG. 4(E).
Thi~ output horizontal synchroniæing signal is applied to, and proce~sed in, the horizontal synchr~nizing ~ignal processing circuit 3. The horizontal synchronizing signal is applied to the vertical synchronizing signal separator 7. However, as the horizontal synchronizing ~ignal includes no vertical synchronizing signal, a low level signal is outputted from the output side of the vertical synchronizing signal sepaxator 7 as shown in FIG. 4(F).
Accordingly the transi~tor TR2 turns into OF~ so that high level signal is applied to the other side input terminal of the ex~lusive OR-gate EXOR2 as shown in FIG. 4(G~.
Therefore, the vertical synchronizing signal inputted to the vert.ical ~ynahronizing signal input terminal V is inverted in the exclusive OR-gate EXOR2, as ~hown in FIG.
4~H), and applied to the vertical synchronizing signal proces~ing ciraui.t 4.
Meanwhile, and as æhown in FIG, 5(A), when the synchronizing signal in which the horizontal and vertical synchronizing signals are combined, is inputted to the horizontal and horizontal/vert.ical ~ynchronizing signal input terminal HHV, the synchronizing si~nal is detected at the synchronizing signal detecting circuit 8 and the transistor TR3 becomes ON-state. Accordingly the output ~ignal of the signal inverter 6 flows to ground. A high level signal i~ outputted from the polarity detecting circuit 9 as shown in FIG. 5(B) and applied to the other input terminal of the exclu3ive OR gate EXOR3.
Therefore, the synchronizing ~ignal inputted to the horizontal and horizontal/vertical synchronizing signal input terminal HHV i~ inverted at the exclusive OR-gate A
~ 10 -EXOR3 as shown in FIG. 5 IC) and inverted again at the transistor TRl as shown in FIG. 5(D) and applied to the ho.rizontal synchronizing signal processing circui-t 3. The vertical synchronizing signal contained in the synchronizing signals outputted to the collector of the transistor TR1 is separated at the vertical synchronizing signal separator 7 as shown in FIG. 5~E) and applied to the ba~e of the transistor TR2. Con~equently the vertical synchronizing signal is outputted to the collector of the transi~tor TR2 as shown in FIG~ 5~E~) and applied to the other input terminal of the exclusive OR-gate EXOR2o Since no vertical synchronizing signal i~ inputted to -the vertical synchronizing ~ignal input terminal V and a low level signal is thereby applied to one input terminal of the exclusive OR-gate EXOR2, as ~hown in FIG. 5(G), the vertical ~ynchroni~ing signal applied to the other input terminal from the exclusive OR-gate EXOR2 is inverted as shown in FIG. 5~H) and appl.ied to the vertical synchronizing signal proaessing circuit 4.
As described above in detail, the present invention makes it possible to select automatically the synchronizing signal without changing the ~witche~ separately. Where the composite video signal and the synchronizing signal are input together at the same time, the .synchronizing signal of the composite video signal is cut off and the synchronizing signal separately input is selected.
; A
.~ .
FIG. 1 shows the prior art. As shown the conventional æynchronizing signal selecting circui~ is de~igned to select one synchronizing signal according to the æelection of switches SWl,SW2. When switches SWl,SW2 are short-circuited to fixed terminals al,a2 on one side, horizontal and vertical synchronizing signals inputted to a color ~ignal input terminal G and then synchronized and separated at the synchronizing signal separating circuit 2 are inputted, respectively, to the horizontal synchronizing ~ignal processing circuit 3 and the vertical synchronizing signal processing circuit 4 through the ~witches SW1,SW2.
When switche~ SWl,SW2 are short-circuited to the intermediate fixed terminals bl,b2, the horizontal and vertical synchronizing signals inputted to the synchronizing si~nal input terminals H, V are inputted~
re~pectively, to the horizontal synchronizing signal processing circuit 3 and the vertical synchronizing signal proces~ing circuit 4 through switches SWl, SW2. When ~witches SWl, SW2 are short-circuited to the fixed terminals Cl, C2 on the other side~ the horizontal and vertical synchronixing signals inputted to the horizontal and vertical synchronizing ~ignals input terminal ~V and synchronized and separated at the synchronizing ~ignal separating circuit 5 are inputted to the horizontal synchronizing signal processing circuit 3 and the vertical synchronizing signal processing circuit 4 through switches 5Wl,SW2. Therefore, the conventional circuit has the disadvantage in that the user must select the synchronizing . ~ .
~303~27 signal by changing the switches SW1, SW2 one by one~
FIG. 2 is a synchronizing signal automatic selection circuit according to the present invention. As shown in FIG. 2, the output side of a synchronizing signal separating circuit 2 connected to a color signal input terminal G is connected to the base of a transistor TR1 through a resîstor R2. A signal inverter 6 consists of an exclusive OR-gate EXOK1 and a resistor Rl. Horizontal and horizontal/vertical synchronizing signal input terminal HHV
is connected to the connecting point of the output side of the signal inverter 6 and the resi~tor R2 through a synchronizing signal detecting circuit 8. Circuit 8 consists of capacitor~ C3,C4, diodes Dl,D2, resi~tors Rg,Rg and transistor TR3. The horizontal and horizontal/vertical synchronizing signal input terminal HHV is also connected to one side input terminal of the exclusive OR-~ate EXOR3 and, at the same time, to the other side input terminal of the exclu~ive OR-gate EXOR3 through a polarity detecting circuit 9. T~e output terminal of the exclusive OR-gate EXOR3 is connected to the base of the tran~istor TRl through the re~iætor Rll. The collector of the transistor TR1 is connected to the input terminal of the horizontal synchronizing signal processing circuit 3. The resistor R3 is connected to the power terminal Vcc and, at the same time, to the base of the transistor TR2 through the vertical ~ynchronizing ~ignal separator 7 consisting of resistors R4, Rs and capacitors Cl,C2.
The collector of the transistor TR2 is connected to one input terminal of the exclusive OR-gate EXOR2. The resistor R6 i~ connected to the power terminal Vcc. The vertical synchronizing signal input terminal V is connected to the other input terminal of the exclu~ive OR-gate EXOR2 and the output terminal of the exclusive ORgate EXOR2 is connected to the input terminal of the vertical synchronizing signal processing circuit 4. The resistor R3 is connected to the power terminal Vcc. The drawings show A
~.3~23227 color signal input terminals R and B and a video processing circuit 1.
The operation and effect of the present invention as de~cribed above will now be de~cribed in more detail with reference to the wave~form views of FIGS. 3 to 5.
Aæ the power ~ource is supplied to the power terminal Vcc, and the color si~nal ~which is a co~posite video signal) is inputted to the color signal input terminals R,B,G, the color signal is inputted to the video processing circuit l and processed there4 ~t this moment the color signal inputted to the color signal input terminal G is inputted to the synchronizing signal separating circuit 2.
The synchronizing æignal of the color signals is thus outputted as shown in FIG. 3~A). The output synchronizing signal is inverted in, and outputted from, the signal inverter 6 as shown in FIG. 3(B).
When no synchronizing ~ignal is .inputted to the horizontal 10 and horizontal/vertical synahronizing signal input terminal HHV, the transistor TR3 of the synchronizing signal det~c~ing element 8 turnæ to O~F, and a high level ~ignal is outputted to the collector thereof and no synchronizing signal polarity being detected from the polarity detecting circu.it 9, a low level signal is outputted to the output terminal ~o that low level signals are output aontinuously to the output terminal of the exclusive OR~gate EXOR3. Accordingly the æynchronizing signal output from the signal inverter 6 is applied to the base of the transistor TR1 through the resi~tor R2 so that the synchronizing signal is inverted and output to the collector as shown in FIG. 3(C).
As described above, the synchroni~ing signal output to the collector of the transistor TR1 is applied to, and processed in, the horizontal synchronizing signal proceæsing circuit 3. Since the synchronizing signal is applied to the vertical synchronizing signal separator 7, rA~ .
the vertical synchronizing signal is separated as shown in FIG. 3~D), and applied to the base of the transistor TR2.
Accordingly the synchronizing signal applied to the base of the transistor TR2 is inverted as shown in FIG. 3(B). The synchronized signal is outputted to the collector thereof and applied to the other input terminal of the exclusive OR-gate EXOR2. When no vertical synchronizing signal is, at this moment, inputted to the vertical synchronizing signal input terminal V, a low level signal is applied to the other input terminal of the exclusive OR-gate EXOR2 as shown in FIG. 3~F). Thu~ the vertical synchronizing ~ignal applied to the o-ther input terminal of the exclusive OR-gate EXOR2 i~ inverted and outputted as shown in FIG. 3~G).
This vertical synchronizing signal is applied to, and processed in, the vertical synchronizing signal processing circuit 4.
Meanwhile the vert.ical synchronizing sigrlal and horiz-ontal synchronizing signal, separated as shown in FIG. 4(A) and 4~B), are inputted to the vertical ~ynchronizing signal input terminal V and the horizontal and horizontal/vertical ~ynchronizing signal input terminal H~V, respectively. The hori~ontal ~ynchronizing signal is full wave rectified at the capa~itor~ C3,C4 and diodes Dl,D~ of the ~ynchronizing signal detecting element 8 and then applied to the base of the transistor TR3 so that the transi~tor TR3 become~ ON-state. Consequently at this moment the synchronizing signal outputted from the signal inverter 6 flows to ground through the transi~tor TR3. Since the horizontal ~ynchronizing signal is applied to one input terminal of the exclusive OR-gate EXO~3, and at the ~ame time the polarity of said horizontal ~ynchronizing signal is de$ected from the polarity detecting circuit 9, a high Ievel signal is applied to the other input terminal of the exclusive O~-gate EXOR3 as shown in FIG~ 4~C). Accordingly the horizontal synchronizing signal applied to the one input terminal of the exclusive OR-gate EXOR3 is inverted at and outputted from the output terminal of said exclusive ,~
~3(~3ZX7 9 _ OR-gate EXOR3 as shown in FIG. 4tD), This output ~ignal is applied to the ba~e of transistor TR1 through the resiætor R11 so that the horizontal synchronizing signal i~
outputted fro~ the collector thereof as shown in FIG. 4(E).
Thi~ output horizontal synchroniæing signal is applied to, and proce~sed in, the horizontal synchr~nizing ~ignal processing circuit 3. The horizontal synchronizing signal is applied to the vertical synchronizing signal separator 7. However, as the horizontal synchronizing ~ignal includes no vertical synchronizing signal, a low level signal is outputted from the output side of the vertical synchronizing signal sepaxator 7 as shown in FIG. 4(F).
Accordingly the transi~tor TR2 turns into OF~ so that high level signal is applied to the other side input terminal of the ex~lusive OR-gate EXOR2 as shown in FIG. 4(G~.
Therefore, the vertical synchronizing signal inputted to the vert.ical ~ynahronizing signal input terminal V is inverted in the exclusive OR-gate EXOR2, as ~hown in FIG.
4~H), and applied to the vertical synchronizing signal proces~ing ciraui.t 4.
Meanwhile, and as æhown in FIG, 5(A), when the synchronizing signal in which the horizontal and vertical synchronizing signals are combined, is inputted to the horizontal and horizontal/vert.ical ~ynchronizing signal input terminal HHV, the synchronizing si~nal is detected at the synchronizing signal detecting circuit 8 and the transistor TR3 becomes ON-state. Accordingly the output ~ignal of the signal inverter 6 flows to ground. A high level signal i~ outputted from the polarity detecting circuit 9 as shown in FIG. 5(B) and applied to the other input terminal of the exclu3ive OR gate EXOR3.
Therefore, the synchronizing ~ignal inputted to the horizontal and horizontal/vertical synchronizing signal input terminal HHV i~ inverted at the exclusive OR-gate A
~ 10 -EXOR3 as shown in FIG. 5 IC) and inverted again at the transistor TRl as shown in FIG. 5(D) and applied to the ho.rizontal synchronizing signal processing circui-t 3. The vertical synchronizing signal contained in the synchronizing signals outputted to the collector of the transistor TR1 is separated at the vertical synchronizing signal separator 7 as shown in FIG. 5~E) and applied to the ba~e of the transistor TR2. Con~equently the vertical synchronizing signal is outputted to the collector of the transi~tor TR2 as shown in FIG~ 5~E~) and applied to the other input terminal of the exclusive OR-gate EXOR2o Since no vertical synchronizing signal i~ inputted to -the vertical synchronizing ~ignal input terminal V and a low level signal is thereby applied to one input terminal of the exclusive OR-gate EXOR2, as ~hown in FIG. 5(G), the vertical ~ynchroni~ing signal applied to the other input terminal from the exclusive OR-gate EXOR2 is inverted as shown in FIG. 5~H) and appl.ied to the vertical synchronizing signal proaessing circuit 4.
As described above in detail, the present invention makes it possible to select automatically the synchronizing signal without changing the ~witche~ separately. Where the composite video signal and the synchronizing signal are input together at the same time, the .synchronizing signal of the composite video signal is cut off and the synchronizing signal separately input is selected.
; A
.~ .
Claims (6)
1. A synchronizing signal automatic selecting circuit having a horizontal and horizontal/vertical synchronizing signal terminal HHV which circuit is coupled to a horizontal synchronizing signal processing circuit, a vertical synchronizing signal processing circuit, and vertical synchronizing signal input terminal V comprising a synchronizing signal separating circuit for separating a synchronizing signal from color signals or a color signal, a signal inverter means for inverting the synchronizing signal output from said synchronizing signal separating circuit, a synchronizing signal detecting element for detecting the synchronizing signal when the synchronizing signal is inputted to the horizontal and horizontal/vertical synchronizing signal input terminal HHV
and grounding the output signal of said signal inverter means, a polarity detecting means for detecting the synchronizing signal polarity of said horizontal and horizontal/vertical synchronizing signal input at said terminal HHV, an exclusive OR-gate for combining the output signal of said polarity detecting means and the synchronizing signal of the horizontal and horizontal/vertical synchronizing signal input terminal, a first transistor for inverting the output signal of said exclusive OR-gate or the output signal of the signal inverted means and applying it to the horizontal synchronizing signal processing circuit, a vertical synchronizing signal separate means for separating the vertical synchronizing signal from the output signal of said first transistor, a second transistor for inverting the output signal of said vertical synchronizing signal separator means and an exclusive OR-gate for combining the output signal of said second transistor and the vertical synchronizing signal of the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
and grounding the output signal of said signal inverter means, a polarity detecting means for detecting the synchronizing signal polarity of said horizontal and horizontal/vertical synchronizing signal input at said terminal HHV, an exclusive OR-gate for combining the output signal of said polarity detecting means and the synchronizing signal of the horizontal and horizontal/vertical synchronizing signal input terminal, a first transistor for inverting the output signal of said exclusive OR-gate or the output signal of the signal inverted means and applying it to the horizontal synchronizing signal processing circuit, a vertical synchronizing signal separate means for separating the vertical synchronizing signal from the output signal of said first transistor, a second transistor for inverting the output signal of said vertical synchronizing signal separator means and an exclusive OR-gate for combining the output signal of said second transistor and the vertical synchronizing signal of the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
2. A synchronizing signal automatic selecting circuit as claimed in claim 1, wherein said vertical synchronizing signal separator means comprises a first capacitor, first and second resistors and a second capacitor and wherein the collector of said first transistor is connected to the base of said second transistor through said resistors.
3. A synchronizing signal automatic selecting circuit as claimed in claim 1, which further includes a means for providing power and wherein said synchronizing signal detecting element comprises a first capacitor, a first diode, a second diode, a second capacitor a first and second resistor and a third transistor, the collector of said third transistor connected to said second resistor, said second resistor connected to the means for providing power and the output side of the signal inverter means and wherein said horizontal and horizontal/vertical synchronizing signal input terminal is connected to the base of said third transistor through said first capacitor said second diode and said first resistor.
4. A synchronizing signal automatic selecting circuit having a horizontal and horizontal/vertical synchronizing signal terminal which circuit is coupled to a horizontal and vertical synchronizing signal processing circuit comprising a synchronizing signal separating circuit for separating a synchronizing signal from color signals or a color signal input, a signal inverter means for inverting the synchronizing signal output from said synchronizing signal separating circuit, a synchronizing signal detecting means for detecting the synchronizing signal when the synchronizing signal is inputted to the horizontal and horizontal/vertical synchronizing signal input terminal and disabling the output signal of said signal inverter means, a polarity detecting means for detecting the synchronizing signal polarity of said horizontal and horizontal/vertical synchronizing signal input, first combining means for combining the output signal of said polarity detecting means and the synchronizing signal of the horizontal and horizontal/vertical synchronizing signal input terminal, a first inverting means for inverting the output signal of said first combining means or the output signal of the signal inverter means and applying it to the horizontal synchronizing signal processing circuit, a vertical synchronizing signal separator means for separating the vertical synchronizing signal if present from the output signal of said first inverting means, a second inverting means for inverting the output signal of said vertical synchronizing signal separator, and a second combining means for combining the output signal of said second inverting means and the vertical synchronizing signal at the vertical synchronizing signal input terminal and applying it to the vertical synchronizing signal processing circuit.
5. The synchronizing signal automatic selecting circuit of claim 4, wherein said first and second combining means comprises exclusive OR-gates.
6. A synchronizing signal automatic selecting circuit for separating a synchronizing signal from one of (a) color signals or a color signal at an input terminal G, (b) a horizontal and horizontal/vertical synchronizing signal at an input terminal HHV, or (c) a vertical synchronizing signal at an input terminal V, comprising: a synchronizing signal separating circuit connected to the terminal G, signal inverter means connected to and for inverting the synchronizing signal output from said synchronizing signal separating circuit, synchronizing signal detecting means connected to the terminal HHV for detecting when a synchronizing signal is inputted and disabling the output signal of said signal inverter means, polarity detecting means conneted to and for detecting the signal polarity of signals at input terminal HHV, first logical means for logically combining the output signal of said polarity detecting means and the synchronizing signal at input terminal HHV, first inverter means for applying the output signal of said first logical means or the output signal of the signal inverter means to a horizontal synchronizing signal processing circuit, vertical synchronizing signal separator means for separating the vertical synchronizing signal if present from the output signal of said first inverter means, second inverter means connected to the output of said vertical synchronizing signal separator means, second logical means for logically combining the output signal of said second inverter means and a signal at input terminal V, and means for connecting the output of the second logical means to a vertical synchronizing signal processing circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR8367/1987 | 1987-07-30 | ||
| KR1019870008367A KR900002792B1 (en) | 1987-07-30 | 1987-07-30 | Automatic selecting circuit for synchronous signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1303227C true CA1303227C (en) | 1992-06-09 |
Family
ID=19263446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000573370A Expired - Lifetime CA1303227C (en) | 1987-07-30 | 1988-07-29 | Synchronizing signal automatic selecting circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4894719A (en) |
| JP (1) | JPS6444986A (en) |
| KR (1) | KR900002792B1 (en) |
| CA (1) | CA1303227C (en) |
| DE (1) | DE3825908A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005922U (en) * | 1988-08-02 | 1990-03-09 | 삼성전자 주식회사 | Sub-screen art (ART) processing circuit when detecting the same video signal |
| KR920006949B1 (en) * | 1989-07-21 | 1992-08-22 | 삼성전자 주식회사 | Sync-signal seperating circuit |
| US5091774A (en) * | 1990-11-30 | 1992-02-25 | Eastman Kodak Company | Method and apparatus for providing sync on R-G-B video signals |
| JPH0651729A (en) * | 1992-06-05 | 1994-02-25 | Matsushita Electric Ind Co Ltd | Automatic switching circuit for input signal path |
| JPH0651730A (en) * | 1992-06-05 | 1994-02-25 | Matsushita Electric Ind Co Ltd | Mixed synchronizing signal selecting circuit |
| US20020091850A1 (en) * | 1992-10-23 | 2002-07-11 | Cybex Corporation | System and method for remote monitoring and operation of personal computers |
| KR100202079B1 (en) * | 1996-06-21 | 1999-06-15 | 윤종용 | Detecting and separating method of multiplex syncronous signal |
| KR100391580B1 (en) * | 1997-07-12 | 2003-10-22 | 삼성전자주식회사 | Apparatus for generating vertical synchronous signal of complex signal |
| EP1116086B1 (en) * | 1998-09-22 | 2007-02-21 | Avocent Huntsville Corporation | System for accessing personal computers remotely |
| US6597352B1 (en) * | 1999-05-05 | 2003-07-22 | Nokia Corporation | Method and device for filtered sync detection |
| EP1176809A1 (en) * | 2000-07-28 | 2002-01-30 | THOMSON multimedia | Synchronisation circuit for a display device |
| US7576803B2 (en) * | 2005-04-07 | 2009-08-18 | Aten International Co., Ltd. | Processing circuit for processing horizontal and vertical synchronization signals |
| WO2009045752A2 (en) | 2007-10-01 | 2009-04-09 | 3M Innovative Properties Company | Orthodontic composition with polymeric fillers |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4677484A (en) * | 1985-05-10 | 1987-06-30 | Rca Corporation | Stabilizing arrangement for on-screen display |
| US4709267A (en) * | 1985-11-07 | 1987-11-24 | Rca Corporation | Synchronizing circuit with improved interlace arrangement |
-
1987
- 1987-07-30 KR KR1019870008367A patent/KR900002792B1/en not_active IP Right Cessation
-
1988
- 1988-07-25 US US07/223,551 patent/US4894719A/en not_active Expired - Lifetime
- 1988-07-26 JP JP63184777A patent/JPS6444986A/en active Granted
- 1988-07-29 DE DE3825908A patent/DE3825908A1/en active Granted
- 1988-07-29 CA CA000573370A patent/CA1303227C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4894719A (en) | 1990-01-16 |
| DE3825908A1 (en) | 1989-02-09 |
| JPS6444986A (en) | 1989-02-17 |
| KR900002792B1 (en) | 1990-04-30 |
| DE3825908C2 (en) | 1990-09-27 |
| KR890003206A (en) | 1989-04-13 |
| JPH0585912B2 (en) | 1993-12-09 |
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