CA1288522C - Method and apparatus for determining available memory size - Google Patents

Abstract

ABSTRACT OF THE INVENTION

The present invention provides apparatus and methods for use in a computer system, and particularly, a computer system employing memory devices having discrete capacity (i.e., 256K bit, 1M bit, etc.), such as random access memory (RAM). The present invention includes a central processing unit (CPU) coupled through a multiplexor to a plurality of contiguous banks of memory devices. In a typical embodiment, a user inserts a desired number of RAM memory vices having a particular memory capacity into the memory banks. A maximum memory address is defined for each bank as the address which would exist if the highest capacity memory devices available were utilized (e.g., 16 M bit/device). On power-up, the CPU
sequentially attempts to store the numerical address value of each possible memory address at that address location, from the highest possible contiguous address to the lowest, for the first memory bank. In the event that the CPU attempts to write to a non-existent address, the value is automatically stored at the highest real address in the system. The CPU then sequentially reads each possible memory address from the lowest to the highest. For each address read, the CPU compares the stored value with the address. The fact that the stored value equals the address indicates that the address exists. In the event the stored value does not equal the address, but rather equals the previously read address, the address does not exist and the highest available memory is set to the previous address value. The CPU repeats this procedure for the next bank of memory until the total available memory of the system is determined.
A bit value is assigned which corresponds to the available memory size of the first memory bank. This bit value is stored in a register coupled to control logic which controls the operation of the multiplexor and generates row address (RAS) and column address (CAS) signals to access the memory. Memory banks are selected by the control logic based upon the logical state of predetermined address bits outputted by the CPU which are identified by the bit value.

Description

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BACKGROUND OF THE INVENTION

1. Field ~he In~ention;
The present invention relates to apparatus and methods ~or determining the size of available memory in a cornputer system. More particularly, the present invention relates to a method for automatically determining memo~ size in a computer system in which a user may selectively remove and add rnemory devices.

2. E~r~or~
In the computing industry, it is quite common for a central processing unit (GPU~
to be coupled to memory devices, such as for example, ~ynamic random access o memory (DRAM). Tha DRAM memory (like all semi-conductor memory devices) identifies specific storage locations of data with a unique address. The more memory which is available to the CPU, the higher the addresses available to access data within the memory devices. In many computer systems, such as personal computers (PCs), a user may increase the amount of available memory by adding discrete memory devices, such as 256K bit, 1 M bit, etc. memory chips.
In those compu~sr systems which permit a user to incrsase the amount of available memory, it is necessary to identify the total available memory address space in order to permit the CPU to access all of the data lucations in th~ now expanded memory.
Historically, the memory size of the system was identified to the CPU through the use of jumper wires on the main printsd circuit board, or dual in-line package (DIP) switches located adjacent to the memory on the printed circuit board. If a user incorrectly sets the available memory size in the computer system high~r than it actually is, the CPU will overwrite data stored at these non-existant higher addresses into the highest real ~ .

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address which exists in the memory syst~m. This feature is commonly refQrred to as memory ~wrap aroundn. Accordingly, ~rrors may result, data loss, and overall system efficiency sacrificed through improper setting of the DIP switches or jumper wires on the printsd circuit board, since the CPU will operate undsr conditions of impropsr memory 5 address space allocation.
As will be describ~d more fully below, the present invention provides a m~thod and apparatus which permits the CPI 3 to determine the true memory siza available to it without the necessity of the user flipping switches, jumpers, or other hardware to set the available memory size in the system.

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The present inven~ion provides apparatus and methods for use in a computer system, and particularly, a computer system emplnyin~ merno~y devices having discrete 5 capacity (i.e., 256K bit, tM bi~, etc.), such as random access memory (RAM,. Ths pres~nt invention includes a central processing unit (CPU) coupled through a multiplexor to a plurality of contiguous banks of memory d~vices. In a typical embodiment, a user ins~rts a desired number of RAM memory devices having a particular memory capacity into the memory banks. A maximum memory address is 10 defined for each bank as the address which would exist if the highest capacity memory devices available were utilized (e.g., 16 M biVdevice~. On power-up, the CPlJ
sequentially attempts to store the numerical address value of each possible memory address at that address location, from the highest possible contiguous address to the lowest, for the first memory bank. In the event that the CPU attempts to write to a non-15 existsnt address, the valu~ is automatica11y stored at the highest real address in thesystem. The CPU then sequentially reads each possible memory address from the lowest to the highest. For each aWress read, the CPU compares the stored value with the address. The fact that ths stored value ~quals the address indicates that the address exists. in ths event the stored value does not equal the address, but rather 20 equals the previously read addr~ss, the address does not exist and the highest available memory is set to the previous address value. The CPU repeats this procedure for the next bank of memory uniil the total available memory of the system is determined.
A bit value is assigned which corresponds to the availabl~ memory si2e of the first rn~mory bank. This bit Yalue is stored in a r~gister coupled to control logic which 2~ controls the operation of the multiplexor and generates row address (RAS) and column address ~CAS) signals to access the memory. Memory banks are selected by the control logic based upon the logical state of prede~ermined address bits outputted by the CPU which are identified by the bit valu~.

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FIGURE ~ illus~rat~s a block diagram of a computer system incorporating the teachinys of the presQnt invention.
FIGURE 2 illustrates, in conceptual form, the opsration of the present invention to determine available memory si~e in a computer system.

FIGURE 3 symbolically illustrates the overall ssquance of operations of the 10 present invention as ~xecut~d by the CPU.

FIGURE 4 jS a more detailed ~low chart iliustrating the sequence of operations of the present invention described herain.

F~GURF 5 jllUStratBS a mora detailed block diagram of a system incorporating theteachings of the present inventi3n.

FIGURE 6 symbolically illustrates the operation of the multiplexor shown in FIGURE 5.
FIGURE 7 illustra~es th~ presen~ invention's us~ of FtAMSlZE bits to represent the size of available memory in bank A of the mernory in the system of FI~URE 5.

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UOTf~ll~NOM~l~ATUARE

The delailed description which follows is presented larg01y in t~rms of algorithms and symbolic representations of operations on data bits within a computer memory.
5 Thesa algorithmic descriptions and representations ara the rneans used by those skilled in the data proc~ssing arts to most effQctively conv~y the substancs of thair work to others skill~d in the art.
An algorithm is her~, and gsnerally, conceived to b~ a self consistent sequ~nce o St6pS leading to a desirad resuit. These steps are ~hose requirin~ physical 10 manipulations of physical quantiti~s. Usually, though not n~cessarily, these quantities take tha form of electrical or magn~tic signals capable of b~ing stored, transferred, combinsd, compared, and othsrwise manipulated. It proves convenient at times, principally for reasons of common usage, to refer to these si~nals as bits, values, elements, symbols, charact~rs, terms, numbers or the like. It should be kept in mind, I5 however, that all of thes~ and similar t~rms are to be associated with th~ appropriate physical quantities and are mersly convenient labels applied to these ~uantities.
Further, the manipulations perform~d are also referrad to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary, or desirable in 20 most cases, in any of the opera~ions described herein which form part of the present invention; the operations ars machine operations. Useful machines ~or per~orming the operations of the present invention include general purpose digital computers or other similar devices. In all cases, the distinction between the method operations andoperating a comput0r and the method of computation itself should be no~ed. Thc 25 present invention relates to method steps for operating the computer and processing ~lectrical or oth~r (e.g. mechanical, chemical) physical signals îo ~enerate other d~sired physical signals.
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The present invention also relates to apparatus ~or performing these operations.This apparatus may be specially constructed for the required purposes or it may comprise a general computer as sslectively activated or reconfigured by a computer program stor~d in the computar. The algorithms presented herain are not inhersntly related to any particular compu~er or other apparatus. In particular, various general purpose machines may be used with the teachings herein, or it may prove mora convenient to construct more specialized apparatus to perform th~ required method steps. The required stru~ure for a variety of these machines wili appear from the description given below.

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The present invention provides apparatus and methods for use in a computer system employing memory deYices havin~ discrete capacity, such as random access 5 msmory (RAM), to automatica11y detsrmina th~ amount of available mamory in thesystem. In tha following dascription for purposes of explanation, specific architectures, block diagram layouts, m0mory devices, memory d~vic~ capaci~ies, etc. are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to ons skilled in the art that the present invsntion may be practiced without 10 these specific details. In other instances, well known circuits and devices are shown in block diagram form in order not to obscure the present invention unnacessarily.
Referring now to Figure 1, ons possible configuration of hardware which may - utilize the teachings of the present invention is disclosed. As illustrated, a C:PU 10 is coupled to a bus 12 for communication with a variety of data proc~ssing devices,15 including a Read-Only-Memory (ROM) 14. As is well known, ROM 14 contains preprogrammed operations, data, etc. which is available for execution and access by CPU 10. CPU 10 may also utilize Random-Aecess-Memory (RAM~ situated in one or mora memory banks, such as for example Bank A and Bank B of Figura 1. Each bank of mamory is comprised oi a plurality of memory devices having a specific memory 20 capacity. For example, Bank A may be comprised of RAM chips having 256K bit or one megabit of memory, which are currently on the market. In practicc, a user inserts the memory devices into sockets on a printed circuit board comprising memory Bank A.Sirnilarly, Bank B is comprisad of a plurality of memoly devices having a particular capacity. In prior art systems, it was necessary for a user to set hardware or software 25 switches, or physical jumper wires, in the comput0r system to notify the CPU of the RAII
memory size which is available in the system. In the event a user replaced, for example, 256K memory devices with one megabit devices, the systam would b~ unable to utilize thi~ anhanced memory capacity without hardware modifications to the physical structure of the circuit. The requirement that a user set switches for modified jumpers proves 30 inconvenient, and, if done improperly, may result in data loss, irlefficiency, or possible systarn failure. As will b~ described belvw, the present invention permits a userto-add or substract memory devices from the system without the necessity of pl1ysically ., . - . ':. . ~

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reconfiguring tha hardware to notify CPU 10 of the amount of memory available.
As illustrated in Figure 1, CPU 10 is coupled through bus 12 to P~AM Bank A (18)and RAM Bank B (20). RAM Bank A is comprised of a plurality of RAM msmory devices, wherein each possibls storage location for the rnemory bank is defined by a unique address from Mo through MN. The address locations Mo through MN are contiguous and sequential. Similarly, RAM Bank B is comprised of a plurality of memory devices with possible addresses MN+1 through MMaX, and therefore, it is possible in tha syste of the present invention for the available memory addresses to nun contiguously from Mo through MMaX. However, in the even~ that maximum memory is not utili~ed RAM Bank B
may be only partially fillsd, such that the highsst addrass is l~ss than MMaX~ but greater than MN+~. Similarly, it is conc~ivable that RAM Bank A may only be partially filled and RAM Bank B completely empty. Due to the limitation that the memory addresses be contiguous, the presently preferred embodiment would not permit a partially filled Bank A and partially filled Bank B, although the methods and app~ratus of the presentinvention could, wi~h modification, accomodate such a m0mory scheme. In addition, the present invention, as illustrated in Figure 1, has the attribute, as do most computer systems, that any attempt tc store data at a address which does not physically relate to a real storage location will result in the data being stored in the highest real physical address. This "wrap around" occurs since a system error would result through anyattempt to store data at a non-existant address.
Currently, dynamic RAM rnemory devices are available commercially in certain fixed memory capacities. For example, devices are available in 256K or 1 Megabitcapacities for most personal cornputer systems on the market. It is anticipated that by the year 1990, 4Megabit RAM density devices will be available, and possibly by the yea~
1993, 1 6Megabit devices will be provided in commercial quantities. As will ba described mors fully below, the present invention's methods and operations may be optimi~ed by the fact that RAM densities are provided in increments of 256K, 1 Megabit, 4Megabit and 16Megabit, as opposed to odd densities. In addition, for purposes of tha pressntly preferr~d embodiment, the present invention is designed to accept 1 6Megabit memory davices as the largest devices which may be utilized, under the assumption that these devices will ba available in the future. HoweYer, it will b~ appreciated that although th~ presently preferred embodiment is designed to accept a maximum of 16 !
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Mbit devices, that the present invention may b~ utilized using a variety of devices of various capacities.
Referring to Figure 2, the conceptual operation of the present inv~ntion will bedisclosed. The variable ~N" is defined as the total numbar of "binary increments"
5 comprising boundary points within each memory bank. For example, if 256K memory devices ar~ used in the system, ~hen the boundary points d~fining the beginning and end of the total possible memory available fall on 256K increments. It will be appreciated by one skilled in the art, ~hat to determine whsther or not a particular memory d0vice is coupled to RAM Bank A or B of Figure 1, it is only necessary to test at 10 these binary boundary increments (i.e., 256K), and not each storage location within all o the memory devices. In Figure 2, for purposes of illustration, the binary boundary increments for Bank A are identified as Mo, M1, M3, and MN. Upon power up, CPU 10 attempts to store, beginning at the highest possible address increment for the Bank (MN) through to ths lowest address increment (Mo) the address of each binary increment for 15 storage at that location. In other words, CPU 10 attempts to sequentially store the address of the particular memory location at that memory location, and begins from the highest address to tha lowest incremental address. It will be apparent to one skilled in th~ art, that although the present invention has optimized and increased the efficiency of the system through the use of testing only at ths binary increments (Mo, M1, etc.), that 20 the methods, apparatus and operations of the present invention are equally applicable to those computar systems in which each storage location within the memory, or other predefined increments, are used in place of increments Mo through MN as disclosed.
With rsference to Figures 2 and 3, once CPU 10 has sequentially stored the addresses of the memory boundary points, the CPU then begins to sequentially read the 25 addresses at the increment boundary points from low (Mo) to high address ~MN 3. At each address read, CPU 10 compares th~ contents of the storage location at the address with the address it has read. If the stored contents are equivalent to the addresc read, it will be appreciated that this indicates that tha memory address cDnstitutes a real physical storage location within thc computer system. CPU 10 continues to sequentially 30 rcad and compar~ the contents of th~ stored values for each binary increment (N) and compares each valu~ to ths rsspectiYa address. In the ~v~nt that the stored value of ~ach binary increment ~quals tha address throughout the mamory bank (for example ~' :

3~3~jZ~.' Bank A) this indicat~s that the msmory is fill~d to its maximum capacity and that continguous available memory locations exist from address Mo through address MN.In the event that a stored value does not equal the address value at a particular binary incr~ment, it will bc appreciated that the RAM memory is less than the maximum capacity, and in fact, the highest real address is Isqual to the memory address at the previous binary incr~ment. It will be recalled, that due to the memory "wrap around"
foatur~ of th~ present invsntion (a featura pressrlt in virtually all comput~r systems) any attempt to write data to a non-axistent address r~sults in the data being stored at the last (highest) raal physical address location of the system. For axample, assume that the contents of M2 (see Figure 2) are compared with the address and are found to be equivalent. If CPU 10 sequentially increments to memory address location M3 and detsrmines that the contents of M3 are equal to the contents of M2, they are not equal to the address of M3. Due to memory wrap around, an attempt to read a non-existent address (such as M3) results in the retrieval of data at the last highest real address in existenoe (M2). Since CPU 10 had written the address locations as data, for eachaddress location from the highest address to the lowest, address location M2 would sontain the value of the address M2, as opposed to the value of M3. The reading of a non-existent address such as M3, results in retrieval of th~ value stored at M2. Since memory devices are commercially manufactured having finite known capacities (i.e., 256K bit, 1 M bit, etc.) CPU 10 may then set the maximum contiguous real address at M2 at the last real binary increment d~tected.
Once the memory capacity of Bank A is determined using the above-described m~thod, CPU 10 foliows a similar procedure with respect to determining the amount of memory in RAM Bank B. In the case of RAM Bank B, ~he lowest address value is MN+1, with tha highest address being MMaX~ with a total number of binary incr~ments (N) for th~ bank.
Figure 4 illustrates, in a more detailed fashion, the se4uenca of operations exacuted by CPU 10 in determining the size of memory banks coupled to bus 12. Asillustrated, upon power up of the system CPU 10 determines th~ siz~ of th~ available mamory in th~ first bank ~Bank A), and sets a variabl~ (N) as the to~al number of binary increments in the ~irst bank (X). As previously describsd, allhough the present invention wiil function by sequentiaily writing and reading each possible address in a memory ` 3 f ~ ~ ~ Z ~. d disposed in one of the memory banks illustrated in Fi~ur~ 1, it has baen found that by using discrete binary increments (i.e., 256K) the method of the presant invention performs faster and more e~lioien~ly. Slnce memory davlces are not commercially marketed in odd sizes (for oxample 300K memory devices), it is known that a user will fill memory banks utilized by the present invention in tinite, discrete and known increments.
Once the total number of binary increments is set for the bank as variable N, CPU
10 writes the value of each address, commencinS~ from the higher increment to the lowest increment, of MN/2A-1. CPU 10 then determines if each increment has been addressed and stored and, if not, continues its writing operation to store the value of oach increment address, sequentially, from highest to lowest. Oncc the writing operation has been completed, CPU 10 ~hen sequentially reads the address of eachincrsment, from the lowest increment (i.e.i MN+1 for Bank B) to the highest increment (i~e., MMaX). For each increment address read by CPll 10, the CPU determines whether or not the address value is equal to stored data at that address. As previously discussed, if an address is real and physically present in the system, the stored value at the address will equal the address value. In the event that an address increment does not physically exist in the system, the increment address will not equal the stored addrass, and the stored address will (as a result of ~wrap aroundn) be the va,ue of the highest physical address actually found within ~he memory bank. CPIJ 10 thereby determines the highest memory value physically coupled to the memory bank, and then determines if more memory banks are coupled to bus 12 of the system.
It will be appreciated by one skilled in the art, that although a memory Bank A
and a memory Bank B are shown in Figure 1, that numerous additional memory banksmay be coupled to bus 12 using the teachings of the present invention. As illustrated in Figure 4, the operations illustrated are repeated for subsequent memory banks until the total size of the available msmory coupled to the systam illustrated in Figure 1 is determined.
Raferrinç~ now to Figure 5, a more detailed discussion of the operation of the present invention using the methods discussed abovs will be described. As illustrated, a CPlJ 3û is coupled to a multiplexor 32 and a register 3~. Multiplexor 32 is in turn coupled to a bus 36 for communication with a RAM memory situated in one or more memory banks, such as for example, memory Bank A (40) and Bank B (42). Memory ~ ~s~ .,2.PJ' Bank A (40) and Bank B (42) correspond to mamory Banks A ancl B in Fi~ure 1. As previously describ~d, these memory banks are comprisad of RAM chips having discrete memory devices of specific size (e.g. 256K bit or 1 Me~abit~. As in the case of the systcm illustrated in Fi~ure 1, the computer system of Figure 5 dalineates each possible 5 storage location for the memory bank by a unique address which, in the case of Bank A, runs from Mo lhrough MN. Similarly, RAM Bank B is comprised of a plurality of mernory dovices with possibl~ address MN+1 through MMAX. For pu,poses of th~ discussion relative to Figure 5, ~he reader is ref~rred to the description of Figures 1-4, above, with respect to the sequence of operations which the CPU 30 (or in the case of Figure 1, CPU
10 10) execute in order to determine th~ range of available memory addresses in memory Banks A and B.
Initially, CPU 30 executes th~ sequencs of operations illustrated in Figure 4 and previously described with respect to Figure 1, to determine the range of available m~mory in the computer system. In the presently preferrsd embodiment, CPU 30 15 comprises a 32 bit processor which accesses RAM memory locations based on a 32 bit address (~Ao ... A31). As is common, the address of a memory location is comprised of the row ~ddress and column address of tha particular storage location in the RAMmemory which is to be accessed. Multiplexor 32 first applies the row address to the RAM which is then followed by a column address in order to complete the memo~
~o access cycle ~see Figure 6). Multiplexor 32 is controlled by control logic 45, and is coupled to multiplexor 32 by line 46.
Once CPU has executed a sequence oi op~rations illustrated in Figure 4, above, a two-bit RAMSIZE variable is set to a binary n~mber between 0 and 4. As illustrated in Figure 7, the value of th~ RAMSIZE bits corresponds to the memory capacity of Bank 25 A (possibl~ addresses Mo through MN) as determined by CPU 30 through ex0cution of th0 ssquence of operations illustrat~d in Figur~ 4. The CPU 30 stores th0 RAMSIZE
value in register 35 which, as illustrated, is coupled to control logic 45. Control logic 4 includ0s a memory having a look-up tablo (not shown) which maps the RAMSIZE
number to a particular address bit provid~d in th~ address (Ao through A31 ) by CPU 30 30 for accessing a RAM location. In the prasently preferred ernbodiment, address bit number 20 (A20) corresponds to a 1 Me~abyts memo,sy in Bank A. As illustrated inFiguro 7, a 1 Megabit m0mory size is danot0d by a P~AMSIZE value of 0. Similarly9 a ~ ~ f~ 87 5 2 ~d RAMSIZE value of 01 refers to a four me~abit0 RAM Bank A mamory size, and corrosponds to address bit A22. As illustrated in Figure 7, in address bit 24 corresponds to a 15 Megabyts memory, and address bit 26 corresponds to a 64 Megabyte mamory si~e.
In operation, the logical state of the address bit identified by the RAMSIZE
variable determines which memory bank is selectled by control logic 45. For exam~!e, if the RAMSIZE variable is equal to 4, then control 13gic 4~ checks the value of address bit A22. In the present smbodiment, if the value of A22 is a logical 0 then Bank A is selected, whereas if the value of A22 is a logical 1 then Bank B is selected by control logic 4~. Control logic 45 then issues appropriate row address strobe (RAS) and column address strobe (CAS) signals, as is well known, to access a particular memory location in the bank of RAM identified by the logical state of ~he address bit. It wiii be appreciated by one skilled in the art that if the RAMSIZE variable is equal to 1, then in accordance with the above discussion, control lo~ic 4~ will check the Yalue of address bit A22 from CPU 30. Control logic 45 then selects the appropriate memory bank bassd on the logical state of address bit A22.
Accordingly, the present invention, as described above, provides apparafus and msthods for use by computer system to determine and allocate the size of the available memory currently in the system. The present invention permits a user to insert or remove memory devices from memory banks without the need of setting switches, providing jumper wires or the like to reconfigure the memory system size. Although the present invention has been described with reference to Figures 1-7, and with 6mphasis on a computer system employing two banks of memory devices, it should be understood that the figures are for illustration only and should not be taken as limitations upon the invention. It is contemplated that many changes and modifications may be rnade, by one of ordinary skill in the art7 to the materials and arrangements of the elements in the Invention without depar~inçl from the spirit and scope of the invention as disclosed abova.
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Claims (23)

1. In a computer system having a central processing unit (CPU) coupled to at least one memory bank (A) having a plurality of possible contiguous addresses (#MO-MN) for storing data, said memory bank configured to receive a plurality of memory devices, each of said devices having a plurality of storage locations identified by one of said possible contiguous addresses, a method for determining the range of real memory addresses which exist in said memory bank, comprising the steps of:
said CPU sequencially storing the addresses of each of said possible storage locations at said respective addresses, from the highest possible address to the lowest possible address, said CPU storing the value of an address which does not physically exist at the highest real address of said memory bank;
said CPU sequentially reading the address of each of said possible storage locations from the lowest possible address to the highest possible address, and comparing the data stored at each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address being the highest address in which said stored value is equivalent to said address value;
whereby the highest real address available in said memory bank is determined by said CPU.

2. In a computer system having a central processing unit (CPU) coupled to a memory bank A having a plurality of possible contiguous addresses (#MO-MN) and a memory bank B having a plurality of possible contiguous addresses (#MN+1-MMAX) for storing data, said memory banks configured to receive a plurality of memory devices, each of said devices having a plurality of storage locations identified by one of said possible contiguous addresses, said CPU accessing data by providing a multi-bit address of a desired storage location, a method for determining the range of real memory addresses which exist in said memory banks and accessing said desired storage location, comprising the steps of:
dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses;
said CPU sequentially storing the addresses of each of said N increments at said respective increment addresses, from the highest possible increment address to the lowest possible increment address, said CPU storing the value of an address which does not physically exist in a memory bank at the highest real increment address of said respective memory bank;
said CPU, for each of said memory banks, sequentially reading the address of each of said possible increment addresses from the lowest possible increment address to the highest possible increment address, and comparing the data stored in each of said possible increment addresses with the respective address, such that said increment address is considered to be real if said address and said stored data are equivalent, said highest real increment address being the highest increment address for each of said memory banks in which said stored value is equivalent to said address value;
said CPU providing a bit value corresponding to the total memory size in Bank A
to control logic coupled between said CPU and said memory banks; said control logic enabling one of said memory banks based on the logical state of a predefined row of said address bits provided by said CPU, said predefined address bit identified by said bit value;
said control logic providing control signals to said storage location identified by said multi-bit address provided by said CPU, thereby accessing said desired storage location in said enabled memory bank.

3. The method as defined by claim 2, further including a register coupled between said CPU and said control logic, such that said bit value is stored in said register prior to being provided to said control logic.

4. The method as defined by claim 3, wherein said multi-bit address includes row addrss bits and column address bits identifying said desired storage location.

5. The method as defined by claim 4, further including a multiplexor coupled between said CPU and said memory banks, said multiplexor being coupled to said control logic.

6. The method as defined by claim 5, wherein said multiplexor alternately couples said row address bits and said column address bits to said memory banks.

7. The method as defined by claim 6, wherein said control logic enables one of said memory banks by coupling a row address strobe (RAS) signal to said selected bank.

8. The method as defined by claim 7, wherein said multi-bit address comprises 32 bits numbered A0 through A31.

9. The method as defined by claim 8, wherein said one predefined address bit is address bit number A20 if the memory size of Bank A is 1 megabyte.

10. The method as defined by claim 8, wherein said one predefined address bit is address bit number A22 if the memory size of Bank A is 4 megabytes.

11. The method as defined by claim 8, wherein said one predefined address bit is address bit number A24 if the memory size of Bank A is 16 megabytes.

12. The method as defined by claim 8, wherein said one predefined address bit is address bit number A26 if the memory size of Bank A is 64 megabytes.

13. In a computer system having a central processing unit (CPU) coupled to a memory bank A having a plurality of possible continguous addresses (MO-MN) and a memory Bank B having a plurality of possible contiguous addresses (MN+1-MMAX) for storing data, said memory banks configured to receive of a plurality of memory devices, each of said devices having a plurality of storage locations identified by one of said possible contiguous addresses said CPU accessing data by providing a multi-bit address of a desired storage location, an apparatus for determining the range of real memory addresses which exist in said memory banks, and accessing said desired storage location,comprising:
storing means coupled to said CPU for dividing said memory banks into N binary increments separated by a predetermined number of contiguous possible addresses, said memory means sequentially storing the addresses of each of said N increments at said respective addresses, from the highest possible address to the lowest possible address, said CPU storing the value of an address which does not physically exist in a memory bank at the highest real address of said respective memory bank;
reading means coupled to said CPU for reading the address of each of said possible storage locations for each of said memory banks, from the lowest possible address to the highest possible address, and comparing the data stored in each of said possible addresses with the respective address, such that said address is considered to be real if said address and said stored data are equivalent, said highest real address for each of said memory banks being the highest address in which said stored value is equivalent to said address value;
control logic means coupled between said CPU and said memory banks for receiving and storing a bit value corresponding to the total memory size in memory Bank A, said control logic means enabling one of said memory banks based on the logical state of a predefined one of said address bits provided by said CPU, said predefined address bit identified by said bit value;
said control logic means providing control signals to said memory bank in which storage location is disposed, thereby accessing said desired storage location in said enabled memory bank.

14. The apparatus as defined by claim 13, further including a register coupled between said CPU and said control logic, such that said bit value is stored in said register prior to being provided to said control logic.

15. The apparatus as defined by claim 14, wherein said multi-bit address includes row addrss bits and column address bits identifying said desired storage location.

16. The apparatus as defined by claim 15, further including a multiplexor coupled between said CPU and said memory banks, said multiplexor being coupled to said control logic.

17. The apparatus as defined by claim 16, wherein said multiplexor alternately couples said row address bits and said column address bits to said memory banks.

18. The apparatus as defined by claim 17, wherein said control logic enables one of said memory banks by coupling a row address strobe (RAS) signal to said selected bank.

19. The apparatus as defined by claim 18, wherein said multi-bit address comprises 32 bits numbered A0 through A31.

20. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A20 if the memory size of Bank A is 1 megabyte.

21. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A22 if the memory size of Bank A is 4 megabytes.

22. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A24 if the memory size of Bank A is 16 megabytes.

23. The apparatus as defined by claim 18, wherein said one predefined address bit is address bit number A26 if the memory size of Bank A is 64 megabytes.