CA1237819A - Multilayer circuit arrangement and method of manufacturing such multilayer circuit arrangement and its electric connections - Google Patents
Multilayer circuit arrangement and method of manufacturing such multilayer circuit arrangement and its electric connectionsInfo
- Publication number
- CA1237819A CA1237819A CA000496297A CA496297A CA1237819A CA 1237819 A CA1237819 A CA 1237819A CA 000496297 A CA000496297 A CA 000496297A CA 496297 A CA496297 A CA 496297A CA 1237819 A CA1237819 A CA 1237819A
- Authority
- CA
- Canada
- Prior art keywords
- support element
- metal layer
- holes
- metallized
- plane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Attorney's Docket No. 7605 CAN
INVENTOR: JOSEF ELSENER
INVENTION: MULTILAYER CIRCUIT ARRANGEMENT AND METHOD OF
MANUFACTURING SUCH MULTILAYER CIRCUIT
ARRANGEMENT AND ITS ELECTRIC CONNECTIONS
ABSTRACT OF THE DISCLOSURE
A multisubstrate or multilayer circuit arrangement and a method of manufacturing such multisubstrate circuit arrangement and its electrical connections is proposed. The arrangement of the multisubstrate circuit is essentially a three layer construction comprising a first, double-sided metallized support element, a second, one-sided metallized support element as well as an insulating material arranged between the two. Conducting tracks are etched from the metal layer of an intermediate plane between the first and second support elements and then the above mentioned elements are bonded into a single unit. A first set of holes is bored at pre-programmed locations using a first hole schedule and starting from a component plane. The unit is inverted and a second set of holes is bored at pre-programmed locations using a second, mirrored hole schedule and starting from a lower plane. After the metallization of all holes, the contact and conducting surfaces or pads on the component plane and the corresponding conducting tracks on the lower plane are etched.
WWK/04;02/se:SENC6
INVENTOR: JOSEF ELSENER
INVENTION: MULTILAYER CIRCUIT ARRANGEMENT AND METHOD OF
MANUFACTURING SUCH MULTILAYER CIRCUIT
ARRANGEMENT AND ITS ELECTRIC CONNECTIONS
ABSTRACT OF THE DISCLOSURE
A multisubstrate or multilayer circuit arrangement and a method of manufacturing such multisubstrate circuit arrangement and its electrical connections is proposed. The arrangement of the multisubstrate circuit is essentially a three layer construction comprising a first, double-sided metallized support element, a second, one-sided metallized support element as well as an insulating material arranged between the two. Conducting tracks are etched from the metal layer of an intermediate plane between the first and second support elements and then the above mentioned elements are bonded into a single unit. A first set of holes is bored at pre-programmed locations using a first hole schedule and starting from a component plane. The unit is inverted and a second set of holes is bored at pre-programmed locations using a second, mirrored hole schedule and starting from a lower plane. After the metallization of all holes, the contact and conducting surfaces or pads on the component plane and the corresponding conducting tracks on the lower plane are etched.
WWK/04;02/se:SENC6
Description
~3~19 BACKGROUND OF THE INVENTION
The present invention broadly relates to circuit boards and, more specifically, pertains to a new and improved arrangement of and method for manufacturing multisubstrate or multilayer circuit boards.
Generally speaking, the circuit board arrangement of the present invention comprises a multiple substrate circuit arrangement between individual metal layers applied to mutually insulated and mutually pressure-bonded support elements and separable into contact surfaces, conducting traces or both.
In other words, the multilayer circuit board of the present invention comprises a substantially planar first support element, a substantially planar second support element and a substantially planar insulative element for bonding the first support element and the second support element together.
The first support element has a first side remote from the second support element and a second side confronting the second support element and bonded to the .insulative element. The second support element has a first side remote from the first support element and a second side confronting the first support element and bonded to the insulative element. The first side of the first support element is provided with a metal layer and the second side of the first support element is provided with a 3k 1~37~ 1~
metal layer. The first side of the second support element is provided with a metal layer.
The method of the present invention relates to for fabricating a multiple substrate circuit arrangement and electrical intexconnections thereof.
A circuit arrangement having a plurality of superimposed printed circuit boards as well as a process for interconnecting the individual circuit boards of the plurality are known from German Patent No. 2,103,767. The circuit boards are separated from each other by an insulating layer and the appropriate holes can go through the whole layered block or, alternatively, only through individual layers. Solder-coated or pre-tinned spiral springs are inserted in these holes. This multilayered arrangement employs only such electrical interconnection between the separate circuit boards as can be achieved by merely heating the solder-coating or tinning on the springs.
SUMMARY OF THE _NVENTION
Therefore, with the foregoing in mind, it is a primary object of the present invention to provide a new and improved arrangement of a multilayer circuit board of the previously-mentioned type and a method for fabricating such a ~23'7~
circuit board and its electrical interconnections which do not exhibit the aforementioned drawbacks and shortcomings of the prior art constructions.
Another and more specific object of the present invention is to provide a multisubstrate or multilayer, i.e.
multiple-plane, circuit arrangement as well as a method of manufacturing such a multisubstrate circuit arrangement and the electrical connections thereof in which a reduction of the number of substrate carrier elements and simultaneously a smaller construction unit is realized while retaining a relatively high connection density (packing density) in a minimum amount of space.
Yet a further significant object of the present invention aims at providing a new and improved construction of a multisubstrate circuit arrangement of the character described which is relatively simple in construction and design, extremely economical to manufacture, highly reliable in operation, and not readily subject to breakdown or malfunction.
Now in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the multiple substrate circuit arrangement of the present invention is manifested by the features that the multiple substrate circuit arrangement is 1~3'7~1~
fabricated as a pressure-bonded, three-layer multiple substrate. This pressure-~onded, three-layer multiple substrate comprises a component plane, an intermediate plane and a ~ottom or lower plane. Tn~s multiple su~strate circuit arrangement compr~ses a douale-sidedly metallized support element defining a f~rst support element of the mutually insulated and mutually pressure-~onded support elements. The multiple substrate circu~t arrangement compr~ses a single-sidedly metallized support element defines a second support element of the mutually ~nsulated and mutually pressure-~onded support elements, and th.e multiple suDstrate circuit arrange-ment st~ll further comp~ises an ~nsulat~ve element arranged ~etween the first support element and the second support element. The component plane has an exposed metal layer defining a ~irst ~etal l~yer of th.e individual metal layers, while th.e ~ottom or lo~er plane has an exposed metal layer de~ning a second met~l layer o~ the individual metal layers.
A t~rd ~etal layer o~ th.e ind~v~dual metal layers de~ines a sandwic~.ed metal layex. T~e ~ t metal layer and the second metal layer are electr~cally connected to th.e ~ni~d metal laye~ ~y metallized Dl~nd holes, and the flrst metal layer and the second metal layer are mutu~lly electrically interconnected ~y metallized through.holes.
In ot~er wo~ds, the multilayer circuit ~oard of the present inVenti~n ~s man~fested ~y the features that the first - h ~
1~3~1S 1'~
support element is provided with blind holes extending from the first side of the first support element through the metal layer of the second side of the first support element, the blind holes of the first support element are metallized for electrically interconnecting the metal layer of the first side of the first support element with the metal layer of the second side of the first support element, the second support element is provided with blind holes extending from the first side of the second support element through the insulative element and through the metal layer of the second side of the first support element, the blind holes of the second support element are metallized for electrically interconnecting the metal layer of the second side of the first support element with the metal layer of the first side of the second support element, predetermined ones of the blind holes of the first support element axial:Ly coinciding with predetermined ones of the blind holes of the .second support element such that through holes are formed extending ~rom the first side of the first support element to the first side of the second support element and the through holes are metallized for electrically interconnecting the metal layer of the first s:ide of the first support element with the metal layer of the first side of the second support element.
The method of the present invention is manifested by the features that it comprises the steps of etching a metal ~L~3 r ~ ~
layer of an intermedia~e plane to form conductor traces, pressing together a first support element, an insulative element and a second support element for bonding the first support element to the second support element to form a construction unit, subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane and the conductor traces of the intermediate plane at programmatically predetermined locations, inverting the construction unit, subsequently boring a second plurality of holes in accordance with a second mirror-image hole schedule and extending between a bottom plane and associated conductor traces of the intermediate plane at programmatically predetermined locations, metallizing all holes of the first plurality of holes and the second plurality of holes for electrically interconnecting the component plane, the intermediate plane and the bottom plane, fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by etching and fabricating correspondingly arranged conductor traces in the bottom plane by etching.
In other words, the method of the present invention is manifested by the features that it comprises the steps of photo-etching a first metal layer provided on a second side of a substantially planar first support element to form a desired one of conductor traces extending substantially parallel to a predetermined direction, conductor traces extending substantially perpendicular to the predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to the predetermined direction, pressure-bonding the first support element to a substantially planar second support element by the intermediary of a substantially planar insulative bonding element to form a multilayer circuit board blank, boring a plurality of blind holes extending from a second metal layer provided on an exposed first side of the second support element through the insulative bonding element and through desired ones of the conductor traces formed on the second side of the first support element at desired locations, inverting the multilayer circuit board blank, boring a plurality of holes extending from a third metal layer provided on an exposed first side of the first support element through desired ones of the conductor traces formed on the second side of the first support element at desired locations such that desired holes of the plurality of holes axially coincide with desired holes of the plurality of blind holes to form through holes extendi.ng from the first metal layer to the third metal l~yer and such that remaining holes of the plurality of holes form blind holes, metallizing all holes of the blind holes and the through holes for electrically interconnecting the first metal layer with desired ones of the conductor traces formed on the second side of the first support element for electrically interconnecting the ~Z;~'781~
third metal layer with desired ones of the conductor traces formed on the second side of the first support element and for electrically directly interconnecting the second metal layer with the third metal layer independently of the conductor traces formed on the second side of the first support element, photo-etching the second metal layer to form a desired configuration of contact pads and power conducting traces, and photo-etching the third metal layer to form conductor traces extending substantially parallel to the predetermined direction.
BRIEF DESCRIPTION OF THE DRAWINGS
. _ The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein throughout the various figures of the drawings there have been generally used the same reference characters to denote the same or analogous components and wherein:
Figure 1 schematically shows a multisubstrate circuit arrangement as an embodiment of the invention in cross-section and on an enlarged scale; and :1~3'7~:~9 Figure 2 schematically shows the circuit arrangement of Figure 1 in exploded perspective view.
DETAILE~ DESCRIPTION OF THE PREFERRED EMBODIMENTS
Describing now the drawings, it is to be understood that to simplify the showing thereof only enough of the structure of the multisubstrate circuit arrangement has been illustrated therein as is needed to enable one skilled in the art to readily understand the underlying principles and concepts of this invention. Turning now specifically to Figure 1 of the drawings, the structure illustrated therein by way of example and not limitation will be seen to comprise a three-layer superimposed or laminated multisubstrate circuit arrangement which essentially comprises a first substrate 10 serving as a first support sheet or laminate as well as a second substrate 20 serving as a second support sheet or laminate. A pre-impregnated insulative sheet material 30, such as for instance the commercially available product Prepreg, is employed as an adhesive or bonding agent and as an insulator between the first and second substrates 10 and ~0. The first substrate 10 is coated on first and second sides thereof with a not particularly referenced suitable metal layer which is etched into separate, mutually spaced, conducting tracks or traces using a known photolithographic process of semiconductor technology, i.e. photo-etching. The second substrate 20 is ~f~ 3~
coated on a first side only thereof with a not particularly referenced suita~le metal layer whic~ is also, as described a~ove, suh-divtded tnto indiv~dual contact surfaces or pads or into conducting tracks ~r traces ay etch~ng.
The circu~t arrangemen~ tS presented ~n exploded perspective v~e~ in Figure 2 and ~ithout t~e sheet of insulative material 3Q. T~e second su~strate 2Q having mult~ple contact surfaces ox pads 22, 23, 24, 25, 26, 26' and 27 etc~ed ~rom the met~l layer as ~ell as a conduct~ng track or trace 28 used as an electr~cal current supply track or rail and electrically connected to the contact surface 26 ~y a path or trace 26', can ~e recogn~zed, Furthermore, the first su~strate 10, ~h~cH.~s provided wit~ conducting tracks ar traces 31, 32, 33, 34, 35, 36 and 37 formed from a metal layer on the second side o~ the ~irst su~strate lQ facing t~e second su~strate 2Q and which ~u~th.er i`5 pxov~ded with con-ducting trac~s or txaces 13, 14, 15, 16, 17 and 18 etc~ed ~om th.e ~etal layer on t~e ~rst s~.de c~ tn.e ~irst su~trate lQ. ~ci~ng aw~y~rom t~e second suPstrate 2U, can ~e ~ecogn~zed. T~.e canducting t~ac~s~ ~r tr~c~s 31 to 37 P~ovided on tH.e second s~de ~ac~g t~e second subs~t~ate 2a can ~e o~ented suhstant~lly ~n e~,ther of two mutually orthDgonal d~rections indic~ted ~y~the dou~le-h.eaded ar~ows X
and X in Figure 2 or in ~oth.of these di~ections, wh~le the conducting tracks or traces 13 to 18 arranged on the under or ~ ~2 ~
1~3~7~ 1~
first side of the first substrate 10 may be oriented substantially in only the direction indicated by the arrow Y.
The conducting tracks or traces 13 to 18 as well as 31 to 37 provided on the first substrate 10, as well as the contact surfaces or pads 22 to 27 and the current supply track or rail 28 provided on the second substrate 20, are etched from the actual metal layers according to a program (CAD). The metal layers can consist of, for example, a bonded copper foil or of a vapor-deposited or sputtered copper layer, or the like.
The electrical contacts in the circuit arrangement described above must not only be established between the contact surfaces or pads 22 to 27 on a component plane indicated by the arrow A and the conducting tracks or traces 31 to 37 in an intermediate plane indicated by the arrow B and oriented in the X or Y direction, or both, but also, as illustrated in Figure 1 and Figure 2, must be established between the contact surfaces or pads 22 to 27 of the component plane A, the conducting tracks or traces 31 to 37 of the intermediate plane B and the conducting tracks or traces 13 to 18 of a lower or bottom plane of the first substrate 10 indicated by the arrow C and oriented in the Y direction. The contact surfaces or pads 22 io 27, the contact tracks or traces 31 to 37 as well as the sontact tracks ox traces 13 to 18 can hereby be displaced in the X or Y direction, or both, in relation to each other. Essentially, this is achieved ~y a processing step wherein a first set of holes 1', 3", 4', 6' and 7' is ~ored in thedirections indicated ~y the arrows 1, 3, 4, 6 and 7. The holes are bored, for instance using a first hole schedule ~CAD-data~, at pre-programmed locations ~here an electrical connect~on ~etween the metal layer o~ the component plane A and the corresponding conducting tracks or traces of the intermediate plane B are to ~e esta~lished. The holes are bored after t~.e conducting tracks ~r traces in t~e intermediate plane B ha~e ~een etc~ed and the separate elements 10, 20 and 3Q have ~een ~onded into a 6ingle unit.
The uni.t ~.s inyerted ~n a ~econd processing step and positioned ~,n suc~ a manner tnat, at pre-programmed locations ~nere an electr~c~l connect~on ~etween the metal layer o~ the lo~er or ~ottom plane ~ and the corresponding conducting trac~s or traces of the intermed~ate plane B are to ~e esta~lis~.ed, a second set o~ holes 2~, 3", 5~ and 6" is ~ored uslng a second ~o~ed ~Ple schedule ~CAD-datal ~n the directions ~ndicated ~y t~e ar~ow~ 2, 3~, 5~ and 6~. T~e holes 1~, 2~, 4~, 5~ and 7 t are sh~ s~ ~lin~ noles i`n ~gure 1.
The hole$ 3" and 6'~, due to t~e do~ s~ded boring process, ~ecome th.rough holes. T~e ~oles 1~, 2~, 3~, 4~, 5l, 6" and 7' are metallized ~,n a thi`rd process~ng step wherein electrical interconnection o~ th.e met~ ers of the separate planes A, B
a,nd C ~s ach.~eved. The contact sur~aces or pads 22 to 27, as 8.~
well as the current supply track or rail 28 on the component plane A and the conducting tracks or traces 13 to 18 oriented in the Y direction on *he lower or bottom plane C, are now produced by etching.
The present invention broadly relates to circuit boards and, more specifically, pertains to a new and improved arrangement of and method for manufacturing multisubstrate or multilayer circuit boards.
Generally speaking, the circuit board arrangement of the present invention comprises a multiple substrate circuit arrangement between individual metal layers applied to mutually insulated and mutually pressure-bonded support elements and separable into contact surfaces, conducting traces or both.
In other words, the multilayer circuit board of the present invention comprises a substantially planar first support element, a substantially planar second support element and a substantially planar insulative element for bonding the first support element and the second support element together.
The first support element has a first side remote from the second support element and a second side confronting the second support element and bonded to the .insulative element. The second support element has a first side remote from the first support element and a second side confronting the first support element and bonded to the insulative element. The first side of the first support element is provided with a metal layer and the second side of the first support element is provided with a 3k 1~37~ 1~
metal layer. The first side of the second support element is provided with a metal layer.
The method of the present invention relates to for fabricating a multiple substrate circuit arrangement and electrical intexconnections thereof.
A circuit arrangement having a plurality of superimposed printed circuit boards as well as a process for interconnecting the individual circuit boards of the plurality are known from German Patent No. 2,103,767. The circuit boards are separated from each other by an insulating layer and the appropriate holes can go through the whole layered block or, alternatively, only through individual layers. Solder-coated or pre-tinned spiral springs are inserted in these holes. This multilayered arrangement employs only such electrical interconnection between the separate circuit boards as can be achieved by merely heating the solder-coating or tinning on the springs.
SUMMARY OF THE _NVENTION
Therefore, with the foregoing in mind, it is a primary object of the present invention to provide a new and improved arrangement of a multilayer circuit board of the previously-mentioned type and a method for fabricating such a ~23'7~
circuit board and its electrical interconnections which do not exhibit the aforementioned drawbacks and shortcomings of the prior art constructions.
Another and more specific object of the present invention is to provide a multisubstrate or multilayer, i.e.
multiple-plane, circuit arrangement as well as a method of manufacturing such a multisubstrate circuit arrangement and the electrical connections thereof in which a reduction of the number of substrate carrier elements and simultaneously a smaller construction unit is realized while retaining a relatively high connection density (packing density) in a minimum amount of space.
Yet a further significant object of the present invention aims at providing a new and improved construction of a multisubstrate circuit arrangement of the character described which is relatively simple in construction and design, extremely economical to manufacture, highly reliable in operation, and not readily subject to breakdown or malfunction.
Now in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the multiple substrate circuit arrangement of the present invention is manifested by the features that the multiple substrate circuit arrangement is 1~3'7~1~
fabricated as a pressure-bonded, three-layer multiple substrate. This pressure-~onded, three-layer multiple substrate comprises a component plane, an intermediate plane and a ~ottom or lower plane. Tn~s multiple su~strate circuit arrangement compr~ses a douale-sidedly metallized support element defining a f~rst support element of the mutually insulated and mutually pressure-~onded support elements. The multiple substrate circu~t arrangement compr~ses a single-sidedly metallized support element defines a second support element of the mutually ~nsulated and mutually pressure-~onded support elements, and th.e multiple suDstrate circuit arrange-ment st~ll further comp~ises an ~nsulat~ve element arranged ~etween the first support element and the second support element. The component plane has an exposed metal layer defining a ~irst ~etal l~yer of th.e individual metal layers, while th.e ~ottom or lo~er plane has an exposed metal layer de~ning a second met~l layer o~ the individual metal layers.
A t~rd ~etal layer o~ th.e ind~v~dual metal layers de~ines a sandwic~.ed metal layex. T~e ~ t metal layer and the second metal layer are electr~cally connected to th.e ~ni~d metal laye~ ~y metallized Dl~nd holes, and the flrst metal layer and the second metal layer are mutu~lly electrically interconnected ~y metallized through.holes.
In ot~er wo~ds, the multilayer circuit ~oard of the present inVenti~n ~s man~fested ~y the features that the first - h ~
1~3~1S 1'~
support element is provided with blind holes extending from the first side of the first support element through the metal layer of the second side of the first support element, the blind holes of the first support element are metallized for electrically interconnecting the metal layer of the first side of the first support element with the metal layer of the second side of the first support element, the second support element is provided with blind holes extending from the first side of the second support element through the insulative element and through the metal layer of the second side of the first support element, the blind holes of the second support element are metallized for electrically interconnecting the metal layer of the second side of the first support element with the metal layer of the first side of the second support element, predetermined ones of the blind holes of the first support element axial:Ly coinciding with predetermined ones of the blind holes of the .second support element such that through holes are formed extending ~rom the first side of the first support element to the first side of the second support element and the through holes are metallized for electrically interconnecting the metal layer of the first s:ide of the first support element with the metal layer of the first side of the second support element.
The method of the present invention is manifested by the features that it comprises the steps of etching a metal ~L~3 r ~ ~
layer of an intermedia~e plane to form conductor traces, pressing together a first support element, an insulative element and a second support element for bonding the first support element to the second support element to form a construction unit, subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane and the conductor traces of the intermediate plane at programmatically predetermined locations, inverting the construction unit, subsequently boring a second plurality of holes in accordance with a second mirror-image hole schedule and extending between a bottom plane and associated conductor traces of the intermediate plane at programmatically predetermined locations, metallizing all holes of the first plurality of holes and the second plurality of holes for electrically interconnecting the component plane, the intermediate plane and the bottom plane, fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by etching and fabricating correspondingly arranged conductor traces in the bottom plane by etching.
In other words, the method of the present invention is manifested by the features that it comprises the steps of photo-etching a first metal layer provided on a second side of a substantially planar first support element to form a desired one of conductor traces extending substantially parallel to a predetermined direction, conductor traces extending substantially perpendicular to the predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to the predetermined direction, pressure-bonding the first support element to a substantially planar second support element by the intermediary of a substantially planar insulative bonding element to form a multilayer circuit board blank, boring a plurality of blind holes extending from a second metal layer provided on an exposed first side of the second support element through the insulative bonding element and through desired ones of the conductor traces formed on the second side of the first support element at desired locations, inverting the multilayer circuit board blank, boring a plurality of holes extending from a third metal layer provided on an exposed first side of the first support element through desired ones of the conductor traces formed on the second side of the first support element at desired locations such that desired holes of the plurality of holes axially coincide with desired holes of the plurality of blind holes to form through holes extendi.ng from the first metal layer to the third metal l~yer and such that remaining holes of the plurality of holes form blind holes, metallizing all holes of the blind holes and the through holes for electrically interconnecting the first metal layer with desired ones of the conductor traces formed on the second side of the first support element for electrically interconnecting the ~Z;~'781~
third metal layer with desired ones of the conductor traces formed on the second side of the first support element and for electrically directly interconnecting the second metal layer with the third metal layer independently of the conductor traces formed on the second side of the first support element, photo-etching the second metal layer to form a desired configuration of contact pads and power conducting traces, and photo-etching the third metal layer to form conductor traces extending substantially parallel to the predetermined direction.
BRIEF DESCRIPTION OF THE DRAWINGS
. _ The invention will be better understood and objects other than those set forth above will become apparent when consideration is given to the following detailed description thereof. Such description makes reference to the annexed drawings wherein throughout the various figures of the drawings there have been generally used the same reference characters to denote the same or analogous components and wherein:
Figure 1 schematically shows a multisubstrate circuit arrangement as an embodiment of the invention in cross-section and on an enlarged scale; and :1~3'7~:~9 Figure 2 schematically shows the circuit arrangement of Figure 1 in exploded perspective view.
DETAILE~ DESCRIPTION OF THE PREFERRED EMBODIMENTS
Describing now the drawings, it is to be understood that to simplify the showing thereof only enough of the structure of the multisubstrate circuit arrangement has been illustrated therein as is needed to enable one skilled in the art to readily understand the underlying principles and concepts of this invention. Turning now specifically to Figure 1 of the drawings, the structure illustrated therein by way of example and not limitation will be seen to comprise a three-layer superimposed or laminated multisubstrate circuit arrangement which essentially comprises a first substrate 10 serving as a first support sheet or laminate as well as a second substrate 20 serving as a second support sheet or laminate. A pre-impregnated insulative sheet material 30, such as for instance the commercially available product Prepreg, is employed as an adhesive or bonding agent and as an insulator between the first and second substrates 10 and ~0. The first substrate 10 is coated on first and second sides thereof with a not particularly referenced suitable metal layer which is etched into separate, mutually spaced, conducting tracks or traces using a known photolithographic process of semiconductor technology, i.e. photo-etching. The second substrate 20 is ~f~ 3~
coated on a first side only thereof with a not particularly referenced suita~le metal layer whic~ is also, as described a~ove, suh-divtded tnto indiv~dual contact surfaces or pads or into conducting tracks ~r traces ay etch~ng.
The circu~t arrangemen~ tS presented ~n exploded perspective v~e~ in Figure 2 and ~ithout t~e sheet of insulative material 3Q. T~e second su~strate 2Q having mult~ple contact surfaces ox pads 22, 23, 24, 25, 26, 26' and 27 etc~ed ~rom the met~l layer as ~ell as a conduct~ng track or trace 28 used as an electr~cal current supply track or rail and electrically connected to the contact surface 26 ~y a path or trace 26', can ~e recogn~zed, Furthermore, the first su~strate 10, ~h~cH.~s provided wit~ conducting tracks ar traces 31, 32, 33, 34, 35, 36 and 37 formed from a metal layer on the second side o~ the ~irst su~strate lQ facing t~e second su~strate 2Q and which ~u~th.er i`5 pxov~ded with con-ducting trac~s or txaces 13, 14, 15, 16, 17 and 18 etc~ed ~om th.e ~etal layer on t~e ~rst s~.de c~ tn.e ~irst su~trate lQ. ~ci~ng aw~y~rom t~e second suPstrate 2U, can ~e ~ecogn~zed. T~.e canducting t~ac~s~ ~r tr~c~s 31 to 37 P~ovided on tH.e second s~de ~ac~g t~e second subs~t~ate 2a can ~e o~ented suhstant~lly ~n e~,ther of two mutually orthDgonal d~rections indic~ted ~y~the dou~le-h.eaded ar~ows X
and X in Figure 2 or in ~oth.of these di~ections, wh~le the conducting tracks or traces 13 to 18 arranged on the under or ~ ~2 ~
1~3~7~ 1~
first side of the first substrate 10 may be oriented substantially in only the direction indicated by the arrow Y.
The conducting tracks or traces 13 to 18 as well as 31 to 37 provided on the first substrate 10, as well as the contact surfaces or pads 22 to 27 and the current supply track or rail 28 provided on the second substrate 20, are etched from the actual metal layers according to a program (CAD). The metal layers can consist of, for example, a bonded copper foil or of a vapor-deposited or sputtered copper layer, or the like.
The electrical contacts in the circuit arrangement described above must not only be established between the contact surfaces or pads 22 to 27 on a component plane indicated by the arrow A and the conducting tracks or traces 31 to 37 in an intermediate plane indicated by the arrow B and oriented in the X or Y direction, or both, but also, as illustrated in Figure 1 and Figure 2, must be established between the contact surfaces or pads 22 to 27 of the component plane A, the conducting tracks or traces 31 to 37 of the intermediate plane B and the conducting tracks or traces 13 to 18 of a lower or bottom plane of the first substrate 10 indicated by the arrow C and oriented in the Y direction. The contact surfaces or pads 22 io 27, the contact tracks or traces 31 to 37 as well as the sontact tracks ox traces 13 to 18 can hereby be displaced in the X or Y direction, or both, in relation to each other. Essentially, this is achieved ~y a processing step wherein a first set of holes 1', 3", 4', 6' and 7' is ~ored in thedirections indicated ~y the arrows 1, 3, 4, 6 and 7. The holes are bored, for instance using a first hole schedule ~CAD-data~, at pre-programmed locations ~here an electrical connect~on ~etween the metal layer o~ the component plane A and the corresponding conducting tracks or traces of the intermediate plane B are to ~e esta~lished. The holes are bored after t~.e conducting tracks ~r traces in t~e intermediate plane B ha~e ~een etc~ed and the separate elements 10, 20 and 3Q have ~een ~onded into a 6ingle unit.
The uni.t ~.s inyerted ~n a ~econd processing step and positioned ~,n suc~ a manner tnat, at pre-programmed locations ~nere an electr~c~l connect~on ~etween the metal layer o~ the lo~er or ~ottom plane ~ and the corresponding conducting trac~s or traces of the intermed~ate plane B are to ~e esta~lis~.ed, a second set o~ holes 2~, 3", 5~ and 6" is ~ored uslng a second ~o~ed ~Ple schedule ~CAD-datal ~n the directions ~ndicated ~y t~e ar~ow~ 2, 3~, 5~ and 6~. T~e holes 1~, 2~, 4~, 5~ and 7 t are sh~ s~ ~lin~ noles i`n ~gure 1.
The hole$ 3" and 6'~, due to t~e do~ s~ded boring process, ~ecome th.rough holes. T~e ~oles 1~, 2~, 3~, 4~, 5l, 6" and 7' are metallized ~,n a thi`rd process~ng step wherein electrical interconnection o~ th.e met~ ers of the separate planes A, B
a,nd C ~s ach.~eved. The contact sur~aces or pads 22 to 27, as 8.~
well as the current supply track or rail 28 on the component plane A and the conducting tracks or traces 13 to 18 oriented in the Y direction on *he lower or bottom plane C, are now produced by etching.
Claims (12)
1. A multiple substrate circuit arrangement between individual metal layers applied to mutually insulated and mutually pressure-bonded support elements and separable into contact surfaces, conductor traces or both, wherein:
the multiple substrate circuit arrangement is fabricated as a pressure-bonded, three-layer multiple substrate;
said pressure-bonded, three-layer multiple substrate comprising a component plane, an intermediate plane and a bottom plane;
said multiple substrate circuit arrangement comprising a double-sided metallized support element defining a first support element of the mutually insulated and mutually pressure-bonded support elements;
said multiple substrate circuit arrangement comprising a single-sidedly metallized support element defining a second support element of the mutually insulated and mutually pressure-bonded support elements;
said multiple substrate circuit arrangement comprising an insulative element arranged between said first support element and said second support element;
said component plane having an exposed metal layer of said single-sidedly metallized support element for defining a first metal layer of the individual metal layers;
said bottom plane having an exposed metal layer of said double-sidedly metallized support element for defining a second metal layer of the individual metal layers;
said intermediate plane having a sandwiched metal layer of said double-sidedly metallized support element for defining a third metal layer;
said first metal layer defined by said exposed metal layer of said component plane being electrically connected to said third metal layer defined by said sandwiched metal layer by a first set of metallized blind holes extending from said exposed metal layer of said component plane;
said second metal layer defined by said exposed metal layer of said bottom plane being electrically connected to said third metal layer defined by said sandwiched metal layer by a second set of metallized blind holes extending from said exposed metal layer of said bottom plane;
said first set of metallized blind holes being arranged in offset relationship with respect to said second set of metallized blind holes;
respective predetermined ones of said blind holes of said first set of metallized blind holes being electrically conductively connected with respective predetermined ones of said offset blind holes of said second set of metallized blind holes by means of predetermined portions of said first, second and third metal layers; and said first metal layer defined by said exposed metal layer of said component plane and said second metal layer defined by said exposed metal layer of said bottom plane being mutually electrically interconnected by metallized through holes extending between said exposed metal layer of said component plane and said exposed metal layer of said bottom plane.
the multiple substrate circuit arrangement is fabricated as a pressure-bonded, three-layer multiple substrate;
said pressure-bonded, three-layer multiple substrate comprising a component plane, an intermediate plane and a bottom plane;
said multiple substrate circuit arrangement comprising a double-sided metallized support element defining a first support element of the mutually insulated and mutually pressure-bonded support elements;
said multiple substrate circuit arrangement comprising a single-sidedly metallized support element defining a second support element of the mutually insulated and mutually pressure-bonded support elements;
said multiple substrate circuit arrangement comprising an insulative element arranged between said first support element and said second support element;
said component plane having an exposed metal layer of said single-sidedly metallized support element for defining a first metal layer of the individual metal layers;
said bottom plane having an exposed metal layer of said double-sidedly metallized support element for defining a second metal layer of the individual metal layers;
said intermediate plane having a sandwiched metal layer of said double-sidedly metallized support element for defining a third metal layer;
said first metal layer defined by said exposed metal layer of said component plane being electrically connected to said third metal layer defined by said sandwiched metal layer by a first set of metallized blind holes extending from said exposed metal layer of said component plane;
said second metal layer defined by said exposed metal layer of said bottom plane being electrically connected to said third metal layer defined by said sandwiched metal layer by a second set of metallized blind holes extending from said exposed metal layer of said bottom plane;
said first set of metallized blind holes being arranged in offset relationship with respect to said second set of metallized blind holes;
respective predetermined ones of said blind holes of said first set of metallized blind holes being electrically conductively connected with respective predetermined ones of said offset blind holes of said second set of metallized blind holes by means of predetermined portions of said first, second and third metal layers; and said first metal layer defined by said exposed metal layer of said component plane and said second metal layer defined by said exposed metal layer of said bottom plane being mutually electrically interconnected by metallized through holes extending between said exposed metal layer of said component plane and said exposed metal layer of said bottom plane.
2. The multiple substrate circuit arrangement as defined in claim 1, wherein:
said component plane is provided with a plurality of contact surfaces and a current supply means;
said intermediate plane being provided with a first plurality of conductor traces;
said multiple substrate circuit arrangement having a predetermined reference direction each conductor trace of said first plurality of conductor traces extending substantially in a desired one of a direction parallel to said predetermined reference direction, a direction perpendicular to said predetermined reference direction and a combination of two respective directions extending parallel and perpendicular to said predetermined reference direction;
said bottom plane being provided with a second plurality of conductor traces; and each conductor trace of said second plurality of conductor traces extending substantially in a direction parallel to said predetermined reference direction.
said component plane is provided with a plurality of contact surfaces and a current supply means;
said intermediate plane being provided with a first plurality of conductor traces;
said multiple substrate circuit arrangement having a predetermined reference direction each conductor trace of said first plurality of conductor traces extending substantially in a desired one of a direction parallel to said predetermined reference direction, a direction perpendicular to said predetermined reference direction and a combination of two respective directions extending parallel and perpendicular to said predetermined reference direction;
said bottom plane being provided with a second plurality of conductor traces; and each conductor trace of said second plurality of conductor traces extending substantially in a direction parallel to said predetermined reference direction.
3. The multiple substrate circuit arrangement as defined in claim 1, wherein:
the multiple substrate circuit arrangement comprises the mutually insulated and mutually pressure-bonded support elements and said insulative element; and the multiple substrate circuit arrangement being fabricated as a construction unit.
the multiple substrate circuit arrangement comprises the mutually insulated and mutually pressure-bonded support elements and said insulative element; and the multiple substrate circuit arrangement being fabricated as a construction unit.
4. The multiple substrate circuit arrangement as defined in claim 1, wherein:
said multiple substrate circuit arrangement comprises at most two support elements; and said at most two support elements comprising said first support element defined by said double-sidedly metallized support element and said second support element defined by said single-sidedly metallized support element.
said multiple substrate circuit arrangement comprises at most two support elements; and said at most two support elements comprising said first support element defined by said double-sidedly metallized support element and said second support element defined by said single-sidedly metallized support element.
5. The multiple substrate circuit arrangement as defined in claim 1, wherein:
said individual metal layers comprise only three metal layers; and said at least three metal layers comprising said first metal layer defined by said exposed metal layer of said single-sidedly metallized support element, said second metal layer defined by said exposed metal layer of said double-sidedly metallized support element and said third metal layer defined by said sandwiched metal layer of said double-sidedly metallized support element.
said individual metal layers comprise only three metal layers; and said at least three metal layers comprising said first metal layer defined by said exposed metal layer of said single-sidedly metallized support element, said second metal layer defined by said exposed metal layer of said double-sidedly metallized support element and said third metal layer defined by said sandwiched metal layer of said double-sidedly metallized support element.
6. The multiple substrate circuit arrangement as defined in claim 1, wherein:
selected ones of said first set of metallized blind holes align with associated ones or said second set of blind holes for forming said metallized through holes.
selected ones of said first set of metallized blind holes align with associated ones or said second set of blind holes for forming said metallized through holes.
7. A multilayer circuit board, comprising:
a substantially planar first support element;
a substantially planar second support element;
a substantially planar insulative element for bonding said first support element and said second support element together;
said first support element having a first side remote from said second support element and a second side confronting said second support element and bonded to said insulative element;
said second support element having a first side remote from said first support element and a second side confronting said first support element and bonded to said insulative element;
said first side of said first support element being provided with a first metal layer;
said second side of said first support element being provided with a second metal layer;
said first side of said second support element being provided with a third metal layer;
said first support element being provided with blind holes extending from said first side thereof through said first metal layer of said first side thereof and through said second metal layer of said second side thereof;
said blind holes of said first support element being metallized for electrically interconnecting said first metal layer of said first side of said first support element with said second metal layer of said second side thereof;
said second support element being provided with blind holes extending from said first side thereof through said third metal layer of said first side thereof and through said insulative element and through said second metal layer of said second side of said first support element;
said blind holes of said second support element being metallized for electrically interconnecting said second metal layer of said second side of said first support element with said third metal layer of said first side of said second support element;
said blind holes of said first support element being arranged in offset relationship with respect to said blind holes of said second support element;
respective predetermined ones of said blind holes of said first support element being electrically conductively connected with respective predetermined ones of said offset blind holes of said second support element by means of predeterminate portions of said first, second and third metal layers;
predetermined ones of said blind holes of said first support element axially coinciding with predetermined ones of said blind holes of said second support element such that through holes are formed extending from said first side of said first support element at least through said first metal layer of said first side thereof and said third metal layer of said first side of said second support element to said first side of said second support element;
and said through holes being metallized for electrically interconnecting said first metal layer of said first side of said first support element with said third metal layer of said first side of said second support element.
a substantially planar first support element;
a substantially planar second support element;
a substantially planar insulative element for bonding said first support element and said second support element together;
said first support element having a first side remote from said second support element and a second side confronting said second support element and bonded to said insulative element;
said second support element having a first side remote from said first support element and a second side confronting said first support element and bonded to said insulative element;
said first side of said first support element being provided with a first metal layer;
said second side of said first support element being provided with a second metal layer;
said first side of said second support element being provided with a third metal layer;
said first support element being provided with blind holes extending from said first side thereof through said first metal layer of said first side thereof and through said second metal layer of said second side thereof;
said blind holes of said first support element being metallized for electrically interconnecting said first metal layer of said first side of said first support element with said second metal layer of said second side thereof;
said second support element being provided with blind holes extending from said first side thereof through said third metal layer of said first side thereof and through said insulative element and through said second metal layer of said second side of said first support element;
said blind holes of said second support element being metallized for electrically interconnecting said second metal layer of said second side of said first support element with said third metal layer of said first side of said second support element;
said blind holes of said first support element being arranged in offset relationship with respect to said blind holes of said second support element;
respective predetermined ones of said blind holes of said first support element being electrically conductively connected with respective predetermined ones of said offset blind holes of said second support element by means of predeterminate portions of said first, second and third metal layers;
predetermined ones of said blind holes of said first support element axially coinciding with predetermined ones of said blind holes of said second support element such that through holes are formed extending from said first side of said first support element at least through said first metal layer of said first side thereof and said third metal layer of said first side of said second support element to said first side of said second support element;
and said through holes being metallized for electrically interconnecting said first metal layer of said first side of said first support element with said third metal layer of said first side of said second support element.
8. The multilayer circuit board as defined in claim 7, wherein:
said first metal layer of said first side of said first support element is etched to form conductor traces extending substantially parallel to a predetermined direction;
said second metal layer of said second side of said first support element being etched to form a desired one of conductor traces extending substantially parallel to said predetermined direction, conductor traces extending substantially perpendicular to said predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to said predetermined direction;
said third metal layer of said first side of said second support element being etched to form contact pads and power conducting traces;
said metallized blind holes of said first support element electrically interconnecting desired ones of said conductor traces of said first side of said first support element with desired ones of said conductor traces of said second side thereof;
said metallized blind holes of said second support element electrically interconnecting desired ones of said conductor traces of said second side of said first support element with desired ones of said contact pads and said power conducting traces of said first side of said second support element; and said metallized through holes electrically interconnecting desired ones of said conductor traces of said first side of said first support element with desired ones of said contact pads and power conducting traces of said first side of said second support element.
said first metal layer of said first side of said first support element is etched to form conductor traces extending substantially parallel to a predetermined direction;
said second metal layer of said second side of said first support element being etched to form a desired one of conductor traces extending substantially parallel to said predetermined direction, conductor traces extending substantially perpendicular to said predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to said predetermined direction;
said third metal layer of said first side of said second support element being etched to form contact pads and power conducting traces;
said metallized blind holes of said first support element electrically interconnecting desired ones of said conductor traces of said first side of said first support element with desired ones of said conductor traces of said second side thereof;
said metallized blind holes of said second support element electrically interconnecting desired ones of said conductor traces of said second side of said first support element with desired ones of said contact pads and said power conducting traces of said first side of said second support element; and said metallized through holes electrically interconnecting desired ones of said conductor traces of said first side of said first support element with desired ones of said contact pads and power conducting traces of said first side of said second support element.
9. The multilayer circuit board as defined in claim 7, wherein:
the multilayer circuit board is integrally modular in configuration.
the multilayer circuit board is integrally modular in configuration.
10. A method of fabricating a multiple substrate circuit arrangement and electrical interconnections thereof, comprising the steps of:
photo-etching a metal layer of an intermediate plane to form conductor traces;
providing a first support element, an insulative element and a second support element;
pressing together said first support element, said insulative element and said second support element for bonding said first support element to said second support element by the intermediary of said insulative element to form a construction unit with said insulative element sandwiched between said first support element and said second support element;
subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane at an exposed side of said second support element and said conductor traces of said intermediate plane at programmatically predetermined locations;
inverting said construction unit;
subsequently boring a second plurality of holes in accordance with a second mirror-image hole schedule and extending between a bottom plane of an exposed side of the first support element and associated conductor traces of said intermediate plane at programmatically predetermined locations;
the boring of the first plurality of holes at the exposed side of the second support element and the boring of the second plurality of holes at the exposed side of the first support element being accomplished such that at least one of the first plurality of holes defines a blind hole, at least one of the second plurality of holes defines a blind hole, and at least one further one of the first plurality of holes and at least one further one of the second plurality of holes are axially aligned with one another to form a through hole;
metallizing all holes of said first plurality of holes and said second plurality of holes for electrically interconnecting said component plane, said intermediate plane and said bottom plane;
fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by photo-etching; and fabricating correspondingly arranged conductor traces in said bottom plane by photo-etching.
photo-etching a metal layer of an intermediate plane to form conductor traces;
providing a first support element, an insulative element and a second support element;
pressing together said first support element, said insulative element and said second support element for bonding said first support element to said second support element by the intermediary of said insulative element to form a construction unit with said insulative element sandwiched between said first support element and said second support element;
subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane at an exposed side of said second support element and said conductor traces of said intermediate plane at programmatically predetermined locations;
inverting said construction unit;
subsequently boring a second plurality of holes in accordance with a second mirror-image hole schedule and extending between a bottom plane of an exposed side of the first support element and associated conductor traces of said intermediate plane at programmatically predetermined locations;
the boring of the first plurality of holes at the exposed side of the second support element and the boring of the second plurality of holes at the exposed side of the first support element being accomplished such that at least one of the first plurality of holes defines a blind hole, at least one of the second plurality of holes defines a blind hole, and at least one further one of the first plurality of holes and at least one further one of the second plurality of holes are axially aligned with one another to form a through hole;
metallizing all holes of said first plurality of holes and said second plurality of holes for electrically interconnecting said component plane, said intermediate plane and said bottom plane;
fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by photo-etching; and fabricating correspondingly arranged conductor traces in said bottom plane by photo-etching.
11. A method of fabricating a multilayer circuit board, comprising the steps of:
photo-etching a first metal layer provided on a second side of a substantially planar first support element to form a desired one of conductor traces extending substantially parallel to a predetermined direction, conductor traces extending substantially perpendicular to said predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to said predetermined direction;
pressure-bonding said first support element to a substantially planar second support element by the intermediary of a substantially planar insulative bonding element to form a multilayer circuit board blank;
boring a plurality of blind holes extending from a second metal layer provided on an exposed first side of said second support element through said insulative bonding element and through desired ones of said conductor traces formed on said second side of said first support element at desired locations;
inverting said multilayer circuit board blank;
boring a plurality of holes extending from a third metal layer provided on an exposed first side of said first support element through desired ones of said conductor traces formed on said second side of said first support element at desired locations such that desired holes of said plurality of holes axially coincide with desired holes of said plurality of blind holes to form through holes extending from said second metal layer to said third metal layer and such that remaining holes of said plurality of holes form blind holes;
metallizing all holes of said blind holes and said through holes for electrically interconnecting said first metal layer with desired ones of said conductor traces formed on said second side of said first support element, for electrically interconnecting said third metal layer with desired ones of said conductor traces formed on said second side of said first support element and for electrically directly interconnecting said second metal layer with said third metal layer independently of said conductor traces formed on said second side of said first support element;
photo-etching said second metal layer to form a desired configuration of contact pads and power conducting traces; and photo-etching said third metal layer to form conductor traces extending substantially parallel to said predetermined direction.
photo-etching a first metal layer provided on a second side of a substantially planar first support element to form a desired one of conductor traces extending substantially parallel to a predetermined direction, conductor traces extending substantially perpendicular to said predetermined direction and conductor traces extending both substantially parallel and substantially perpendicular to said predetermined direction;
pressure-bonding said first support element to a substantially planar second support element by the intermediary of a substantially planar insulative bonding element to form a multilayer circuit board blank;
boring a plurality of blind holes extending from a second metal layer provided on an exposed first side of said second support element through said insulative bonding element and through desired ones of said conductor traces formed on said second side of said first support element at desired locations;
inverting said multilayer circuit board blank;
boring a plurality of holes extending from a third metal layer provided on an exposed first side of said first support element through desired ones of said conductor traces formed on said second side of said first support element at desired locations such that desired holes of said plurality of holes axially coincide with desired holes of said plurality of blind holes to form through holes extending from said second metal layer to said third metal layer and such that remaining holes of said plurality of holes form blind holes;
metallizing all holes of said blind holes and said through holes for electrically interconnecting said first metal layer with desired ones of said conductor traces formed on said second side of said first support element, for electrically interconnecting said third metal layer with desired ones of said conductor traces formed on said second side of said first support element and for electrically directly interconnecting said second metal layer with said third metal layer independently of said conductor traces formed on said second side of said first support element;
photo-etching said second metal layer to form a desired configuration of contact pads and power conducting traces; and photo-etching said third metal layer to form conductor traces extending substantially parallel to said predetermined direction.
12. A method of fabricating a multiple substrate circuit arrangement and electrical interconnections thereof, comprising the steps of:
photo-etching a metal layer of an intermediate plane to form conductor traces;
providing a first support element, an insulative element and a second support element;
pressing together said first support element, said insulative element and said second support element for bonding said first support element to said second support element by the intermediary of said insulative element to form a construction unit with said insulative element sandwiched between said first support element and said second support element;
subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane at an exposed side of said second support element and said conductor traces of said intermediate plane at programmatically predetermined locations;
inverting said construction unit;
subsequently boring a second plurality of holes in accordance with a second hole schedule and extending between a bottom plane of an exposed side of the first support element and associated conductor traces of said intermediate plane at programmatically predetermined locations;
the boring of the first plurality of holes at the exposed side of said second support element and the boring of said second plurality of holes at the exposed side of the first support element being accomplished such that at least one of the first plurality of holes and at least one of the second plurality of holes are axially aligned with one another to form a through hole;
metallizing all holes of said first plurality of holes and said second plurality of holes for electrically interconnecting said component plane, said intermediate plane and said bottom plane;
fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by photo-etching; and fabricating correspondingly arranged conductor traces in said bottom plane by photo-etching.
photo-etching a metal layer of an intermediate plane to form conductor traces;
providing a first support element, an insulative element and a second support element;
pressing together said first support element, said insulative element and said second support element for bonding said first support element to said second support element by the intermediary of said insulative element to form a construction unit with said insulative element sandwiched between said first support element and said second support element;
subsequently boring a first plurality of holes in accordance with a first hole schedule and extending between a metal layer of a component plane at an exposed side of said second support element and said conductor traces of said intermediate plane at programmatically predetermined locations;
inverting said construction unit;
subsequently boring a second plurality of holes in accordance with a second hole schedule and extending between a bottom plane of an exposed side of the first support element and associated conductor traces of said intermediate plane at programmatically predetermined locations;
the boring of the first plurality of holes at the exposed side of said second support element and the boring of said second plurality of holes at the exposed side of the first support element being accomplished such that at least one of the first plurality of holes and at least one of the second plurality of holes are axially aligned with one another to form a through hole;
metallizing all holes of said first plurality of holes and said second plurality of holes for electrically interconnecting said component plane, said intermediate plane and said bottom plane;
fabricating contact surfaces and conductor surfaces in mutual spaced relationship in said component plane by photo-etching; and fabricating correspondingly arranged conductor traces in said bottom plane by photo-etching.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH567484 | 1984-11-28 | ||
| CH5674/84-1 | 1984-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1237819A true CA1237819A (en) | 1988-06-07 |
Family
ID=4297513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000496297A Expired CA1237819A (en) | 1984-11-28 | 1985-11-27 | Multilayer circuit arrangement and method of manufacturing such multilayer circuit arrangement and its electric connections |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0183936A1 (en) |
| JP (1) | JPS61131598A (en) |
| CA (1) | CA1237819A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3639402A1 (en) * | 1986-11-18 | 1988-05-19 | Siemens Ag | METHOD FOR THE PRODUCTION OF A MULTI-LAYERED CIRCUIT BOARD AND THE CIRCUIT BOARD PRODUCED THEREOF |
| US4927983A (en) * | 1988-12-16 | 1990-05-22 | International Business Machines Corporation | Circuit board |
| JPH0499394A (en) * | 1990-08-17 | 1992-03-31 | Cmk Corp | Multilayer printed circuit board |
| CA2071662A1 (en) * | 1991-06-26 | 1992-12-27 | Jon J. Gulick | Integrated socket-type package for flip-chip semiconductor devices and circuits |
| US5345256A (en) * | 1993-02-19 | 1994-09-06 | Compaq Computer Corporation | High density interconnect apparatus for an ink jet printhead |
| EP0852451A3 (en) * | 1997-01-02 | 2004-05-12 | Siemens Audiologische Technik GmbH | Hearing aid |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3649475A (en) * | 1969-07-22 | 1972-03-14 | Gen Dynamics Corp | Multi-layer printed circuit boards and methods of making same |
| DE2053221A1 (en) * | 1970-10-29 | 1972-05-04 | Sel | Multi-layer circuit with electrical through-connection |
| FR2241946B1 (en) * | 1973-08-24 | 1976-11-19 | Honeywell Bull Soc Ind |
-
1985
- 1985-09-27 EP EP85112266A patent/EP0183936A1/en not_active Withdrawn
- 1985-11-18 JP JP25683385A patent/JPS61131598A/en active Pending
- 1985-11-27 CA CA000496297A patent/CA1237819A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61131598A (en) | 1986-06-19 |
| EP0183936A1 (en) | 1986-06-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |