CA1231440A - Read channel for optical recorder - Google Patents
Read channel for optical recorderInfo
- Publication number
- CA1231440A CA1231440A CA000473236A CA473236A CA1231440A CA 1231440 A CA1231440 A CA 1231440A CA 000473236 A CA000473236 A CA 000473236A CA 473236 A CA473236 A CA 473236A CA 1231440 A CA1231440 A CA 1231440A
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Abstract
ABSTRACT OF THE Disclosure Disclosed is a read channel for an optical recorder.
Data is recorded on the media in a fixed block code. The data is read and the location of the holes within a symbol are determined for the the odd and even symbol positions separately. The loca-tion of the hole is determined for an odd or an even hole by using two sample and hold cells to hold the signal value received at a symbol position and compare it to the signal value received at a previous position. If the comparison results in a new higher valued signal being found, the output of the comparator changes.
If the output of the comparator changes, the address of the change is recorded. The last such change denotes the location of the symbol position having the highest signal value, which is the address of the hole. The address of the holes, even and odd, are used to directly convert from the fixed block code to binary. Two symbols convert to 8 binary bits.
Data is recorded on the media in a fixed block code. The data is read and the location of the holes within a symbol are determined for the the odd and even symbol positions separately. The loca-tion of the hole is determined for an odd or an even hole by using two sample and hold cells to hold the signal value received at a symbol position and compare it to the signal value received at a previous position. If the comparison results in a new higher valued signal being found, the output of the comparator changes.
If the output of the comparator changes, the address of the change is recorded. The last such change denotes the location of the symbol position having the highest signal value, which is the address of the hole. The address of the holes, even and odd, are used to directly convert from the fixed block code to binary. Two symbols convert to 8 binary bits.
Description
Lo ~l~L~3 Roy invention relates generally to the field of optical recording systems and more particularly to apparatus for detecting and decoding data therefrom.
Prior art optical recorder systems using fixed block code formatted data read the data by first delaying the data so that the signal values of all symbol positions were present at a series of comparators at the same instant of time, at Lucia time the comparators were operated to determine the two locations (assuming a code having two holes per symbol) within the symbol which had the highest signal values for the hole associated power of the reflected laser beam. (Hole associated power may be taken to mean the inverse of the power of the reflected laser beam.) These were the locations of the holes. Thereafter, the hole toga-lions were converted from the fixed hock code to binary using somewhat complex logic. The entire apparatus was somewhat comply-acted, expensive in the use of delay lines and comparators, and prone to failure due to loss of signal in the various delay lines.
SUMMARY OF THE INVENTION
The invention comprises breaking the apparatus which decodes the hole position of the fixed block codes separately for the even and odd symbol positions. For each, two sample and hold cells are provided, and these are input to one comparator. One sample and hold cell in each respective comparator is respectively clocked at the first even and the first odd symbol positions. The other is clocked at the next even or odd position. If the second is higher, the output of the comparator changes. If it is not, ,, the output of the comparator does not change. In either case, the timing circuit knows which cell has the highest valued signal in it and clocks the other the one with the lower valued signal, at the next even or odd symbol position. This process continues until all symbol positions have been sampled, except for the ninth, which is always empty. If a hole is present in the symbol in either the even or odd positions, the last time the comparator for the even or odd sample and hold will change is at the symbol.
Every time the state of the respective even and odd comparators changes, a transition detector connected to the respective compare atop, signals the change by generating an even or odd pulse. This even or odd pulse causes the output of a symbol position counter to be input into an even or odd register. The even and odd ad-dresses of the holes in the symbol together form the four binary bits of the encoded information. Two consecutive symbols are decoded, and the eight bits of binary data encoded by the two symbols are formed into eight binary bits and output on a data bus.
Thus, in accordance with one broad aspect ox the invent lion, there is provided apparatus for differential decoding of fixed-block encoded data comprising signals read from an apparatus having data recorded thereon in a fixed-block code, comprising TOWN counter means for counting the symbol positions within a symbol, including means for initializing said ONE counter after reaching the count ox the last symbol position of the symbol; a pair of even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon yin a Eixed-blocked format comprising symbols having a predetermined number of symbol positions in which Hess may be written; a pair of odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format; means no-sponsive to said TOWN counter means for triggering a first of said even pair of sample and hold Silas at the first even symbol post-lion of a symbol; means responsive to said TOWN counter means for triggering a second of said even pair of sample and hold cells at the second even symbol position of a symbol even comparator means for comparing the first even sample and hold cell valve with the second even sample and hold cell value and for generating an even comparator output indicative of the results of the comparison;
means responsive to said TOWN counter means and to said even come portray means for retaining the value it the even sample and hold cell having the higher value and for triggering the other even sample and hold cell at the next even symbol position and for repeating said retention end said triggering of the other even sample and hold cell at the occurrence of every even symbol post-lion for which the fixed-block code may contain a hole; means responsive to said TOWN counter means for triggering a first of said odd pair of sample and hold cells at the first odd symbol position of a symbol; means responsive to said TOWN counter means for triggering a second of said odd pair of sample and hold cells at the second odd symbol position of a symbol; odd comparator means for comparing the first odd sample and hold cell value with the second odd sample and hold cell value and for generating an odd comparator output indicative of the results of the comparison;
means responsive to said TOWN counter means and to said odd come portray means for retaining the value in the odd sample and hold cell having the higher value and for triggering the other odd sample and hold cell at the next odd symbol position and for repeating said retention and said triggering of the other odd sample and hold cell at the occurrence of every odd symbol post-lion for which the fixed-block code may contain data; even binary register means responsive to a change in the state of said even comparator output for recording the count of said TOWN counter divided by two, ignoring fractions; old binary resister means responsive to a change in the state of said odd comparator output for recording the count of said ONE counter divided by two, Gino-ring fractions; output register means for loading the contents of said even and said odd binary register means into at least one output register at the end of a symbol.
In accordance with another broad aspect ox the invention there is provided apparatus for differential decoding of fixed block encoded data comprising signals read from an apparatus having data recorded thereon in a fi~ed-block code, comprising symbol counter means for counting the symbol positions within a symbol, including means for initializing said symbol courter after reaching the count of the last symbol position of the symbol; n even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed bloc format comprisirlg symbols having a predetermined number of symbol positions in which holes may be written and a predetermined number, 2 on - 1), of holes, half written in even positions and half written in odd positions; n odd sample and hold cells responsive to said read signals from said apparatus reading data from sated medium having data recorded thereon in a fixed block format; means responsive to said symbol counter means for triggering a first of said n even sample and hold cells at the first even symbol position of a symbol; means responsive to said symbol counter means for triggering successive others of said n even sample and hold cells at successive even symbol positions of lo a symbol, the number of successive cells triggered corresponding to the number, n - 1, of holes which may be written in even post-lions; n (n - lo even comparator means err comparing each even sample and hold cell value with each of the other even sample and hold cell values; means responsive to said symbol counter means and to said n (n - 1)~2 even comparator means for retaining the values in the even sample and hold cells having the higher values and for triggering the even sample and hold cell having the lowest value at the next even symbol position and for repeating said retention and said triggering of the even sample and hold cell having the lowest value at the occurrence of every even symbol position for which the fixed-block code may contain a hole; means responsive to said symbol counter means for triggering a eeriest of said n odd sample and hold cells at the first odd symbol position ox a symbol; means responsive to said symbol counter means for triggering successive others of said n odd sample and hold cells at successive odd symbol positions of a symbol, the number of cells triggered corresponding to the number, n - l, of holes which may be written in odd positions; n (n - 1)/2 odd comparator means for comparing each odd sample and hold cell value with each of the other odd sample and hold cell values; and means responsive to said symbol counter means and to said n (n - 1)/2 odd compare atop means for retaining the values in the odd sample and held cells having the higher values and for triggering the odd sample and hold cell having the lowest value at the next odd symbol post-lion and for repeating said retention and said triggering of the odd sample and hold cell having the lowest value at the occurrence of every odd symbol position for which the Eixed-block code may contain a hole.
BRIEF DESCRIPTION OF THE DUNKS
Figure 1 is a block diagram of the read channel of the present invention.
Figure 2 shows the TOWN code and its corresponding bin-cry equivalent.
Figure 3 is a timing diagram of various signals gene-rated by the read channel of the present invention.
Figure 4 it a schematic circuit diagram of the critical circuits of the present invention.
Figure 5, on the second sheet of drawings, is a timing diagram showing the fine timing differences between several of the signals of Figure 3.
Figure 6 (on two sheets) is a blackjack diagram of a vane-lion of the invention for a 4/15 code.
INSCRIPTION OF TIE Proofread EI~IE3ODIMENT
Figure 1 shows a block diagram of the read channel according to the present invention. The optical recorder reading the information from the optical disk does so conventionally by means of a laser operated at read power. The beam reflects from the disk, and the drop in reflection normally indicates the pros-once of a hole. Because reflected spot density distributions have a Gaussian shape, the hole associated power of the reflected beam (the hole associated power means the inverse of the reflected power from the disk) spreads a significant distance beyond the boundaries OX the holes themselves. Indeed, the hole power pro-sent at the center of the next possible position of a hole in closely spaced systems may be significant. Therefore, one cannot rely on threshold detectors to detect the presence of a hole, because the threshold may be reached due to a hole at an earlier or later position, or a combination of the two. Additionally hole sizes vary widely causing corresponding wide variations in the amplitude of the signal indicative of the presence of holes.
As well, prerecorded material, slush as sector marts which the read I system must also detect, cause drops in re1ectlon far less than caused by burned holes. This necessitates a variation in the threshold level depending on the type of material being read.
Moreover, other system variables negate the use of threshold detection. Among these are reflectivity variations from disk to disk and across a single disk, variations in laser power levels, I
optical efficiency, sense diode coupling errors, circuit toter-antes, etc. For these reasons, an alternative method of detection of holes is desirable. The method employed by the preferred embodiment is that of differential detection.
The signal from the read detectors is input to the AGO
lo shown in Figure 1, which outputs the amplified and limited signal on Read 1 and Read 2 outputs. The Read 1 output is input to a phase lock loop 112 which tracks a prerecorded clock insert-bed in the optical disk, or if the code is self-clocking, the lo clock information present in the code. The phase lock loop out-puts several clock signals, the most important of which is a 2C~
clock at a frequency twice that of the prerecorded clock. This 2CK is input to a Timing Chip I and to a TOWN counter 46. TOO
is the name of the fixed block code of the preferred embodiment.
The TOWN Counter's essential purpose is to count the number of symbol positions to generate a symbol position address. The Hung-lion of the Timing Chip I will be discussed nfra.
The Read 2 signal is input to four grated sample and hold ceils 114, two cells each for the respective even and odd symbol position of the TOWN code. The sapling of the cells is con-trolled by Timing Chip 44. The outputs of the cells are input to two comparators 116, an even and an odd comparator respectively, which determine Nash of the two sample and hold cells has the highest hole associated signal power. The comparator OUtplltS are fed back to Timing Chip 44 and to a transition detector circuit 118. The transition detectors detect a change in the state of the comparators l16 outputs and signal that change to a pair of binary registers 120, one (84~ Figure 4) for the even and one (86, Figure I for the odd symbol positions, which record the address of the change. The address of the change as represented by the count on tune TAO Counter 46 is divided by two ignoring the remainder. The binary registers are copied into one of two four-bit output registers 88, I Figure 4, at the end of a symbol. After two symbols have been recorded in the output registers, the optical disk recorder reads the eight binary bits of data out of the registers along a data bus 96.
The system also detects the presence of sector marks and this information is supplied to a sync register 122 which with decoder 124 decodes the location of the sector mark and initial-ides a TOWN counter 46 and a nibble counter 126, which continues to count up by one each symbol until the next sector mark. The lowest order bit 128 of this nibble counter, nibble count 0, is provided to clock the output registers 88 and 90, as will be disk cussed infer.
The present invention pertains to an optical recording system which writes data on an optical disk in fixed-block format wherein binary data is encoded into a symbol having a predator-mined number of positions in which a predetermined number of holes are recorded. queue preferred embodiment uses a so-called loon code which has eight positions in which holes may be written and one position in which no holes are written. rho latter position is normally reserved at the end of the symbol. The TOWN code is further constrained to have one hole written at an even position and one hole written at an odd position. Only two holes are written in the symbol.
Figure 2 shows the TOWN code. It has nine positions numbered in the Figure from zero to eight. The ninth position, number eight, is the one constrained to never have a hole recorded in it. The other eight positions have one hole in an even posit lion and one hole in an odd position. The code is shown in the figure and the corresponding binary bit values are shown in the table to the right. Each symbol of the TOWN code encodes four bits of information.
The code is recorded on the media in such a manner that four and one half clock periods, To span the symbol. Rerun to Figure pa, the prerecorded clock is illustrated as the sinus swaddle line 10. It is from this signal that the phase lock loop generates the 2CK signal shown in Figure 3b.
The fall of 2CK denotes the beginning of a symbol post-lion and the rise of 2CK denotes the center of a symbol position.
There are exactly nine 2CK clocks in a symbol.
Figure 3c corresponds to the Taco bit out of the TOWN
Counter 46. It undergoes eight transitions during a symbol and the transitions occur at the center of a given symbol position.
The numbers in the figure correspond to the number of the symbol position in which the next transition occurs. There is no trays-it ion in symbol position nine primarily because no hole will ever be recognized in this position even if a hole is somehow recorded therein.
'I 1 owes are preferably written at the center of a symbol position To write a hole, the optical recording device generates a write pulse from a laser beam of approximately 60 nanoseconds in length. Tune symbol position length or the length of time for a symbol position to pass past a fixed location at typical operating speeds of the optical recording system of the preferred embodiment is 180 nanoseconds. Roy hole burned in-to the optical recording medium by such a write pulse is typically such larger than 60 nanoseconds in length and may be larger than -the 180 nanoseconds length of a symbol position.
Figure pa shows the inverse of the power of the no-Elected laser beam for two typical symbols on the optical record-in medium. The absence of reflection caused by the presence of a hole is shown as a positive signal, while the presence of reflect-ion is indicated by a negative sic3nal. The vertical dashed lines in the figure represent the boundaries at the edges of the symbols.
Again referring to figure pa, the optical recording surface reflection indicates the presence of holes at the center of symbol positions numbers l and 4 of the first symbol. The holes do not reflect the laser beam and the inverse of the signal detected by apparatus detecting the reflected beam will generate a high signal at 14 and 16 in the figure. As can be seen by inspect lion of the figure, the hole associated power 20 of a hole written at symbol position 1 will be present to a significant degree at symbol position 2.
The second positive going pulse in figure pa represents a second hole written in the symbol at the center of symbol post-lion 4. Here again, the line 28 represents the hole associated signal power which is received by the read system and detects the hole under normal reading conditions.
Assuming a defect in the media or perhaps a defect in the writing system, a hole nay not be formed in the media. When the position is "read", the hole associated power of the read signal, such as for the first hole in the Figure pa, then does not I follow line 20 but instead follows the line 10 which corresponds to the signal of the prerecorded clock.
The second symbol shows holes written at symbol post-lions 6 and 7. Note that the signal power from -the two holes significantly overlap and the signal merges into one large bell-shaped curve.
Figure 4 shows apparatus first for detection of the location of a hole and secondly for generating binary output from the address of the holes for two consecutive symbols.
Referring to the top right-most part of Figure 4, the 2CK clock derived from the phase lock loop 112 is provided as an input to both a Timing Chip 44 and a TON counter 46. TOWN count-or 46 counts once for each cycle of the 2CK with its four-bit count on outputs TACO, TNC1, TNC2, and TNC3, respectively. A
count of 8, TNC3, synchronously (at the next clock) resets the counter to zero due to the inventor 48 feeding TNC3 back into master reset not 50 of the TOWN counter 46. The state of TNCI is shown at Figure on and the state of TNC3 is shown at Figure up.
The timing Chip 44 also outputs an REX signal, which is inverted by inventor 54, to become an REV NOT signal. The signal REV is output once per symbol during the last half period of symbol position 0. See Figure JO. The purpose of REV is to signal the end of a symbol to various registers as will be discussed infer, and also resets other registers.
As can be seen from Figure Ed, the Timing Chip outputs an S-clock ("SUCK") which corresponds directly with the 2CK signal.
SUCK is delayed from 2CK by approximately 22.5 nanoseconds and inverted therefrom as can be seen from relative timing diagram Figure 5.
The Timing Chip I also outputs through register 52 signals So, So, So and So and REV signal Signals So - So are set by the rising edge of SUCK clocking register 52. Signal SIR NOT
resets register 52 and signals So through So and REV. STAR NOT is triggered at the falling edge of SUCK, see Figure 5 where it can be seen that at the fall of the SIR signal, which occurs 22.5 nanoseconds after the fall of the 2CK signal, causes the Timing Chip I to output a signal SUPS (Fig. 5), which when coupled with an Reel signal from register 52 (Figure Ed) through RAND gate 51l generates an STAR NOT signal (see Figure ye) which resets register 52 and thereby resets signal So through So as can be seen from Figure of, which shows the resetting of the So signal. It also resets REM, which in turn resets STAR NOT. Thus, the So signal is normally "on" for a period of approximately JO nanoseconds from a point approximately 30 nanoseconds after the fall of the 2CK sign net to approximately 30 nanoseconds aster its rise.
I
- 1'1 -Referring to the upper leftmost of Figure I the sign nets So to So control corresponding FRET gates 58 between the Read
Prior art optical recorder systems using fixed block code formatted data read the data by first delaying the data so that the signal values of all symbol positions were present at a series of comparators at the same instant of time, at Lucia time the comparators were operated to determine the two locations (assuming a code having two holes per symbol) within the symbol which had the highest signal values for the hole associated power of the reflected laser beam. (Hole associated power may be taken to mean the inverse of the power of the reflected laser beam.) These were the locations of the holes. Thereafter, the hole toga-lions were converted from the fixed hock code to binary using somewhat complex logic. The entire apparatus was somewhat comply-acted, expensive in the use of delay lines and comparators, and prone to failure due to loss of signal in the various delay lines.
SUMMARY OF THE INVENTION
The invention comprises breaking the apparatus which decodes the hole position of the fixed block codes separately for the even and odd symbol positions. For each, two sample and hold cells are provided, and these are input to one comparator. One sample and hold cell in each respective comparator is respectively clocked at the first even and the first odd symbol positions. The other is clocked at the next even or odd position. If the second is higher, the output of the comparator changes. If it is not, ,, the output of the comparator does not change. In either case, the timing circuit knows which cell has the highest valued signal in it and clocks the other the one with the lower valued signal, at the next even or odd symbol position. This process continues until all symbol positions have been sampled, except for the ninth, which is always empty. If a hole is present in the symbol in either the even or odd positions, the last time the comparator for the even or odd sample and hold will change is at the symbol.
Every time the state of the respective even and odd comparators changes, a transition detector connected to the respective compare atop, signals the change by generating an even or odd pulse. This even or odd pulse causes the output of a symbol position counter to be input into an even or odd register. The even and odd ad-dresses of the holes in the symbol together form the four binary bits of the encoded information. Two consecutive symbols are decoded, and the eight bits of binary data encoded by the two symbols are formed into eight binary bits and output on a data bus.
Thus, in accordance with one broad aspect ox the invent lion, there is provided apparatus for differential decoding of fixed-block encoded data comprising signals read from an apparatus having data recorded thereon in a fixed-block code, comprising TOWN counter means for counting the symbol positions within a symbol, including means for initializing said ONE counter after reaching the count ox the last symbol position of the symbol; a pair of even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon yin a Eixed-blocked format comprising symbols having a predetermined number of symbol positions in which Hess may be written; a pair of odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format; means no-sponsive to said TOWN counter means for triggering a first of said even pair of sample and hold Silas at the first even symbol post-lion of a symbol; means responsive to said TOWN counter means for triggering a second of said even pair of sample and hold cells at the second even symbol position of a symbol even comparator means for comparing the first even sample and hold cell valve with the second even sample and hold cell value and for generating an even comparator output indicative of the results of the comparison;
means responsive to said TOWN counter means and to said even come portray means for retaining the value it the even sample and hold cell having the higher value and for triggering the other even sample and hold cell at the next even symbol position and for repeating said retention end said triggering of the other even sample and hold cell at the occurrence of every even symbol post-lion for which the fixed-block code may contain a hole; means responsive to said TOWN counter means for triggering a first of said odd pair of sample and hold cells at the first odd symbol position of a symbol; means responsive to said TOWN counter means for triggering a second of said odd pair of sample and hold cells at the second odd symbol position of a symbol; odd comparator means for comparing the first odd sample and hold cell value with the second odd sample and hold cell value and for generating an odd comparator output indicative of the results of the comparison;
means responsive to said TOWN counter means and to said odd come portray means for retaining the value in the odd sample and hold cell having the higher value and for triggering the other odd sample and hold cell at the next odd symbol position and for repeating said retention and said triggering of the other odd sample and hold cell at the occurrence of every odd symbol post-lion for which the fixed-block code may contain data; even binary register means responsive to a change in the state of said even comparator output for recording the count of said TOWN counter divided by two, ignoring fractions; old binary resister means responsive to a change in the state of said odd comparator output for recording the count of said ONE counter divided by two, Gino-ring fractions; output register means for loading the contents of said even and said odd binary register means into at least one output register at the end of a symbol.
In accordance with another broad aspect ox the invention there is provided apparatus for differential decoding of fixed block encoded data comprising signals read from an apparatus having data recorded thereon in a fi~ed-block code, comprising symbol counter means for counting the symbol positions within a symbol, including means for initializing said symbol courter after reaching the count of the last symbol position of the symbol; n even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed bloc format comprisirlg symbols having a predetermined number of symbol positions in which holes may be written and a predetermined number, 2 on - 1), of holes, half written in even positions and half written in odd positions; n odd sample and hold cells responsive to said read signals from said apparatus reading data from sated medium having data recorded thereon in a fixed block format; means responsive to said symbol counter means for triggering a first of said n even sample and hold cells at the first even symbol position of a symbol; means responsive to said symbol counter means for triggering successive others of said n even sample and hold cells at successive even symbol positions of lo a symbol, the number of successive cells triggered corresponding to the number, n - 1, of holes which may be written in even post-lions; n (n - lo even comparator means err comparing each even sample and hold cell value with each of the other even sample and hold cell values; means responsive to said symbol counter means and to said n (n - 1)~2 even comparator means for retaining the values in the even sample and hold cells having the higher values and for triggering the even sample and hold cell having the lowest value at the next even symbol position and for repeating said retention and said triggering of the even sample and hold cell having the lowest value at the occurrence of every even symbol position for which the fixed-block code may contain a hole; means responsive to said symbol counter means for triggering a eeriest of said n odd sample and hold cells at the first odd symbol position ox a symbol; means responsive to said symbol counter means for triggering successive others of said n odd sample and hold cells at successive odd symbol positions of a symbol, the number of cells triggered corresponding to the number, n - l, of holes which may be written in odd positions; n (n - 1)/2 odd comparator means for comparing each odd sample and hold cell value with each of the other odd sample and hold cell values; and means responsive to said symbol counter means and to said n (n - 1)/2 odd compare atop means for retaining the values in the odd sample and held cells having the higher values and for triggering the odd sample and hold cell having the lowest value at the next odd symbol post-lion and for repeating said retention and said triggering of the odd sample and hold cell having the lowest value at the occurrence of every odd symbol position for which the Eixed-block code may contain a hole.
BRIEF DESCRIPTION OF THE DUNKS
Figure 1 is a block diagram of the read channel of the present invention.
Figure 2 shows the TOWN code and its corresponding bin-cry equivalent.
Figure 3 is a timing diagram of various signals gene-rated by the read channel of the present invention.
Figure 4 it a schematic circuit diagram of the critical circuits of the present invention.
Figure 5, on the second sheet of drawings, is a timing diagram showing the fine timing differences between several of the signals of Figure 3.
Figure 6 (on two sheets) is a blackjack diagram of a vane-lion of the invention for a 4/15 code.
INSCRIPTION OF TIE Proofread EI~IE3ODIMENT
Figure 1 shows a block diagram of the read channel according to the present invention. The optical recorder reading the information from the optical disk does so conventionally by means of a laser operated at read power. The beam reflects from the disk, and the drop in reflection normally indicates the pros-once of a hole. Because reflected spot density distributions have a Gaussian shape, the hole associated power of the reflected beam (the hole associated power means the inverse of the reflected power from the disk) spreads a significant distance beyond the boundaries OX the holes themselves. Indeed, the hole power pro-sent at the center of the next possible position of a hole in closely spaced systems may be significant. Therefore, one cannot rely on threshold detectors to detect the presence of a hole, because the threshold may be reached due to a hole at an earlier or later position, or a combination of the two. Additionally hole sizes vary widely causing corresponding wide variations in the amplitude of the signal indicative of the presence of holes.
As well, prerecorded material, slush as sector marts which the read I system must also detect, cause drops in re1ectlon far less than caused by burned holes. This necessitates a variation in the threshold level depending on the type of material being read.
Moreover, other system variables negate the use of threshold detection. Among these are reflectivity variations from disk to disk and across a single disk, variations in laser power levels, I
optical efficiency, sense diode coupling errors, circuit toter-antes, etc. For these reasons, an alternative method of detection of holes is desirable. The method employed by the preferred embodiment is that of differential detection.
The signal from the read detectors is input to the AGO
lo shown in Figure 1, which outputs the amplified and limited signal on Read 1 and Read 2 outputs. The Read 1 output is input to a phase lock loop 112 which tracks a prerecorded clock insert-bed in the optical disk, or if the code is self-clocking, the lo clock information present in the code. The phase lock loop out-puts several clock signals, the most important of which is a 2C~
clock at a frequency twice that of the prerecorded clock. This 2CK is input to a Timing Chip I and to a TOWN counter 46. TOO
is the name of the fixed block code of the preferred embodiment.
The TOWN Counter's essential purpose is to count the number of symbol positions to generate a symbol position address. The Hung-lion of the Timing Chip I will be discussed nfra.
The Read 2 signal is input to four grated sample and hold ceils 114, two cells each for the respective even and odd symbol position of the TOWN code. The sapling of the cells is con-trolled by Timing Chip 44. The outputs of the cells are input to two comparators 116, an even and an odd comparator respectively, which determine Nash of the two sample and hold cells has the highest hole associated signal power. The comparator OUtplltS are fed back to Timing Chip 44 and to a transition detector circuit 118. The transition detectors detect a change in the state of the comparators l16 outputs and signal that change to a pair of binary registers 120, one (84~ Figure 4) for the even and one (86, Figure I for the odd symbol positions, which record the address of the change. The address of the change as represented by the count on tune TAO Counter 46 is divided by two ignoring the remainder. The binary registers are copied into one of two four-bit output registers 88, I Figure 4, at the end of a symbol. After two symbols have been recorded in the output registers, the optical disk recorder reads the eight binary bits of data out of the registers along a data bus 96.
The system also detects the presence of sector marks and this information is supplied to a sync register 122 which with decoder 124 decodes the location of the sector mark and initial-ides a TOWN counter 46 and a nibble counter 126, which continues to count up by one each symbol until the next sector mark. The lowest order bit 128 of this nibble counter, nibble count 0, is provided to clock the output registers 88 and 90, as will be disk cussed infer.
The present invention pertains to an optical recording system which writes data on an optical disk in fixed-block format wherein binary data is encoded into a symbol having a predator-mined number of positions in which a predetermined number of holes are recorded. queue preferred embodiment uses a so-called loon code which has eight positions in which holes may be written and one position in which no holes are written. rho latter position is normally reserved at the end of the symbol. The TOWN code is further constrained to have one hole written at an even position and one hole written at an odd position. Only two holes are written in the symbol.
Figure 2 shows the TOWN code. It has nine positions numbered in the Figure from zero to eight. The ninth position, number eight, is the one constrained to never have a hole recorded in it. The other eight positions have one hole in an even posit lion and one hole in an odd position. The code is shown in the figure and the corresponding binary bit values are shown in the table to the right. Each symbol of the TOWN code encodes four bits of information.
The code is recorded on the media in such a manner that four and one half clock periods, To span the symbol. Rerun to Figure pa, the prerecorded clock is illustrated as the sinus swaddle line 10. It is from this signal that the phase lock loop generates the 2CK signal shown in Figure 3b.
The fall of 2CK denotes the beginning of a symbol post-lion and the rise of 2CK denotes the center of a symbol position.
There are exactly nine 2CK clocks in a symbol.
Figure 3c corresponds to the Taco bit out of the TOWN
Counter 46. It undergoes eight transitions during a symbol and the transitions occur at the center of a given symbol position.
The numbers in the figure correspond to the number of the symbol position in which the next transition occurs. There is no trays-it ion in symbol position nine primarily because no hole will ever be recognized in this position even if a hole is somehow recorded therein.
'I 1 owes are preferably written at the center of a symbol position To write a hole, the optical recording device generates a write pulse from a laser beam of approximately 60 nanoseconds in length. Tune symbol position length or the length of time for a symbol position to pass past a fixed location at typical operating speeds of the optical recording system of the preferred embodiment is 180 nanoseconds. Roy hole burned in-to the optical recording medium by such a write pulse is typically such larger than 60 nanoseconds in length and may be larger than -the 180 nanoseconds length of a symbol position.
Figure pa shows the inverse of the power of the no-Elected laser beam for two typical symbols on the optical record-in medium. The absence of reflection caused by the presence of a hole is shown as a positive signal, while the presence of reflect-ion is indicated by a negative sic3nal. The vertical dashed lines in the figure represent the boundaries at the edges of the symbols.
Again referring to figure pa, the optical recording surface reflection indicates the presence of holes at the center of symbol positions numbers l and 4 of the first symbol. The holes do not reflect the laser beam and the inverse of the signal detected by apparatus detecting the reflected beam will generate a high signal at 14 and 16 in the figure. As can be seen by inspect lion of the figure, the hole associated power 20 of a hole written at symbol position 1 will be present to a significant degree at symbol position 2.
The second positive going pulse in figure pa represents a second hole written in the symbol at the center of symbol post-lion 4. Here again, the line 28 represents the hole associated signal power which is received by the read system and detects the hole under normal reading conditions.
Assuming a defect in the media or perhaps a defect in the writing system, a hole nay not be formed in the media. When the position is "read", the hole associated power of the read signal, such as for the first hole in the Figure pa, then does not I follow line 20 but instead follows the line 10 which corresponds to the signal of the prerecorded clock.
The second symbol shows holes written at symbol post-lions 6 and 7. Note that the signal power from -the two holes significantly overlap and the signal merges into one large bell-shaped curve.
Figure 4 shows apparatus first for detection of the location of a hole and secondly for generating binary output from the address of the holes for two consecutive symbols.
Referring to the top right-most part of Figure 4, the 2CK clock derived from the phase lock loop 112 is provided as an input to both a Timing Chip 44 and a TON counter 46. TOWN count-or 46 counts once for each cycle of the 2CK with its four-bit count on outputs TACO, TNC1, TNC2, and TNC3, respectively. A
count of 8, TNC3, synchronously (at the next clock) resets the counter to zero due to the inventor 48 feeding TNC3 back into master reset not 50 of the TOWN counter 46. The state of TNCI is shown at Figure on and the state of TNC3 is shown at Figure up.
The timing Chip 44 also outputs an REX signal, which is inverted by inventor 54, to become an REV NOT signal. The signal REV is output once per symbol during the last half period of symbol position 0. See Figure JO. The purpose of REV is to signal the end of a symbol to various registers as will be discussed infer, and also resets other registers.
As can be seen from Figure Ed, the Timing Chip outputs an S-clock ("SUCK") which corresponds directly with the 2CK signal.
SUCK is delayed from 2CK by approximately 22.5 nanoseconds and inverted therefrom as can be seen from relative timing diagram Figure 5.
The Timing Chip I also outputs through register 52 signals So, So, So and So and REV signal Signals So - So are set by the rising edge of SUCK clocking register 52. Signal SIR NOT
resets register 52 and signals So through So and REV. STAR NOT is triggered at the falling edge of SUCK, see Figure 5 where it can be seen that at the fall of the SIR signal, which occurs 22.5 nanoseconds after the fall of the 2CK signal, causes the Timing Chip I to output a signal SUPS (Fig. 5), which when coupled with an Reel signal from register 52 (Figure Ed) through RAND gate 51l generates an STAR NOT signal (see Figure ye) which resets register 52 and thereby resets signal So through So as can be seen from Figure of, which shows the resetting of the So signal. It also resets REM, which in turn resets STAR NOT. Thus, the So signal is normally "on" for a period of approximately JO nanoseconds from a point approximately 30 nanoseconds after the fall of the 2CK sign net to approximately 30 nanoseconds aster its rise.
I
- 1'1 -Referring to the upper leftmost of Figure I the sign nets So to So control corresponding FRET gates 58 between the Read
2 input 56 and respective grounded capacitors 60. The combination of a gate and a capacitor forms a sample and hold cell as is known to the art. The respective sample and hold cells will henceforth be referred by the respective signals controlling their gazes, So, So, So and So. The signal input on read 2 line 56 corresponds to the hole associated power of the reflected laser beam as discussed above. Each of the capacitors 60 is also connected two each to respective comparators I and 64. Comparator 62 operates on the odd positions of a TOWN symbol and comparator 64 operates on the even positions. Comparator 62 compares the signal value on the So sample hold with the signal value then present on the So sample and hold, while the comparator 64 compares the signal value in the So sample hold with signal value on the So sample and hold. The comparators output the results of the comparison on outputs 66 and 68, respectively, which are provided as respective inputs 70 and 72 to the Timing Chip 44 through flip flops 74 and 75.
During the first symbol position of a symbol, symbol position 0, an even position, sample and hold cell So is turned on to sample the signal at the first even cell. During the first odd position, position number 1, sample and hold So is turned on to sample the signal at the first odd cell. The signals present on the read line 56 during these symbol positions are copied into the corresponding capacitors 60 of the sample and hold cells. At the next even position, sample and hold cell So is triggered to record the signal level at symbol position number 2, and at the t.~S`1~ Lo next odd position, sample and hold cell So is triggered to record the signal level at symbol position number 3. Comparator 62 coy pares the value of sample and hold cells So and So, the odd sample and holds, and comparator 64 compares the value of sample and hold cells So and So, the even sample and hold cells. If, for example, the results of this former comparison indicate that So sample and hold value exceeds the So sample and hold value, the output 66 of the comparator 62 will be low. output 68 will similarly be low if So exceeds So. '['he Timing Chip 44 then saves the higher of the two values, So (So). It does this at the next occurrence of an odd (or even) cell by triggering the other sample and hold So (So), which then holds the lowest valued signal of the two. If again the So (So) sample and hold contains the highest value at the next occurrence of an odd (even) symbol position, the So (So) sample and hold is again triggered. This process continues throughout the symbol with the highest valued sample and hold cell retained and compared with the next sampled value. At the end of the symbol, one of the sample and holds of each comparator will contain the highest valued signal, and this signal corresponds to signals generated by the holes within the symbol, if there were holes recorded there.
Referring to the example shown in Figure pa, when the So sample and hold cell is triggered at position 1 in the first symbol, it samples the signal caused by the first hole 20 shown in the example. Lowe sample and hold samples a read signal at approx-irately the level indicated at point 14 on Figure pa. Sample and hold cell So is next triggered at position 3 and samples a signal approximately the level indicated at point 22 in inure pa. As can be seen by inspection of Figure pa, the signal level at point 14 is higher than the signal at point 22. Therefore, the I
sample and hold and is retained. At the next occurrence of an odd symbol, at symbol position 5, the Tiring Chip 44 determines that So now contains the nighest signal and triggers the So sample and hold. By inspection of Figure pa, it can be seen that -the signal level at this point 24 is higher than the reference clock signal but lower than the peak value 14 of the signal at position l.
Thus, So continues to contain the higher of the two values.
riming whip 44 triggers So at the last odd position, position number 7. This value it again less than the value in sample and hold cell Sly (The sequence of triggering of So and So just described is shown at Figures oh and I.) If at any time the two signal levels present in the respective sample and holds are about equal which may occur when the holes are recorded later in the symbol, the state of the come portrays 62 or 64 is indeterminate. Either one of the two is retained for the next symbol. Issue feature is illustrated by the dashed lines shown in Figures of and 3g which show the triggering of the So and So sample and hold cells.
The Figures 3 to I also show the triggering of the sample and hold cells So through So for the second exemplary sum-boy shown in Figure pa.
Timing chip 44 recognizes the winding of a new higher valued signal by the change in the outputs of the comparators 64 or 62 as can be seen by inspection of Figures 3j and ok, which I
show the state of the outputs of the flip flops 75 and 74 which are coupled to the even and odd comparators respectively. Note that REV NOT initializes registers 74 and 75 at the beginning of a symbol.
The outputs of the comparators 62 and 64 are provided as inputs to respective flip flops 74 and 75, whose outputs are in turn provided to register 76 and as one input to exclusive-OR
gates 78 end 80. The outputs of register 75 are provided as the other inputs to excluslve-OR gate 80. Flip flops 74 and 75 are lo clocked by OR gates 71 and 73 respectively, which form the logical OR of the signals So and Sir and So and So respectively. This method of clocking these flip flops assures that the outputs of the comparators are sampled after the comparators have changed state. Flip flops 74 arc 75 are clocked for an even position at the next odd position and for an odd position at the next even position. Further the state of these flip flops remains steady for a predetermined period, which cannot be said for the state of the comparators 62 and 64.
Register 76 is clocked by the inversion of SUCK approxi-mutely 90 nanoseconds after the clocking of flip flops 74 and 75.
The exclusive-OR gates I and 80 compare the outputs of the come portrays 62 and 64 from one even or odd symbol position to another and generate a pulse of approximately 90 nanoseconds duration if the outputs change. Exclusive-OR gate 78 is indirectly connected to the output 66 of comparator 62. Figure 31 shows the pulse LO
out of exclusive-OR gate 78 indicative of the changes in the net-alive signal levels in the So and So sample and holds discussed I I
heretofore. Exclusive OR gate 80 is indirectly connected to the output 68 of the comparator I Figure em shows the pulse out of exclusive-OR gate 80 indicative of the changes in the relative signal level of sample and hold cells So and So discussed above.
The load odd and load even pulses LO and LYE occur only when a new "higher" signal level has been recognized by the respective comparators.
Referring again to figure 2, it can be seen from inspect lion that there is a systematic correspondence between the toga-lion of the even position symbol and the first two binary bits and likewise a systematic correspondence between the location of the odd symbol and the second two binary bits. The correspondence is that the symbol position address divided by 2, ignoring fractions, directly converts the symbol location into the binary equivalent for the two corresponding bits.
Referring again to Figure 4, the symbol position address divided by two, ignoring fractions, is just the state of the TNC1 and TNC2 outputs from TOWN counter 4Ç. These outputs are -there-fore provided to an address register 82. The state of these out-puts changes every other transition of TACO. Therefore, TNCOclocks the address register 82. The outputs of the address aegis-ton 82 are provided to even and odd binary registers 84 and 86 respectively.
These registers 84 and 86 are in turn clocked by LYE and LO respectively. These latter signals occur, as noted above, each time the state of the comparators 64 and I change; however, the last time they change corresponds to the location of the holes, as the holes generate the highest hole associated signal power. Therefore, these even and odd binary registers are docked the last time yin the symbol at the location of the respective even and odd holes, and the then current address of the respective holes (divided by 2, ignoring the remainc3er) then present in add-revs register 82 is copied into binary registers 84 and 86.
As the combination of these two binary registers I and 86 yields the correct four-bit decoding for the symbol, the out-puts of these two registers are provided to a first symbol four-bit register 88, which contains the four bits decoded from the first symbol of a pair of symbols which encode an eight bit byte of data, and also to a second symbol four-bit register 90, which contains the four binary bits decoded from the second of a two-symbol pair The first symbol four bit register 88 is clocked by the nibble count O ~128) signal from the nibble counter 126 coup-led to sync mark decoder 124, and the second symbol four bit rouge-suer 90 is clocked by the inversion 130 of nibble count 00 As mentioned above, the nibble counter 126 counts the number of symbols in a sector and nibble count O (128) undergoes a positive transition every other symbol.
At the end owe a symbol r the binary registers are reset by the COREY NOT signal. At the end of two symbols, the data for one byte is read out on data bus 96 to the optical recording system, which issues an aeknowledye signal I which in turn no-sets the two four bit registers Jo end 90.
Lowe above apparatus was c'iescribecl in conjunction with a 'Rowley code. Other codes having a null in the frequency spectrum are compatible with a prerecorded clock. One such code is a so-called 4/15 code in which there are 4 holes, two each in the even positions and two each in the odd positions. One position is loft empty at the boundary. With this code, means must be provided to detect the highest signal for both the even and the odd positions, and the second highest. To do this, one merely has LO have three sample and holds instead of two, as well as three comparators.
One sample and hold would hold the highest value, the second would hold the next highest and the third would hold the new sample to be compared with the other two. The results of the comparison would indicate whether we had a new highest or a new second highest value. These results could be latched and fed back through to the Timing Chip, as well as to the address decoder which would convert the addresses of the holes into binary.
Apparatus for decoding the 4/15 code is shown in Figure 6. The figure shows a block diagram of the odd sample and hotels and corresponding decoding apparatus. Identical apparatus for the even positions is not shown. The three odd sample and holds So, So and So are shown. So is triggered at the first odd position, So the next odd and So at the third odd position. The outputs of the sample and holds are input to three comparators C13, C15 and C35 which compare the outputs of the corresponding sample and holds. These are latched as described above in a latch 74, now having 3 inputs and outputs r and clocked by the occurrence of an even symbol position with a signal I from Timing Chip 44 (or an OR gate 71 as above described The outputs of the latches are fed back to the Timing Chip 44 as before and in turn fed into of bidirectional one shots or transition detectors I which issue a pulse if a change in the latch output to which it is connected is detected. In response to the three latched feedbacks, -the Timing Chip may now determine the relative magnitude of the signals in the three sample and holds and trigger the one with the lowest value at the next odd position. This sequence continues until the last odd position in which a hole may be recorded, the lowest valued sample and hold being the one next triggered.
In response to pulse from the one-shots 77, the binary registers 84 load the address from -the position counter 46, the lowest order bit clocking the next three higher bits. From the final state of the latched comparators 7 the Timing Chip knows which one has the lowest value, the next highest and the highest value. This information is provided to a multiplexer I via select lines 50 and 51. The multiplexer places on its two sets of outputs the addresses contained in the two selected binary aegis-lens. The multiplexed outputs are provided to a conversion table 93, which converts the addresses of the four holes into binary and provides the results to a register 99, which is clocked by a byte pulse once per byte. Because the 4/15 code encodes eight bits, this byte pulse occurs every symbol.
The method of the preferred embodiment is intended to be general with respect to the class of codes having a null in the frequency spectrum at the frequency of the prerecorded clock.
These codes may have any number of holes in the odd and even post-Chihuahuas. There must be a sample and hold cell for each such hole, even and odd, plus one. The extra one is the one triggered at the next even or odd position. There are a sufficient number of come portrays to determine which is the lowest, next lowest, etc..
This requires -that each of the sample and holds be interconnected with a comparator to each of the other sample and holds. This requires n (n - 1) /2 comparators, where n is the number of sample and hold cells. Each comparator must be latched and fed back to the riming Chip 44 and also fed to transition detectors which detect a change in the latched output. The transition detectors issue a one shot to the binary registers, which load the address of the "Hillel by loading the count of a position counter 4G as clocked by the lowest order bit of the count. 'Lowe final state of the latched comparators reveals those binary registers containing addresses of holes as opposed to spurious information, and these addresses can be decoded by a decoder into binary.
The enumeration of the elements of the preferred embody-mint are not to be taken as a limitation on the scope of the appended claims.
During the first symbol position of a symbol, symbol position 0, an even position, sample and hold cell So is turned on to sample the signal at the first even cell. During the first odd position, position number 1, sample and hold So is turned on to sample the signal at the first odd cell. The signals present on the read line 56 during these symbol positions are copied into the corresponding capacitors 60 of the sample and hold cells. At the next even position, sample and hold cell So is triggered to record the signal level at symbol position number 2, and at the t.~S`1~ Lo next odd position, sample and hold cell So is triggered to record the signal level at symbol position number 3. Comparator 62 coy pares the value of sample and hold cells So and So, the odd sample and holds, and comparator 64 compares the value of sample and hold cells So and So, the even sample and hold cells. If, for example, the results of this former comparison indicate that So sample and hold value exceeds the So sample and hold value, the output 66 of the comparator 62 will be low. output 68 will similarly be low if So exceeds So. '['he Timing Chip 44 then saves the higher of the two values, So (So). It does this at the next occurrence of an odd (or even) cell by triggering the other sample and hold So (So), which then holds the lowest valued signal of the two. If again the So (So) sample and hold contains the highest value at the next occurrence of an odd (even) symbol position, the So (So) sample and hold is again triggered. This process continues throughout the symbol with the highest valued sample and hold cell retained and compared with the next sampled value. At the end of the symbol, one of the sample and holds of each comparator will contain the highest valued signal, and this signal corresponds to signals generated by the holes within the symbol, if there were holes recorded there.
Referring to the example shown in Figure pa, when the So sample and hold cell is triggered at position 1 in the first symbol, it samples the signal caused by the first hole 20 shown in the example. Lowe sample and hold samples a read signal at approx-irately the level indicated at point 14 on Figure pa. Sample and hold cell So is next triggered at position 3 and samples a signal approximately the level indicated at point 22 in inure pa. As can be seen by inspection of Figure pa, the signal level at point 14 is higher than the signal at point 22. Therefore, the I
sample and hold and is retained. At the next occurrence of an odd symbol, at symbol position 5, the Tiring Chip 44 determines that So now contains the nighest signal and triggers the So sample and hold. By inspection of Figure pa, it can be seen that -the signal level at this point 24 is higher than the reference clock signal but lower than the peak value 14 of the signal at position l.
Thus, So continues to contain the higher of the two values.
riming whip 44 triggers So at the last odd position, position number 7. This value it again less than the value in sample and hold cell Sly (The sequence of triggering of So and So just described is shown at Figures oh and I.) If at any time the two signal levels present in the respective sample and holds are about equal which may occur when the holes are recorded later in the symbol, the state of the come portrays 62 or 64 is indeterminate. Either one of the two is retained for the next symbol. Issue feature is illustrated by the dashed lines shown in Figures of and 3g which show the triggering of the So and So sample and hold cells.
The Figures 3 to I also show the triggering of the sample and hold cells So through So for the second exemplary sum-boy shown in Figure pa.
Timing chip 44 recognizes the winding of a new higher valued signal by the change in the outputs of the comparators 64 or 62 as can be seen by inspection of Figures 3j and ok, which I
show the state of the outputs of the flip flops 75 and 74 which are coupled to the even and odd comparators respectively. Note that REV NOT initializes registers 74 and 75 at the beginning of a symbol.
The outputs of the comparators 62 and 64 are provided as inputs to respective flip flops 74 and 75, whose outputs are in turn provided to register 76 and as one input to exclusive-OR
gates 78 end 80. The outputs of register 75 are provided as the other inputs to excluslve-OR gate 80. Flip flops 74 and 75 are lo clocked by OR gates 71 and 73 respectively, which form the logical OR of the signals So and Sir and So and So respectively. This method of clocking these flip flops assures that the outputs of the comparators are sampled after the comparators have changed state. Flip flops 74 arc 75 are clocked for an even position at the next odd position and for an odd position at the next even position. Further the state of these flip flops remains steady for a predetermined period, which cannot be said for the state of the comparators 62 and 64.
Register 76 is clocked by the inversion of SUCK approxi-mutely 90 nanoseconds after the clocking of flip flops 74 and 75.
The exclusive-OR gates I and 80 compare the outputs of the come portrays 62 and 64 from one even or odd symbol position to another and generate a pulse of approximately 90 nanoseconds duration if the outputs change. Exclusive-OR gate 78 is indirectly connected to the output 66 of comparator 62. Figure 31 shows the pulse LO
out of exclusive-OR gate 78 indicative of the changes in the net-alive signal levels in the So and So sample and holds discussed I I
heretofore. Exclusive OR gate 80 is indirectly connected to the output 68 of the comparator I Figure em shows the pulse out of exclusive-OR gate 80 indicative of the changes in the relative signal level of sample and hold cells So and So discussed above.
The load odd and load even pulses LO and LYE occur only when a new "higher" signal level has been recognized by the respective comparators.
Referring again to figure 2, it can be seen from inspect lion that there is a systematic correspondence between the toga-lion of the even position symbol and the first two binary bits and likewise a systematic correspondence between the location of the odd symbol and the second two binary bits. The correspondence is that the symbol position address divided by 2, ignoring fractions, directly converts the symbol location into the binary equivalent for the two corresponding bits.
Referring again to Figure 4, the symbol position address divided by two, ignoring fractions, is just the state of the TNC1 and TNC2 outputs from TOWN counter 4Ç. These outputs are -there-fore provided to an address register 82. The state of these out-puts changes every other transition of TACO. Therefore, TNCOclocks the address register 82. The outputs of the address aegis-ton 82 are provided to even and odd binary registers 84 and 86 respectively.
These registers 84 and 86 are in turn clocked by LYE and LO respectively. These latter signals occur, as noted above, each time the state of the comparators 64 and I change; however, the last time they change corresponds to the location of the holes, as the holes generate the highest hole associated signal power. Therefore, these even and odd binary registers are docked the last time yin the symbol at the location of the respective even and odd holes, and the then current address of the respective holes (divided by 2, ignoring the remainc3er) then present in add-revs register 82 is copied into binary registers 84 and 86.
As the combination of these two binary registers I and 86 yields the correct four-bit decoding for the symbol, the out-puts of these two registers are provided to a first symbol four-bit register 88, which contains the four bits decoded from the first symbol of a pair of symbols which encode an eight bit byte of data, and also to a second symbol four-bit register 90, which contains the four binary bits decoded from the second of a two-symbol pair The first symbol four bit register 88 is clocked by the nibble count O ~128) signal from the nibble counter 126 coup-led to sync mark decoder 124, and the second symbol four bit rouge-suer 90 is clocked by the inversion 130 of nibble count 00 As mentioned above, the nibble counter 126 counts the number of symbols in a sector and nibble count O (128) undergoes a positive transition every other symbol.
At the end owe a symbol r the binary registers are reset by the COREY NOT signal. At the end of two symbols, the data for one byte is read out on data bus 96 to the optical recording system, which issues an aeknowledye signal I which in turn no-sets the two four bit registers Jo end 90.
Lowe above apparatus was c'iescribecl in conjunction with a 'Rowley code. Other codes having a null in the frequency spectrum are compatible with a prerecorded clock. One such code is a so-called 4/15 code in which there are 4 holes, two each in the even positions and two each in the odd positions. One position is loft empty at the boundary. With this code, means must be provided to detect the highest signal for both the even and the odd positions, and the second highest. To do this, one merely has LO have three sample and holds instead of two, as well as three comparators.
One sample and hold would hold the highest value, the second would hold the next highest and the third would hold the new sample to be compared with the other two. The results of the comparison would indicate whether we had a new highest or a new second highest value. These results could be latched and fed back through to the Timing Chip, as well as to the address decoder which would convert the addresses of the holes into binary.
Apparatus for decoding the 4/15 code is shown in Figure 6. The figure shows a block diagram of the odd sample and hotels and corresponding decoding apparatus. Identical apparatus for the even positions is not shown. The three odd sample and holds So, So and So are shown. So is triggered at the first odd position, So the next odd and So at the third odd position. The outputs of the sample and holds are input to three comparators C13, C15 and C35 which compare the outputs of the corresponding sample and holds. These are latched as described above in a latch 74, now having 3 inputs and outputs r and clocked by the occurrence of an even symbol position with a signal I from Timing Chip 44 (or an OR gate 71 as above described The outputs of the latches are fed back to the Timing Chip 44 as before and in turn fed into of bidirectional one shots or transition detectors I which issue a pulse if a change in the latch output to which it is connected is detected. In response to the three latched feedbacks, -the Timing Chip may now determine the relative magnitude of the signals in the three sample and holds and trigger the one with the lowest value at the next odd position. This sequence continues until the last odd position in which a hole may be recorded, the lowest valued sample and hold being the one next triggered.
In response to pulse from the one-shots 77, the binary registers 84 load the address from -the position counter 46, the lowest order bit clocking the next three higher bits. From the final state of the latched comparators 7 the Timing Chip knows which one has the lowest value, the next highest and the highest value. This information is provided to a multiplexer I via select lines 50 and 51. The multiplexer places on its two sets of outputs the addresses contained in the two selected binary aegis-lens. The multiplexed outputs are provided to a conversion table 93, which converts the addresses of the four holes into binary and provides the results to a register 99, which is clocked by a byte pulse once per byte. Because the 4/15 code encodes eight bits, this byte pulse occurs every symbol.
The method of the preferred embodiment is intended to be general with respect to the class of codes having a null in the frequency spectrum at the frequency of the prerecorded clock.
These codes may have any number of holes in the odd and even post-Chihuahuas. There must be a sample and hold cell for each such hole, even and odd, plus one. The extra one is the one triggered at the next even or odd position. There are a sufficient number of come portrays to determine which is the lowest, next lowest, etc..
This requires -that each of the sample and holds be interconnected with a comparator to each of the other sample and holds. This requires n (n - 1) /2 comparators, where n is the number of sample and hold cells. Each comparator must be latched and fed back to the riming Chip 44 and also fed to transition detectors which detect a change in the latched output. The transition detectors issue a one shot to the binary registers, which load the address of the "Hillel by loading the count of a position counter 4G as clocked by the lowest order bit of the count. 'Lowe final state of the latched comparators reveals those binary registers containing addresses of holes as opposed to spurious information, and these addresses can be decoded by a decoder into binary.
The enumeration of the elements of the preferred embody-mint are not to be taken as a limitation on the scope of the appended claims.
Claims (13)
THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS.
1. Apparatus for differential decoding of fixed-block en-coded data comprising signals read from an apparatus having data recorded thereon in a fixed-block code, comprising TOON counter means for counting the symbol positions within a symbol, including means for initializing said TOON count-er after reaching the count of the last symbol position of the symbol;
a pair of even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed-blocked format comprising symbols having a predetermined number of symbol positions in which holes may be written;
a pair of odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format, means responsive to said TOON counter means for trigger-ing a first of said even pair of sample and hold cells at the first even symbol position of a symbol;
means responsive to said TOON counter means for trigger-ing a second of said even pair of sample and hold cells at the second even symbol position of a symbol;
even comparator means for comparing the first even sample and hold cell value with the second even sample and hold cell value and for generating an even comparator output indicative of the results of the comparison;
means responsive to said TOON counter means and to said even comparator means for retaining the value in the even sample and hold cell having the higher value and for triggering the other even sample and hold cell at the next even symbol position and for repeating said retention and said triggering of the other even sample and hold cell at the occurrence of every even symbol posi-tion for which the fixed-block code may contain a hole;
means responsive to said TOON counter means for trigger-ing a first of said odd pair of sample and hold cells at the first odd symbol position of a symbol;
means responsive to said TOON counter means for trigger-ing a second of said odd pair of sample and hold cells at the second odd symbol position of a symbol;
odd comparator means for comparing the first odd sample and hold cell value with the second odd sample and hold cell value and for generating an odd comparator output indicative of the results of the comparison;
means responsive to said TOON counter means and to said odd comparator means for retaining the value in the odd sample and hold cell having the higher value and for triggering the other odd sample and hold cell at the next odd symbol position and for re-peating said retention and said triggering of the other odd sample and hold cell at the occurrence of every odd symbol position for which the fixed-block code may contain data;
even binary register means responsive to a change in the state of said even comparator output for recording the count of said TOON counter divided by two, ignoring fractions;
odd binary register means responsive to a change in the state of said odd comparator output for recording the count of said TOON counter divided by two, ignoring fractions;
output register means for loading the contents of said even and said odd binary register means into at least one output register at the end of a symbol.
a pair of even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed-blocked format comprising symbols having a predetermined number of symbol positions in which holes may be written;
a pair of odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format, means responsive to said TOON counter means for trigger-ing a first of said even pair of sample and hold cells at the first even symbol position of a symbol;
means responsive to said TOON counter means for trigger-ing a second of said even pair of sample and hold cells at the second even symbol position of a symbol;
even comparator means for comparing the first even sample and hold cell value with the second even sample and hold cell value and for generating an even comparator output indicative of the results of the comparison;
means responsive to said TOON counter means and to said even comparator means for retaining the value in the even sample and hold cell having the higher value and for triggering the other even sample and hold cell at the next even symbol position and for repeating said retention and said triggering of the other even sample and hold cell at the occurrence of every even symbol posi-tion for which the fixed-block code may contain a hole;
means responsive to said TOON counter means for trigger-ing a first of said odd pair of sample and hold cells at the first odd symbol position of a symbol;
means responsive to said TOON counter means for trigger-ing a second of said odd pair of sample and hold cells at the second odd symbol position of a symbol;
odd comparator means for comparing the first odd sample and hold cell value with the second odd sample and hold cell value and for generating an odd comparator output indicative of the results of the comparison;
means responsive to said TOON counter means and to said odd comparator means for retaining the value in the odd sample and hold cell having the higher value and for triggering the other odd sample and hold cell at the next odd symbol position and for re-peating said retention and said triggering of the other odd sample and hold cell at the occurrence of every odd symbol position for which the fixed-block code may contain data;
even binary register means responsive to a change in the state of said even comparator output for recording the count of said TOON counter divided by two, ignoring fractions;
odd binary register means responsive to a change in the state of said odd comparator output for recording the count of said TOON counter divided by two, ignoring fractions;
output register means for loading the contents of said even and said odd binary register means into at least one output register at the end of a symbol.
2. The decoding apparatus of claim 1 wherein said output register means includes means for loading the contents of said binary register means into alternate ones of two output registers at alternate symbols.
3. The decoding apparatus of claim 2 further including means for reading the contents of said two output registers every other symbol and for resetting both of said output registers.
4. The decoding apparatus of claim 1 wherein said even comparator means includes an even latch for holding the state of the even comparator means and means for triggering the even latch at every occurrence of the triggering of one of said odd sample and hold cells.
5. The decoding apparatus of claim 1 wherein said odd com-parator means includes an odd latch for holding the state of the odd comparator means and means for triggering the odd latch at every occurrence of the triggering of one of said even sample and hold cells.
6. The decoding apparatus of claim 1 wherein said even and said odd binary register means include address means for latching the binary count of said TOON counter excluding the lowest and highest order bit of the count in response to the lowest order bit of the count.
7. The decoding apparatus of claim wherein said even binary register means includes means for retaining the state of the output of said even latch for one symbol position and means for exclusive-ORing the output of the even latch with the retained even latch output contained in the even retaining means.
8. The decoding apparatus of claim 5 wherein said odd bina-ry register means includes means for retaining the state of the output of said odd latch for one symbol position and means for exclusive-ORing the output of the odd latch with the retained odd latch output contained in the odd retaining means.
9. The decoding apparatus of claim 1 wherein each of said means responsive to said TOON counter for triggering an odd or an even sample and hold cell at any position of a symbol includes timing means for triggering said odd or even sample and hold cell during the first half of the symbol position and terminating the triggering shortly after the first half of the symbol position.
10. Apparatus for differential decoding of fixed-block en-coded data comprising signals read from an apparatus having data recorded thereon in a fixed-block code, comprising symbol counter means for counting the symbol positions within a symbol, including means for initializing said symbol counter after reaching the count of the last symbol position of the symbol;
n even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed-block format comprising symbols having a pre-determined number of symbol positions in which holes may be writ-ten and a predetermined number, 2 (n - 1), of holes, half written in even positions and half written in odd positions;
n odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format;
means responsive to said symbol counter means for trig-gering a first of said n even sample and hold cells at the first even symbol position of a symbol;
means responsive to said symbol counter means for trig-gering successive others of said n even sample and hold cells at successive even symbol positions of a symbol, the number of suc-cessive cells triggered corresponding to the number, n - 1, of holes which may be written in even positions;
n (n - 1)/2 even comparator means for comparing each even sample and hold cell value with each of the other even sample and hold cell values;
means responsive to said symbol counter means and to said n (n - 1)/2 even comparator means for retaining the values in the even sample and hold cells having the higher values and for triggering the even sample and hold cell having the lowest value at the next even symbol position and for repeating said retention and said triggering of the even sample and hold cell having the lowest value at the occurrence of every even symbol position for which the fixed-block code may contain a hole;
means responsive to said symbol counter means for trig-gering a first of said n odd sample and hold cells at the first odd symbol position of a symbol;
means responsive to said symbol counter means for trig-gering successive others of said n odd sample and hold cells at successive odd symbol positions of a symbol, the number of cells triggered corresponding to the number, n - 1, of holes which may be written in odd positions;
n (n - 1)/2 odd comparator means for comparing each odd sample and hold cell value with each of the other odd sample and hold cell values; and means responsive to said symbol counter means and to said n (n - 1)/2 odd comparator means for retaining the values in the odd sample and hold cells having the higher values and for triggering the odd sample and hold cell having the lowest value at the next odd symbol position and for repeating said retention and said triggering of the odd sample and hold cell having the lowest value at the occurrence of every odd symbol position for which the fixed-block code may contain a hole.
n even sample and hold cells responsive to read signals from an apparatus reading data from a medium having data recorded thereon in a fixed-block format comprising symbols having a pre-determined number of symbol positions in which holes may be writ-ten and a predetermined number, 2 (n - 1), of holes, half written in even positions and half written in odd positions;
n odd sample and hold cells responsive to said read signals from said apparatus reading data from said medium having data recorded thereon in a fixed-block format;
means responsive to said symbol counter means for trig-gering a first of said n even sample and hold cells at the first even symbol position of a symbol;
means responsive to said symbol counter means for trig-gering successive others of said n even sample and hold cells at successive even symbol positions of a symbol, the number of suc-cessive cells triggered corresponding to the number, n - 1, of holes which may be written in even positions;
n (n - 1)/2 even comparator means for comparing each even sample and hold cell value with each of the other even sample and hold cell values;
means responsive to said symbol counter means and to said n (n - 1)/2 even comparator means for retaining the values in the even sample and hold cells having the higher values and for triggering the even sample and hold cell having the lowest value at the next even symbol position and for repeating said retention and said triggering of the even sample and hold cell having the lowest value at the occurrence of every even symbol position for which the fixed-block code may contain a hole;
means responsive to said symbol counter means for trig-gering a first of said n odd sample and hold cells at the first odd symbol position of a symbol;
means responsive to said symbol counter means for trig-gering successive others of said n odd sample and hold cells at successive odd symbol positions of a symbol, the number of cells triggered corresponding to the number, n - 1, of holes which may be written in odd positions;
n (n - 1)/2 odd comparator means for comparing each odd sample and hold cell value with each of the other odd sample and hold cell values; and means responsive to said symbol counter means and to said n (n - 1)/2 odd comparator means for retaining the values in the odd sample and hold cells having the higher values and for triggering the odd sample and hold cell having the lowest value at the next odd symbol position and for repeating said retention and said triggering of the odd sample and hold cell having the lowest value at the occurrence of every odd symbol position for which the fixed-block code may contain a hole.
11. The decoding apparatus of claim 10 further including n (n - 1)/2 even binary register means, one for each of said n (n - 1)/2 even comparator means and responsive to said one of said n (n - 1)/2 even comparator means, for recording the counts of said symbol counter divided by two, ignoring fractions, when said one of said n (n - 1)/2 even comparator means indicates the detec-tion of a new higher value in one of the sample and holds to which it is connected;
n (n - 1)/2 odd binary register means, one for each of said n (n - 1)/2 odd comparator means and responsive to said one of said n (n - 1)/2 odd comparator means, for recording the counts of said symbol counter divided by two, ignoring fractions, when said one of said n (n - 1)/2 odd comparator means indicates the detection of a new higher value in one of the sample and holds to which it is connected;
even decoder means, responsive to said n (n - 1)/2 even comparator means and to said even binary register means, for determining which of the binary register means contains the add-resses of the holes and for decoding these addresses into binary at the end of a symbol;
odd decoder means, responsive to said n (n - 1)/2 odd comparator means and to said odd binary register means, for deter-mining which of the binary register means contains the addresses of the holes and for decoding these addresses into binary at the end of a symbol.
n (n - 1)/2 odd binary register means, one for each of said n (n - 1)/2 odd comparator means and responsive to said one of said n (n - 1)/2 odd comparator means, for recording the counts of said symbol counter divided by two, ignoring fractions, when said one of said n (n - 1)/2 odd comparator means indicates the detection of a new higher value in one of the sample and holds to which it is connected;
even decoder means, responsive to said n (n - 1)/2 even comparator means and to said even binary register means, for determining which of the binary register means contains the add-resses of the holes and for decoding these addresses into binary at the end of a symbol;
odd decoder means, responsive to said n (n - 1)/2 odd comparator means and to said odd binary register means, for deter-mining which of the binary register means contains the addresses of the holes and for decoding these addresses into binary at the end of a symbol.
12. The decoding apparatus of claim 11 wherein said even and said odd binary register means includes address means for latching the binary count of said symbol counter excluding the lowest order bit of the count in response the lowest order bit of the count.
13. The decoding apparatus of claim 10 wherein each of said means responsive to said symbol counter for triggering an odd or an even sample and hold cell at any position of a symbol includes timing means for triggering said odd or even sample and hold cell during the first half of the symbol position and terminating the triggering shortly after the first half of the symbol position.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US57815184A | 1984-02-08 | 1984-02-08 | |
| US578,151 | 1984-02-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1231440A true CA1231440A (en) | 1988-01-12 |
Family
ID=24311651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000473236A Expired CA1231440A (en) | 1984-02-08 | 1985-01-31 | Read channel for optical recorder |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1231440A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743242A (en) * | 2023-11-22 | 2024-03-22 | 中金金融认证中心有限公司 | Even number last level compensation system and compensation method between low-speed CPU cores |
-
1985
- 1985-01-31 CA CA000473236A patent/CA1231440A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117743242A (en) * | 2023-11-22 | 2024-03-22 | 中金金融认证中心有限公司 | Even number last level compensation system and compensation method between low-speed CPU cores |
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