CA1228179A - Packaging microminiature devices - Google Patents

Packaging microminiature devices

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Publication number
CA1228179A
CA1228179A CA000474333A CA474333A CA1228179A CA 1228179 A CA1228179 A CA 1228179A CA 000474333 A CA000474333 A CA 000474333A CA 474333 A CA474333 A CA 474333A CA 1228179 A CA1228179 A CA 1228179A
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CA
Canada
Prior art keywords
chip
substrate
arbitration
component
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000474333A
Other languages
French (fr)
Inventor
Kwok K. Ng
Simon M. Sze
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of CA1228179A publication Critical patent/CA1228179A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

INTEGRATED CIRCUIT CHIP ASSEMBLY
Abstract A compact assembly of integrated circuit chips is produced by inserting chips into wells, grooves, or openings in a carrier substrate. Chips have beveled edges as produced by anisotropic chemical etching, and the substrate has sloping walls so as to allow positioning by match-up with beveled edges of chips. Electrical interconnection of circuits is by patterned metallization overlying chips and substrate.

Description

I

INTEGRATED CIRCUIT CHIP ASSEMBLY

Technical Field The invention is concerned with integrated circuit technology.
Background of the Invention To satisfy an ever-increasing demand for computing and data processing power, both with respect to processing speed and storage capacity, computer design has been evolving toward increasingly compact arrangements of components and assemblies. Attention has been directed to the number of so-called package levels (a package being defined as a group of structurally similar components or assemblies) as, e.g., by R. F. Burner et at, "Advanced Printed-Circuit Board Design for High-Performance Computer Applications", IBM Journal of Research and Development, Vol. 26, No. 3, May 1982, pp. 297-305.
Attention has also been given to the way components and assemblies are interconnected; e.g., C. W. Ho et at, "The Thin-Film Module as a High-Performance Semiconductor Package," IBM Journal of Research and Development, Vol. 26, No. 3, May 1982, pp. 287-296, discuss a musinglei-chip module of silicon chips attached to thin-film transmission lines. Among early proposals for the achievement of high device density in silicon technology is one by P. Crank et at., "Wafer-Chip Assembly for Large-Scale Integration", I_ Transactions on Electron Devices, Vol. Ed-15, No. 9, September 1968, pp. 660-663, where silicon chips are bonded "face down" on a silicon wafer.
The use of preferential etching is known to produce assemblies in which a circuit-carrying chip is positioned on a substrate by means of at least one beveled edge which is matched to a sloping wall of a surface depression in a substrate.
- 2 - ~2~79 Summary of the Invention In accordance with an aspect of the invention there is provided device comprising a substrate and an integrated circuit chip, the material of said substrate and the material of said integrated circuit chip being in crystallographic ally compatible, essentially single-crystal form, said substrate having a surface depression which has a sloping wall resulting from crystallographic ally an isotropic etching, said chip having a beveled edge resulting from crystallographic ally an isotropic etching, said edge and said slope being in juxtaposition, whereby said chip is positioned on said substrate, and a conductive path between said chip and said substrate overlying said chip and said substrate.
In accordance with another aspect of the invention there is provided method of making a device comprising a substrate and an integrated circuit chip, the material of said substrate and the material of said integrated circuit chip being essentially in the same single-crystal form, said method comprising the steps of: anisotropically etching a portion of said substrate to form at least one surface depression having a sloping wall; anisotropically etching a portion of said chip -to form at least one beveled edge; placing said chip in said depression so as to juxtapose said beveled edge and said sloping wall and thereby position said chip on said substrate; and forming a conductive path between said chip and said substrate overlying said chip and said substrate.
Typically, alignment of chips involves match-up between two or four pairs of sloping faces, e.g., when chips are aligned in grooves or in Eour-sided wells.
Chips carry integrated circuitry, and electrical connections are made by one or several conductive paths overlying the chip and the substrate.

- pa 8P79 Brief Description of the Drawing FIGS. 1, 2, and 3 are schematic cross-sectional views of an integrated circuit assembly in accordance with the invention at different stages of manufacture.
Detailed Description The following terms are prominently used in the description of the invention, and their meaning is as follows:
A substrate is a material body which has a surface which can serve as a support for material objects which may be insufficiently rigid in the absence of support or whose spatial arrangement depends on the presence of a support. A substrate typically is relatively thin as compared with a planar extent.
A earlier substrate and a chip are mutually defined as substrates of relatively larger and smaller size, respectively, so that a plurality of chips can be attached to a carrier substrate.
An integrated circuit is a miniaturized electrical circuit which is supported by a substrate.
Preferential etching or crystall~raphically an isotropic etching is a chemical process which results in removal of surface matter at rates which differ depending on crystallographic direction in an essentially single-crystal material.
In accordance with the invention and in the interest of positioning a chip on a carrier substrate so as to facilitate electrical interconnection of circuitry on the chip and on the substrate, preferential etching is applicable to at least a portion of substrate and at lest a portion of chip material. Such portions are here designated as body portions, and it is understood that substrate and chip may comprise portions other than such body portions such as e.g., devices, circuits, and passive components.
FIG. 1, 2, and 3 show substrate 11, chip 12, insulating filler 13, and integrated circuit 14 with contact pads 15.
FIG 2 and 3 further show planarized insulating layer 21, electrical conductor 22, and contact pads 23.
FIG. 3 further shows planarized insulating layer 31 and electrical conductors 32.
Substrate 11 and chip 12 in FIG. 1-3 are preferably made of the same, essentially single-crystal material which is amenable to preferential etching, silicon being a primary example of such material.
In particular, in the case of silicon, it is possible to fabricate chips with precisely oriented beveled sides (i.e., (111) faces) by an isotropic wet etching of (100) planes, with the resulting beveled faces at an angle of 54 degrees. Matching beveled wells in So wafers can be made with an angle of 126 degrees between the bevel and a wafer plane. In the Figures the angle of 54 degrees is between the top surface of chip 12 and the beveled face of ,:

I

the chip, and the angle of 126 degrees is between the top surface of wafer 11 and the beveled face of the wafer).
Etching of silicon for mask alignment is disclosed in U. S. patent No. 4,470,875.
The following sequence of steps can be used to make an assembly in accordance with the invention:
Circuits are produced on chip-size portions of a substrate in customary fashion by deposition of layers and photo lithographic patterning. A layer of silicon nitride is deposited on front and back sides of the silicon wafer, a layer of a photo resist material is deposited on the silicon nitride on the back side, and a pattern corresponding to desired chips or openings is optically projected onto the photo resist layer. The exposed photo resist is developed, and the developed pattern is copied into the silicon nitride layer, e.g., by reactive ion etching. Preferential etching of the exposed portions of the silicon wafer is conveniently effected by the use of, e.g., potassium hydroxide as an enchant using a silicon nitride mask; etching may be partly into the wafer or through its entire thickness. Etch rate is typically such that a Molly wafer is etched through in a time of from 7 to 8 hours.
Etched chips are inserted into correspondingly etched grooves, wells, or openings in wafers; attachment by means of an insulating adhesive is convenient. The surface of an inserted chip is preferably essentially co-planar with the wafer surface.
A layer of a planarizing material such as, e.g., a polyamide or other photo-definable polymer, is deposited over the assembly, and holes corresponding to underlying circuit contact pads are etched by photo lithographic patterning followed by reactive ion etching. A
metallization such as, e.g., an aluminum metallization is applied and patterned by reactive ion etching.
Among suitable chip and wafer materials other than silicon are III-V semiconductor compounds such as, .
_ - 5 - ~2~79 e.g., gallium arsenide and gallium arsenide indium phosphide.
Among advantages of the new insulating circuit assembly are the following:
1. The new approach eliminates wire bonding operation.
2. The new approach eliminates a level of individual packaging namely, e.g., so-called DIP or chip carriers.
3. All chips of an electronic system or subsystem are packaged in one operation.
4. Circuit design is facilitated by contacts for metallization which can be located at any place inside the chip.
5. Multilevel metallization can be made by repeated deposition of insulating layers, metallization, and patterning.
6. The length of interconnections between chips can be minimized by suitable arrangement of chips on a substrate; this will reduce parasitic inductance and resistance. Parasitic capacitance decreases with increasing thickness of an insulating layer.
Device assemblies as disclosed above are con-ridered to be particularly suitable for the implementation of systems as disclosed in British Patent Application No.
AYE which was filed in the name of D. E. Blowout and which was published on September 4, 1985 which is directed to a plurality of component circuits being coupled together via a signal conduit path. Each of the component circuits is adapted to have a priority with respect -to the trays-mission of information onto the signal conduit path. A
plurality of arbitration conduit paths exists. Each of the component circuits, except for possibly the component circuit having the lowest priority, comprises a separate one of a plurality of arbitration request circuits. Each arbitration request circuit is coupled to separate one of the arbitration conduit paths and is adapted to selectively allow a signal from its component circuit to reach the arbitration conduit path coupled thereto. Each of the component circuits, except for possibly the component circuit having a highest priority, comprises a separate one of a plurality of arbitration circuits. Each arbitration circuit is coupled to at least one of the arbitration conduit paths and is adapted to detect which of any of the other component circuits having a higher priority is requesting access to the signal conduit path and to enable its component circuit to gain access to the signal conduit path if its component circuit is requesting access to the signal conduit path and if its component circuit has a higher priority than any other component circuit which is requesting such access.

,..

Claims (15)

Claims:
1. Device comprising a substrate and an integrated circuit chip, the material of said substrate and the material of said integrated circuit chip being in crystallographically compatible, essentially single-crystal form, said substrate having a surface depression which has a sloping wall resulting from crystallographically an isotropic etching, said chip having a beveled edge resulting from crystallographically an isotropic etching, said edge and said slope being in juxtaposition, whereby said chip is positioned on said substrate, and a conductive path between said chip and said substrate overlying said chip and said substrate.
2. Device of claim 1, the material of at least a body portion of said substrate and the material of at least a body portion of said chip having the same crystallographic structure.
3. Device of claim 2, the material of said body portion of said substrate being essentially the same as the material of said body portion of said chip.
4. Device of claim 3 in which said material is a semiconductor material.
5. Device of claim 1 in which at least two beveled edges of a chip are in juxtaposition with sloping walls of a surface depression.
6. Device of claim 5 in which your beveled edges of a chip are in juxtaposition with sloping walls of a surface depression.
7. Device of claim 4 in which said material is essentially silicon.
8. Device of claim 1 comprising a plurality of chips, said chips being electrically interconnected by electrical conductors on said wafer.
9. Device of claim 1 in which said conductive path is on a planarizing layer.
10. Device of claim 8 in which the material of said planarizing layer is a photodefineable material.
11. Device of claim 1 comprising:
a plurality of component circuits being coupled to a signal conduit path and selectively needing to transmit information onto the signal conduit path;
a plurality of arbitration conduit paths;
each of the component circuits being adapted to have a priority with respect to transmission of information onto the signal conduit path;
each of the component circuits, except for possibly the component circuit having the lowest priority, comprising a separate one of a plurality of arbitration request circuits;
each arbitration request circuit being coupled to a separate one of the arbitration conduit paths and being adapted to selectively allow a signal from its component circuit to reach the arbitration signal conduit path coupled thereto;
each of the component circuits, except for possibly the component circuit having a highest priority, comprising a separate one of a plurality of arbitration circuits; and each arbitration circuit being coupled to at least one of the arbitration conduit paths and being adapted to detect which of any of the other component circuits having a higher priority is requesting access to the signal conduit path and to enable its component circuit to gain access to the signal conduit path if its component circuit is requesting access to the signal conduit path and if its component circuit has a higher priority than any other component circuit which is requesting such access.
12. Method of making a device comprising a substrate and an integrated circuit chip, the material of said substrate and the material of said integrated circuit chip being essentially in the same single-crystal form, said method comprising the steps of:
anisotropically etching a portion of said substrate to form at least one surface depression having a sloping wall;
anisotropically etching a portion of said chip to form at least one beveled edge;
placing said chip in said depression so as to juxtapose said beveled edge and said sloping wall and thereby position said chip on said substrate; and forming a conductive path between said chip and said substrate overlying said chip and said substrate.
13. Method of claim 12, said method comprising juxtaposing at least two beveled edges and corresponding at least two sloping walls.
14. Method of claim 13, said method comprising juxtaposing four beveled edges and corresponding four sloping walls.
15. Method of claim 12, said method comprising the step of depositing a planarizing layer prior to forming said conductive path.
CA000474333A 1984-02-17 1985-02-14 Packaging microminiature devices Expired CA1228179A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58126084A 1984-02-17 1984-02-17
US581,260 1984-02-17

Publications (1)

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CA1228179A true CA1228179A (en) 1987-10-13

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