CA1204515A - Interface for serial data communications link - Google Patents

Abstract

Abstract An interface circuit for coupling a parallel data device to a serial data channel over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder comprising a flip-flop an exclusive-or gate and at least one delay line separates the data and clocking signals. The serial data signals are clocked into a serial register under control of the external clocking signals from the channel. A carrier detector enables the serial register only when valid information signals are present. A
parallel data register receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

Description

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This application is a divisional of copending Canadian Application Serial No. 427,591 wiled on May 6, 1983 in the name of Digital Equipment Corporation.
The invention which is the subject of this Application is particular-ly useful in a system incorporating one or more of the invent-ions shown in the followingly commonly assigned applications.
Canadian Patent Application Serial No. 427,593 filed May 6, 1983, titled METHOD AND APPARATUS FOR DIRECT MEMORY - TO-MEMORY INTERCOMPUTER COMMUNI-CATION, in the name(s) of William Strecker, Robert Stewart, and Samuel Fuller;
Canadian Patent Application Serial No. 427,599 filed May 6, 1983, titled DUAL
PATH BUS STRUCTURE FOR CO~UTER INTERCONNECTION, in the names of William D.
Strecker, David Thompson and Richard Casabona; and Canadian Patent Application Serial No. 427,594 filed May 6, 1983, titled DUAL-COUNT, ROUND-ROBIN
DISTRIBUTED ARBITRATION TECHNIQUE FOR CONTENTION-ARBITRATED SERIAL BUSES, in the name(s) of William D. Strecker, John E. Buzynski, and David Thompson.
This invention relates to the data processing systems, and more specifically, to a digital data communication system useful for decoding and transferring information among devices of a digital data processing system using serial communications therebetween, wherein clock and data signals are combined, such as with so-called Manchester-type encoding.
Various techniques exist for synchronous, bit-serial digital communi-cations. Because both clock and data are sent over the same communications channel in such systems, particular attention must be (and is) given to protecting the integrity of the signal thus conveyed.
One such technique is known in the art as Manchester encoding. To produce Manchester encoded data, representa-tions of digital data bits and ~3 S~5 a clocking signal are combined together for transmission as but one common information signal which may be sent over a single serial data channel. Fre-quently, a coaxial cable constitutes the transmission medium of the informa-tion channel. decoder, coupled to the inEormation channel at the receiver, separates the data bits and clocking signals from the composite signal, whereby the data bitsg under control of the clocking signals extracted thereby, are transferred to the device which is coupled to the decoder. With most coding schemes, more difficulties lie with decoding operations than with encoding operations, and Manchester-type encoding follows this general rule. See, for example, United States patents 4,167,760 and 4,317,211. This invention, too, is directed to the provision of an efficient Manchester-type decoder.
However, this invention is directed in particular to the problems encountered when Manchester encoding is used for serial transmission over a carrier-sense multiple access (CSMA) channel. Since, in a con~nunications sy-stem employing Manchester-type codes, the timing signals needed for controlling the transfer of data bits at the receiving end are derived both from clocking signals transmitted by a transmitting device (i.e., they must be extracted from the data channel) and from an internal clock source in the receiving device, some means must be provided to synchronize the two clocks. (It is presumed the transmitting device operates asynchronously and independently from the receiv-ing device.) Furthermore, the external clocking signals transmitted by the transmitting device may become corrupted by, for example, noise or a collision of signals on the channel due to two or more transmitting devices attempting simultaneously to transmit information. It is desirable, therefore, to pre-vent collisions or other corruptive influences from interfering with internal timing operations.

S~5 Further, as with any digital data communication system it is desired to attain as high a rate as possible of data transEers, keeping within the cost and timing contraints imposed by available circuit components. It is an object of this invention to provide for very high speed serial transfers without incurring exhorbitant circuitry costs. Prior art systems which might use, for example, a phase-locking loop circuit for controlling the Manchester decoding operations are both costly and relatively slow in locking onto in-formation signals transmitted at rates of, say9 7~ megabits per second or more.
Another objective of this invention is to provide an economical and efficient Manchester decoder useful for decoding high-speed bit-serial informa-tion transmitted over a serial communications link that is shared by several devices connected thereto.
According to one aspect, the present invention provides apparatus or decoding (i.e., separating the clocking and data signals of) a Manchester encoded signal comprising: i. a flip-flop having a data input for receiving the information signals, ii. a first delay means having an input connected to the non-inverting output of the flip-flop, iii. an exclusive-OR gate which receives at one input thereof the data output of the flip-Elop delayed by the first delay means, said exclusive-OR gate being coupled for clocking the clocking input of the flip-flop, and iv. a serond delay means having an output coupled to a second input of said exclusive-OR gate and an input for receiving the in-formation signals, thereby to generate decoded clocking signals at the output of the exclusive-OR gate and decoded data signals at the non-inverting output of the flip-flop.
According to another aspect, the present invention provides apparatus 12~4S~

for decoding to an NRZ signal an encoded signal received from a signal source, the encoded signal encoding a series of data bits with, for each data 'oit, a first transition in the encoded signal, and, for each data bit for which the succeeding data bit has the same binary value, a second transition occurring within a predetermined time interval after the first transition, said apparatus comprising: A. storage means responsive to a clocking signal of at least a predetermined minimum pulse width, received at a clock input of the storage means, for storing a sample of a digital signal received at a data input of the storage means, the storage means having at least one output indicative of the value of the stored sample, an output of the storage means providing the decoded NR~ signal, B. an exclusive-OR gate, C. a first signal path from an output of the storage means through the exclusive-OR gate to the clock input of the storage means, D. a second signal path from the source of the encoded signal through the exclusive-OR gate to the clock input of the storage means, and E. a third signal path from the source of the encoded signal to the data input of the storage means, wherein a. the time for a signal to propagate along the first signal path is at least as long as the minimum pulse width required to clock the storage means, and b. wherein the difference between the time for a signal to propagate along the second signal path and the time for a signal to propagate along the third signal path is at least as long as said predeter-mined time interval, and c. the output signal from the exclusive-OR gate com-prises a signal which has exactly one pulse for each data bit.
The invention will now be described ln greater detail with reference to the accompanying drawings, in which:
Figure 1 deplcts a communications channel to which several devices 4S~5 of a data processing system connect through the interEace network of the present invention, shown in block diagram form;
Figure 2A is a schematic circuit diagram of one embodiment of a Manchester decoder according to the present invention; depicted in Figure l;
of the present invention;
Figures 3 and are timing diagrams illustrating the operation of the Manchester decoder of Figure PA;
Figure 2B is a schematic circuit diagram of another embodiment of a Manchester decoder according to the invention;

1~45~5 ig. 5 is a circuit diagram of the carrier detector circuit depicted in Fig. l;
Pig. 6 is a circuit diagram of the serial shift register, parallel shift register, framer, and synchronizing character detector depicted in Fig. l; and Fig. 7 is a circuit diagram ox the internal clock and synchronizing circuit depicted in Fig. 1.
Description of an Illustrative Embodiment Fig. 1 depicts a communications link and interface 0 including a transmitting channel 14 and receiving channel 16 over which a plurality of devices 12a, 12b and 12c connect via their respective interfaces 10a, 10b and 10c Information on the transmitting and receiving channels 14 and 16 are coupled by a coupler lS which lS enables devices on the channel 16 to sense information signal transmitted on the channel 14. In a data processing system, a device 12a includes at least a processor and memory, and may be a computer system, input/output device on secondary memory such as a controller and disk or tape storage device, for example, which transmits or receives data in parallel.
As this invention is concerned with a system for decoding Manchester~encoded serial data and transferring the decoded data to a parallel device, we show in interface 10c, an expanded block diagram of the interface circuitry in which a driYer 20 (e.g., amplifier) receives from the receiving channel 16 signals representing serial data bits are clock transitions and supplies these signals to a Manchester decoder 22. As is well known, Manchester-encoded data comprises data bits and clock transitions combined in the same information signal. The :decoder 22, being subsequently described, extracts the data signal (herein called data bits) and a clock (i.e., CLOCK) signal from the information signals on the channel s . , i . i ._ ._ .. ,.____ , ._, _,_ .. , ,, , , _, _, _ . .. , . ___ _, . _ , , _ . , . .. . . _ .. .

16 and supplies both the data bits and the CLOCK signal to a serial shift register 30 via conductors 26 end 28, repectively. The data bits are applied to the input of the first stage of the register 30 while the CLOCK signal serially shifts of the data bits into the successive stages thereof.
In order to determine whether valid information signals are present on the receiving channel 16, a carrier detector circuit 24 also receives information ~0 from driver 20~ The circuit 24 tests, in a unique manner, the character of the information signals and, under certain conditions subsequently described in detail, produces an EN (i.e., enabling) signal on conductor 32, which enables the serial shift register 30 so that it receives and shifts the serial data bits from the data line 26. In essence, the carrier detector circuit 24 prevents noise signals which might appear on the channel 16 from entering the register 30.
A periodic instances of time during the transmission of the serial data, a predetermined number pf data bits to a byte) is transferred from the serial register 30 to the parallel register 40. In our preferred embodiment, eight data bits constitute a byte.
Thus, the byte rate is ~ne-eighth the bit rate. As each ~5 set of eight data bits accumulates in the serial register 30, a byte is transferred under control of a framer 38, also subsequently described, which enables the loading of the parallel register 40 associated with the serial register 30. The framer 38 effects a transfer of a byte to the parallel register 40 at a time înstance that is .coincident with the shift of a serial data bit into the serial register 30. The parallel register 40 then periodically transers these bytes to the device 12c under control of an internal receiver clock 46~ The ~4~S

receiver clock is controlled by the crystal oscillator circuit.
As previously mentioned, a problem solved by this invention is the synchronizing of the transfer of the bytes from the register 40 to the device 12c (this transfer is controlled by the internal clock 46) with the transfer of the individual data bits from the channel 16 to the register 30 (this transfer is controlled by the CLOCK signal pulses extracted from the channel 16~.
l Since it is possible that two or more of the devices 12 may simultaneously attempt to transmit information signals and thus corrupt the CLOCK signal, it is not possible to rely on the CLOCK signal to run the device 12c; otherwise, the parallel transfers could become lS fouled in this case.
To overcome this problem, an internal clock synchronizing circuit 42 is provided. This circuit runs freely and is synchronized with the CLOCK signal pulses when a synchroni7ation detector circuit 34 detects a unique synchronizing character at the beginning of the serial data stream. When the synchroni2ing character is detected, it momentarily stalls the internal receiver clock 46 if it is out-of-sync with, in this case, the periodic occurrences of eight CLOCK signal pulses, to adjust the phase of the internal clock 46. Therefore, complete isolation is achieved between the operation of the internal receiver clock 46 and the clocking signals extracted from the receive channel 16. This permits each of the devices 12 coupled to the communications link to operate asynchronously and independently - i.e. t under control of its own separate clocking circuit.
Upon transmitting information from a device l2, a parallel-to-serial register 47 receives eight-bi~ bytes prom the device 12c under control of a clock located .. . .

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therein, and when the signals representing the byte settle in the register 47, a clock 49 effects a shift on a serial basis of the data bits constituting the byte, to the encoder 23. Ihe encoder 23 combines representations of the data bits with clocking signals from the clock 49 to produce Manchester encoded information signals. These information signals are then applied to driver 18 which places the encoded information signals on the transmitting channel 14 where they are distributed by the passive coupler 15 to the other devices connected to the communicating link.
With this basic understanding of the foregoing aspects of the invention, the Manchester decoder 22 is now described. Refer to the circuit of Fig. 2A and the timing diagrams of Figs. 3 and 4. A typical encoded information signal 60 from the receiving channel 16 (Fig.
1) enters the Manchester decoder over a conductor 48 and data and clocking signals leave the decoder via conductors 26 and 28, respectively. As shown by the information signal 60, a "zero" data bit is represented by a positive transition at the midpoint of the bit cell and a "one" data bit is represented by a negative transition at the midpoint of the bit cell. Bit cell 68, for examplel contains a "one data bit.
The ManchestPr decoder essentially comprises a flip-flop 50, an exclusive-or gate 52, and delay lines S4A and 58~. The delay line 56 provides a delay comparable to the exclusive-or gate 52, bein9 provided so that the time difference between the occurrence of pulses in the information signals at the "D" and "CLR" inputs sf the flip-flop 50 is primarily determined by the delay line 58A, rather than by the delay through gate 52 which varies to some extent among circuit components. In ... , , .. .. ,. ,.. ._ . . .. _ .. . _ _ ,_ , . ... ._ . . .. . . _. .. .. .. ... . .

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practice, an exclusive-OR gate on the same logic chip as the gate 52 may constitute the delay line 56.
With that understanding, the Manchester encoded signal 60 appears at the "D" input of flip-flop 50. To begin operations in the decoder, all data transmissions must be preceeded by a "zero-to-one" bit transition and the flip-flop 50 is clocked during the first half of each bit cell thereby to transfer the logical status of the bit cell Jo the data line 26. For example, if a "one" is l detected, it appears on the data line 26. Likewise, if a "zero is detected, it too appears on the data line 26.
The latter half ox each bit cell could be sampled, as well but if so, the loqical status of the data bits would be inverted.
To extract the clocking signal from the sampling flip-flop 50 of the decoder, a clocking signal 66 is derived by "exclusive~OR'ing" in gate 52 the delayed Manchester encoded signal 62 (at the output of delay llne 58A) with the delayed flip-flop output signal 64 (at the output of delay line 54A). The encoded data is sampled by the flip-flop 50 on positive excursions of the signal 66. The e~clusive-OR gate 52 then provides the pulses of the signal 66 to the "CLK" input of the flip-flop, and the width of the pulses is determined by the amount of delay provided by delay line 54A. On the other hand, the amount of delay provided by delay line 58A is established so that, as more clearly shown in Fig. 4, the time instances of a mid-cell transition 86 on the flip-flop "CLR" line occur at the midpoint of the first half period B4 of the next cell time. In this fashion, the bit cells .are most likely to be sampled at a time instance that more reliably passes a representation of the data bit through the flip-flop 50 to the data line 26, even when there is a sliqht phase shift in the incoming information I., .... ... .... _ .. _ _ ... ..... _ .... ... .. ... .... .

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signal. As the flip-flop 50 is clocked on the poSitive-going edges of the pulses of the signal 66, the width of the pulses thereof do not affect the sampling operations except that they must be compatible with the circuitry used. As mentioned with reference to Fig. 1, the output of the flip-flop 50 and the clocking signal from the gate ~2 couple the serial shift register 30.
Note further that, a transition from Hzero" to "one, or from "one to "zero, in the serial bit stream l causes a pulse to be generated in signal 66~ A series of consecutive "zeroes" causes the delayed Manchester signal to appear in the bit cell of signal 66 and a series of "ones" causes the delayed Manchester signal to appear, but inverted. Thus, the na~re and characteristics of the encoded signal also can be derived from this information.
It will be understood by those skilled in the art what operation according to the same principles can be provided by locating delays in other positions within a circuit of comparable topology. For example, as Fig. 2B
shows, part of the required delay may, if desired, be placed between the output of exclusive or gate 52 and the clock input of flip-flop 50. Operation as described above is obtained so long as: l the sum of the delays through the combination of delay lines 54B and 57 and exclusive-OR gate 52 is greater than the minimum clock pulse width required by ~lip-flop 50 and less than one bit cell duration minus the required flip-flop clDck pulse width, and (2~ the sum of the delays through the combination of delay lines 58B and 57 and exclusive-OR
gate ~2 is approximately equal to three~fourths (3/4~ the :bit cell interval. These restrictions may be satisfied with delay 57 or 54B equal to zero, of course, so only two delay element are needed, as a minimum. Indeed, if 'I_ . .. .. l .-- .~ _. I_ _ . _--' _ _--_ I_.__ -- '.`_ .. _ _ .. _ _ .. _. _. _ ..... _ , . _ .. . . , . , _ .

.5~5 teh propagation through the flip-flop and exclusive-OR
gate take long enough, so that a clock pulse of sufficient width can be provided, delay line 54B can be omitted.
As should now be apparent, the above described Manchester decoder is simple, efficient, capable sf high speed operation, needs very little ~lock-acquisition~' time, and is very reliable in that it can tolerate rather large excursions in phase shift c almost one-fourth lo of a bit cell time). In the preferred embodiment, ~siny inexpensive conventional circuit components decoding has been achieved at rates as high as seventy to one hundred megabits per second without losing the clock edge and yet still discriminating between the clocking and data signals.
The carrier detector circuit 24 (Fig. l) is shown in Fig. 5 and is provided for enabling the serial shift register 30 to swift data from data line 26 into the several stages thereof. In effect, the carrier detector cireuit 24 indicates that valid data and clocking signals are present on the data and clock lines 26 and 28, respectively, so as to reject noise signals which might enter the receiver channel 16. A series of alternating "ones" or "zeros preceeds an information transmission over the receive channel. To sense valid data, the circuit 24 employs a comparator 90 for csmparing the level of the signals emanating from the driver 20 and appearing at input 92 of the comparator with a threshold level applied at comparator input 94 from a voltage 3D divider network comprising resistors 96 and 98.
: Following a valid bit information transmission7 the comparator 30 generates a pulse each time an information signal exceeds the threshold voltage level established by the voltage divider network 96 and 98, thereby to set a , .~n . ~.~__~ .~_ _~ .. __~. _ . _ __,, ._ _ _ _ .. _ ._ . _.. __ _ . _ ., __ .. _ . _~ _ .. _ . . .. . _ .. _ ...... _. _ _._ .. , ._ . . _ . _ . .

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data flip-flop 100~ A clock signal from an internal clock source (e.g., 46) includes a divide-by-eight counter 102 which produces clocking signals At in the preferred embodiment, one-eighth of the rate of the information signals; this is referred to as the RCVR CLK
signal. It clocks $1ip-flops 100, 106 and lOB. Being that the rate of the information signals is at least 35 MHz, at least two information pulses are assured to occur between each occurrence of a RCVR Cl,K pulse.
l If a valid informatioo signal (i.e., one exceedlng the carrier detect threshold) is present on the information channel, flip-flop 100 will be set and, upon the occurrence of each RCVR CLK pulse, flip-flop 108 becomes set and flip-flop 100 is cleared. Thus, so long as a carrier signal is present, flip-flop 100 always appears to be set when sampled by flip-flop 106. After two RCVR CL~ pulses, flip-flop lOB becomes set thereby to assert a CARRIER DET signal which enables the serial shift register 30. If, on the other hand, valid information signals are not present at the input 92, the flip-flop 100 is not set but is instead cleared by the RCVR CLK signal in that its data input is tied to ground.
When the contents of flip-flop 100 is sampled by the flip-flop 106, a "zero" appears. After two occurrences of the RCVR CLK pulse, both flip-flops 106 and 108 are cleared and the CARRIER DET signal becomes deasserted.
Fig. 6 shows, in greater detail the circuits 30, 34, 38 and 40 of Fig. 1 for detecting the synchronizing character and for converting serial data to parallel data The serial shit register 30 receives serial data at its input stage D0 under control of the CL~ signal prom the ffanchester decoder 22. Initially, the parallel register 40 is held in load mode by a signal applied on conductor 110, which represents the status of the D7 435~

stage of the framer 38. Until the synchronization character is detected, the Eramer 38 is held in the above-described condition and the parallel register 40 is held in load mode. However, when the synchroni2ing character is present in the serial data stream a decoder 112 detects a unique combination of eight data bits, constituted by the data bits present in stages D0-D6 of the serial shift register 30 and the next serial in data bit appearing at input 114 of the decoder 112. On the next CL~ signal pulse, the decoder 112 asserts an output signal at the ED" input of a flip-flop 116 which, in turn, asserts a signal on conductor 118 and driver 120.
The driver 120 generates the SYNC signal for the internal clock synchronizer 42, its operation being subsequently explained.
As a result of the assertion of flip-flop 116, a "one" signal begins to circulate in the framer 38 under control on the CLK signal pulser. Before the interface is started, the "one" is constantly loaded into the D7 position in the framer 38 and the other stages are cleared. Eight CLK signal pulses later, the "one" signal which was initially loaded into the D7 stage of framer 38 again appears at the D7 stage whereupon a signal becomes asserted on the conductor 110 thereby to enable the parallel register 40 to load. Upon the occurrence of the next CL~ signal, the eight data bits which followed the synchronizing character now reside in the serial shift register 30 and then are shifted, in parallel, to the parallel register 40. The zone" signal in the D7 stage of the register 38 passes to the D0 stave thereof via -conductor 110 and the Uzero~ in the D6 stage pas es to the D7 stage, which thus disables the parallel register 40O The occurrence of every eight CLK signal pulses causes the "one" signal to be recirculated into the D7 ... ,, .,, . .. . _ . .. . . ... . .. .. .

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stage of framer 38, thereby to effect parallel tranfers of eigh~-bit bytes from the serial register 30 to the parallel register 40. Each bit of the byte in the D0-D7 stages of the parallel register 40 is then driven by drivers 122-~36 onto a parallel bus of the receiving device in the data processing system.
Fig. 7 depicts a preferred circuit implementation for the internal clock synchronizing circuit 42 of Fig.
1. As shown, the circuit 42 receives clock pulses from the internal 35 MHz oscillator at an input 140. The 35 MHz clock signals clock each stage of a divide-by-four counter constituted by latches 142, 144, 146 and 14B. At time periods other than the clock synchronization period ~164 set, 166 clear) the output of gate 168 is held at a 15 "one" state. Thus, one input of each of nand gates 152, 154, 156 and 158 is enabled, which permits the contents of each stage 142, 144, 146 to be shifted to a succeeding stage. The last stage 148 produces the RCVR CLK signal.
Upon the occurrence of every fourth cycle of the 35 MHz clock oscillator, the output state of latch 148 sets to the "0" state, thereby to generate the assertion of the RCVR CLK signal. Latch 148 is returned to the "1"
state on the next cycle of the 35 MHz clock. In the feedback network, the nand gate 150 couples the output stages of latches 14~, 144 and 146 which, when each contains a zone" state, for exampley energizes the nand 150. When so energized, "zero is placed in the latch 142 on the next cycle of the 35 MHz clock oscillator.
With the Nero" in latch 142, nand gate 150 become deenergizedl thereby to return the input of watch 142 to none", but the "zero is instead passed to the text latch 144 as the nand gate 154 becomes energized. A5 the 35 MHz clock cycles progress, the zero" propagates to the latch 148, to produce the RCVR CLK pulse thereat; and the .

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state of each of the latches 142, 144 and 146 returns to a "one" state. Afterwards, another "zero" momentarily appears at the input of latch 142 for one period o the 35 MHz oscillator.
When the detector 34 (Fix. 1) detects the synchroniæing character in the serial data stream, the SYNC signal is asserted at the input of the latch 162 at one cycle thereafter (see Fig. 6, latch 116). After two cycles after assertion of the SYNC signal at latch 162, nand gate 168 becomes engergized by the high level output of latch 164 and the low level output of latch 166. Nand gate 168 remains energized for one cycle of the 35 MHz clock oscillator. When so energized, each of the nand gates 152, 154, 156 and 158 becomes deenergized, thereby to recycle the divide-by-four counter constituted by the latches 142, 144, 146 and 148. Recycling places a logical "one" into stages 142, 144, and 14S of the counter, and a "zero" into the latch 142 upon the occurrence of the next clock period of the 35 MHz clock oscillator. If the RCVR CLK signal were already in phase with the SYNC signal, then the "zero" in latch 142 would in effect be shifted to latch 148 as if it were a normal recycling of the counter.
The resynchronization of the internal clock circuit is implemented so as to guarantee a minimum of one byte clock period during resynchr~nization thus avoiding the creation of logic race condition5 due to the occurrence of a short cycle. The receiver clock period may be increased from one to one and three-quarters byte times in duration in one quarter byte increments during the resyncheonization period.
The above illustrative embodiment depicts a circuit arrangement for interfacing a device to a serial data communicating link in a data processing system. It can, , . , , . ... , . . . . , , , . , . , .... _ .. .... .. .. .. .... .

~45~L5 however, be used for any type of 3erial data communicating link over which clocking signals nze transmatted to device lo having itB own internal, clock which requires i601ation from the external clocking signals, whether or no these external clucking signals are extracted from ~anche~ter-type ~nc~ded information.
Etch component Go the ~y~tem beiny exemplary. we do not intend to limit the QC~pe of our invention Jo the specific embodiments shown or described, but instead, we intend the scope o our inventiGn tG encompass eh~se modifications and v~ri~tions as may be apparent tD those persons skilled in the art to which the subject matter pertains.

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Claims (4)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Apparatus for decoding (i.e., separating the clocking and data sig-nals of) a Manchester encoded signal comprising: i. a flip-flop having a data input for receiving the information signals, ii. a first delay means hav-ing an input connected to the non-inverting output of the flip-flop, iii. an exclusive OR gate which receives at one input thereof the data output of the flip-flop delayed by the first delay means, said exclusive-OR gate being coupled for clocking the clocking input of the flip-flop, and iv. a second delay means having an output coupled to a second input of said exclusive-OR gate and an input for receiving the information signals, thereby to generate decoded clocking signals at the output of the exclusive-OR gate and decoded data signals at the non-inverting output of the flip-flop.

2. A decoder circuit as recited in claim 1 further including a third delay means providing a delay that is equal to the delay interjected by said exclusive-OR gate and interposed between the information signals and the data input of the flip-flop.

3. A decoder circuit as recited in claim 1 further including a third delay means interposed between the output of the exclusive-OR gate and the clocking input of the flip-flop.

4. Apparatus for decoding to an NRZ signal an encoded signal received from a signal source, the encoded signal encoding a series of data bits with, for each data bit, a first transition in the encoded signal, and, for each data bit for which the succeeding data bit has the same binary value, a second transition occuring within a predetermined time interval after the first tran-sition, said apparatus comprising: A. storage means responsive to a clocking signal of at least a predetermined minimum pulse width, received at a clock input of the storage means, for storing a sample of a digital signal received at a data input of the storage means, the storage means having at least one output indicative of the value of the stored sample, an output of the storage means providing the decoded NRZ signal, B. an exclusive-OR gate, C. a first signal path from an output of the storage means through the exclusive-OR
gate to the clock input of the storage means, D. a second signal path from the source of the encoded signal through the exclusive-OR gate to the clock input of the storage means, and E. a third signal path from the source of the encoded signal to the data input of the storage means, wherein a. the time for a signal to propagate along the first signal path is at least as long as the minimum pulse width required to clock the storage means, and b. wherein the difference between the time for a signal to propagate along the second signal path and the time for a signal to propagate along the third signal path is at least as long as said predetermined time interval, and c. the output signal from the exclusive-OR gate comprises a signal which has exactly one pulse for each data bit.