CA1173927A - Communication system and method - Google Patents
Communication system and methodInfo
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- CA1173927A CA1173927A CA000405695A CA405695A CA1173927A CA 1173927 A CA1173927 A CA 1173927A CA 000405695 A CA000405695 A CA 000405695A CA 405695 A CA405695 A CA 405695A CA 1173927 A CA1173927 A CA 1173927A
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Abstract
Case 04-4270-U.S.-2 APPLICATION OF
FELIX J. HOUVIG AND RONALD H. ROWLANDS
COMMUNICATION SYSTEM AND METHOD
ABSTRACT
A communication system for communicating with a process variable, e.g., pressure, transmitter over the two wires which supply power to the transmitter apparatus.
The communication operation is half-duplex, bit serial transmission and is represented by the currents and voltages in the transmitter communication loop which are selectively introduced between process variable transmissions of 4-20 ma. A plurality of bit cells are provided for each data word or byte between a start bit and a parity bit cell. Following the completion of transmission of the digital data, a predetermined time period is introduced to enable the resumption of transmission of process variable data. Multiple byte transmission can also be effected between process variable transmissions by having a byte spacing less than the predetermined time period.
FELIX J. HOUVIG AND RONALD H. ROWLANDS
COMMUNICATION SYSTEM AND METHOD
ABSTRACT
A communication system for communicating with a process variable, e.g., pressure, transmitter over the two wires which supply power to the transmitter apparatus.
The communication operation is half-duplex, bit serial transmission and is represented by the currents and voltages in the transmitter communication loop which are selectively introduced between process variable transmissions of 4-20 ma. A plurality of bit cells are provided for each data word or byte between a start bit and a parity bit cell. Following the completion of transmission of the digital data, a predetermined time period is introduced to enable the resumption of transmission of process variable data. Multiple byte transmission can also be effected between process variable transmissions by having a byte spacing less than the predetermined time period.
Description
~ ~IL 739~27 ;' The present invention is directed to data communica-tion systems. More specifically, the present invention is directed to a combined analog and digital data communication - system utilizing power supply circuits.
An object of the present invention is to provide an improved data communication system for providing either analog or digital data transmission over power supply circuits.
In accomplishing this and other objects, there has been provided, in accordance with one aspect of the present invention, a data communication system between a transmitter and a communication device utilizing a resistor in the power transmitting circuit for developing a voltage drop. Selective digital communication is achieved by either the transmitter or the communication device by forcing the power circuit current through the resistor to change rapidly between preset limits.
Each change between the limits is used to carry a digital bit of serial digital information in the circuit which bit is - represented by a voltage change produced by a voltage drop across the resistor. Analog data transmission is effected by a power circuit current level representing an analog value be-tween digital communication.
Briefly stated, according to a first broad aspect of the present invention, there is provided a data communication system comprising a power supply, a power supply current cir cuit, a data transmitting means connected to said power supply current circuit for introducing first power supply current variations in said circuit representative of analog data! and second power supply current variations in said circuit repre-sentative of digital data, said first and second current varia-tions being alternate operations and data receiving means con-nected to said circuit for receiving said first and second ...
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current variations.
; According to a second broad aspect of the present invention, there is provided a method for alternate digital and analog data communication comprising the steps of introduciny into a power supply circuit first current variations having values representative of corresponding analog data~ terminating the first current variations, introducing second current vari-ations into the power supply circuit having a variation between preset current limits with each variation representing a digital bit, terminating the second current variations by introducing - a preset delay represented by a fixed preset current level and reinstating the first current variations.
A better understanding of the present invention may be had when the following detailed description is read in .~
~ -2a-~:~'73~Z7 connection with the accompanying drawings, in which:
Figure l is a simplified b10ck diagram of a communication system embodying an example of the present invention, Figure 2 is a waveshape diagram of a first communication format utilized in the circuit of Figure l, Figure 3 is a waveshape diagram of a second communication format utilized in the circuit shown in Figure l, Figure 4 is a waveshape diagram of multi-byte communication format for the circuit shown in Figure l, Figure 5 is a schematic diagram of a circuit suitable for use in the communication~device of Figure 1, Figure 6 is a communication device driver/receiver timing diagram, Figure 7--i-s a block diagram of a transmitter circuit suitable for use in the present invention, Figure 8 is an expanded block diagram of a portion of Figure 5, Figure 9 is a pictorial representation of an example of a communication device, Figure lO is an expanded block diagram of a portion of Figure 7, and Figure ll is an expanded block diagram of the system shown in Figure l.
Referring to Figure l in more detail, there is shown a simplified block diagram of a communication circuit embodying an example of the present invention. A process ` 30 variable transmitter 2 is powered from a direct current power supply 4 through a resistor 6. A communication 3 _ ~ ~ 7 3 g 2 7 `:
device 8 is connected across the power supply lines. The connection of the communication device 8 may be effected at any point along the power supply lines 17 which affords a maximum utility to the communication device ~ since it can be a hand held device having the circuits, data entry keyboard and display thereon, as discussed hereinafter and shown in Figure 9. This system provides a means for enabling the communication device 8 to communicate with the transmitter 2, e.g., a pressure transmitter monitoring pressure in a pipeline, over the two wires which supply power to the transmitter 2. The communication operation is half-duplex, bit serial transmission and is carried by the currents and voltages present in the transmitter loop. The loop circuit resistor 6 has a value of at lS least 250 ohms and is in series with the communication loop. Normally, the process variable (PV) being monitored - by the transmitter, e.g., pressure, produces an analog signal by means of direct currents in the communication loop in a predetermined range, e.g., 4-20 ma. representing process variable analog values. Such 4-20 ma. analog signals are monitored by conventional so-called two-wire data receivers which respond to the current supplied from the power supply 4 to produce an output representative of the ~alue of the process variable as defined by the 4-20 ma. current signal, such devices being well-~nown in the art as shown in U.S. Patent No. 3,562,729 and as discussed hereinafter with respect to Figure 11. This PV signal is disturbed or altered during digital data communication to provide the digital bit transmission. The digital data communicaion is accomplished by forcing the loop current to change rapidly between the preset limits, e.g., 4 ma.
~73~Z7 and 20 ma. This change of the loop current carries the serial digital bit information.
The communication device during the communication operation accepts or "sinks" 16 ma. from the laop for a logical "0" and 0 ma. from the loop for a logical "1".
The transmitter 2 senses this current variation as a drop in voltage across its input/output terminals. This voltage drop occurs because the 16 ma~ drawn by the communication device 8 causes a four volt drop across the resistor 6 in series with the current loop. This voltage drop decreases the voltage across the input/output terminals of the transmitter 6 by four volts. By the use of bandpass filters, the transmitter 2 is sensitive only to voltage variations more rapid than those allowed in analog signal transmissions, i.e., the transmitter 2 sends analog and digital signals but receivès only digital signals.
When the communication device 8 initiates communication with the transmitter 2, the process variable - ~o (PV) current can be anywhere in the range of 4 to 20 ma.
The communication device draws an additional 16 ma. ~rom the loop making the total loop current in the range of 20 to 36 ma. This occurs for only one digital bit time and is used to signal to the transmitter 2 that communication with the transmitter 2 has been initiated. The voltage at the transmitter input terminal will drop by four volts which represents the voltage drop across the resistor 6.
When the transmitter 2 senses the drop in voltage at its input/output terminals, it waits for one bit time and then drops its own current drain from the former process variable level to a new level of 4 ma. This current drop `` ~1739Z7 is matched by a concurrent drop in current drain by the co~munication device 8 from l6 ma. to 0 ma. Total loop current then drops from the range of 20 to 36 ma. down to 4 ma. The transmitter 2 maintains its current drain of 4 ma. until the communication operation is finished. Loop current is varied for each digital bit including the "start" and parity bits from 4 ma. to 20 ma. by the communication device 8. This variation in current is sensed by the transmitter 2 as a drop in voltage across its input/output terminals whereby each digital bit is sensed. When the communication from the communications device 8 to the transmitter 2 is finished, indicated by steady loop current of 4 ma. for a predefined time period (t), the transmitter adjusts its current drain back to the former process variable (PV) level within the range of 4 to 20 ma. This communication format is shown in Figure
An object of the present invention is to provide an improved data communication system for providing either analog or digital data transmission over power supply circuits.
In accomplishing this and other objects, there has been provided, in accordance with one aspect of the present invention, a data communication system between a transmitter and a communication device utilizing a resistor in the power transmitting circuit for developing a voltage drop. Selective digital communication is achieved by either the transmitter or the communication device by forcing the power circuit current through the resistor to change rapidly between preset limits.
Each change between the limits is used to carry a digital bit of serial digital information in the circuit which bit is - represented by a voltage change produced by a voltage drop across the resistor. Analog data transmission is effected by a power circuit current level representing an analog value be-tween digital communication.
Briefly stated, according to a first broad aspect of the present invention, there is provided a data communication system comprising a power supply, a power supply current cir cuit, a data transmitting means connected to said power supply current circuit for introducing first power supply current variations in said circuit representative of analog data! and second power supply current variations in said circuit repre-sentative of digital data, said first and second current varia-tions being alternate operations and data receiving means con-nected to said circuit for receiving said first and second ...
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current variations.
; According to a second broad aspect of the present invention, there is provided a method for alternate digital and analog data communication comprising the steps of introduciny into a power supply circuit first current variations having values representative of corresponding analog data~ terminating the first current variations, introducing second current vari-ations into the power supply circuit having a variation between preset current limits with each variation representing a digital bit, terminating the second current variations by introducing - a preset delay represented by a fixed preset current level and reinstating the first current variations.
A better understanding of the present invention may be had when the following detailed description is read in .~
~ -2a-~:~'73~Z7 connection with the accompanying drawings, in which:
Figure l is a simplified b10ck diagram of a communication system embodying an example of the present invention, Figure 2 is a waveshape diagram of a first communication format utilized in the circuit of Figure l, Figure 3 is a waveshape diagram of a second communication format utilized in the circuit shown in Figure l, Figure 4 is a waveshape diagram of multi-byte communication format for the circuit shown in Figure l, Figure 5 is a schematic diagram of a circuit suitable for use in the communication~device of Figure 1, Figure 6 is a communication device driver/receiver timing diagram, Figure 7--i-s a block diagram of a transmitter circuit suitable for use in the present invention, Figure 8 is an expanded block diagram of a portion of Figure 5, Figure 9 is a pictorial representation of an example of a communication device, Figure lO is an expanded block diagram of a portion of Figure 7, and Figure ll is an expanded block diagram of the system shown in Figure l.
Referring to Figure l in more detail, there is shown a simplified block diagram of a communication circuit embodying an example of the present invention. A process ` 30 variable transmitter 2 is powered from a direct current power supply 4 through a resistor 6. A communication 3 _ ~ ~ 7 3 g 2 7 `:
device 8 is connected across the power supply lines. The connection of the communication device 8 may be effected at any point along the power supply lines 17 which affords a maximum utility to the communication device ~ since it can be a hand held device having the circuits, data entry keyboard and display thereon, as discussed hereinafter and shown in Figure 9. This system provides a means for enabling the communication device 8 to communicate with the transmitter 2, e.g., a pressure transmitter monitoring pressure in a pipeline, over the two wires which supply power to the transmitter 2. The communication operation is half-duplex, bit serial transmission and is carried by the currents and voltages present in the transmitter loop. The loop circuit resistor 6 has a value of at lS least 250 ohms and is in series with the communication loop. Normally, the process variable (PV) being monitored - by the transmitter, e.g., pressure, produces an analog signal by means of direct currents in the communication loop in a predetermined range, e.g., 4-20 ma. representing process variable analog values. Such 4-20 ma. analog signals are monitored by conventional so-called two-wire data receivers which respond to the current supplied from the power supply 4 to produce an output representative of the ~alue of the process variable as defined by the 4-20 ma. current signal, such devices being well-~nown in the art as shown in U.S. Patent No. 3,562,729 and as discussed hereinafter with respect to Figure 11. This PV signal is disturbed or altered during digital data communication to provide the digital bit transmission. The digital data communicaion is accomplished by forcing the loop current to change rapidly between the preset limits, e.g., 4 ma.
~73~Z7 and 20 ma. This change of the loop current carries the serial digital bit information.
The communication device during the communication operation accepts or "sinks" 16 ma. from the laop for a logical "0" and 0 ma. from the loop for a logical "1".
The transmitter 2 senses this current variation as a drop in voltage across its input/output terminals. This voltage drop occurs because the 16 ma~ drawn by the communication device 8 causes a four volt drop across the resistor 6 in series with the current loop. This voltage drop decreases the voltage across the input/output terminals of the transmitter 6 by four volts. By the use of bandpass filters, the transmitter 2 is sensitive only to voltage variations more rapid than those allowed in analog signal transmissions, i.e., the transmitter 2 sends analog and digital signals but receivès only digital signals.
When the communication device 8 initiates communication with the transmitter 2, the process variable - ~o (PV) current can be anywhere in the range of 4 to 20 ma.
The communication device draws an additional 16 ma. ~rom the loop making the total loop current in the range of 20 to 36 ma. This occurs for only one digital bit time and is used to signal to the transmitter 2 that communication with the transmitter 2 has been initiated. The voltage at the transmitter input terminal will drop by four volts which represents the voltage drop across the resistor 6.
When the transmitter 2 senses the drop in voltage at its input/output terminals, it waits for one bit time and then drops its own current drain from the former process variable level to a new level of 4 ma. This current drop `` ~1739Z7 is matched by a concurrent drop in current drain by the co~munication device 8 from l6 ma. to 0 ma. Total loop current then drops from the range of 20 to 36 ma. down to 4 ma. The transmitter 2 maintains its current drain of 4 ma. until the communication operation is finished. Loop current is varied for each digital bit including the "start" and parity bits from 4 ma. to 20 ma. by the communication device 8. This variation in current is sensed by the transmitter 2 as a drop in voltage across its input/output terminals whereby each digital bit is sensed. When the communication from the communications device 8 to the transmitter 2 is finished, indicated by steady loop current of 4 ma. for a predefined time period (t), the transmitter adjusts its current drain back to the former process variable (PV) level within the range of 4 to 20 ma. This communication format is shown in Figure
2.
When the digital communication operation occurs from the (PV) transmitter 2 to the communication device 8, the ~o transmitter 2 forces its current drain to increase from the process variable level, e.g., the range of 4 to 20 ma.
to 20 ma. It holds this current level for one bit time, then drops the current level to 4 ma. This latter level is also held for one bit time after which the information transmission starts with a "start" bit. Digital communication from the transmitter 2 to the communication device 8 continues with the loop current being varied by the transmitter 2 between 4 ma. and 20 ma. for each digital bit until the communication operation is completed. Completion of the communication operation occurs when the loop current is held steady at 4 ma. for a 39~7 prede~ined time period (t) after which the transmitter 2 adjusts the loop current back to the former process variable level, e.g., the range of 4 to 20 ma. This communication format is shown in Figure 3.
The time between before the start bit period as shown in Figures 2 and 3 is a "signalling bit" which precedes the normal process variable transmission format of a "start bit", 8 data bits, parity bit and stop bit as shown in the communication waveshape format of Figures 2 and
When the digital communication operation occurs from the (PV) transmitter 2 to the communication device 8, the ~o transmitter 2 forces its current drain to increase from the process variable level, e.g., the range of 4 to 20 ma.
to 20 ma. It holds this current level for one bit time, then drops the current level to 4 ma. This latter level is also held for one bit time after which the information transmission starts with a "start" bit. Digital communication from the transmitter 2 to the communication device 8 continues with the loop current being varied by the transmitter 2 between 4 ma. and 20 ma. for each digital bit until the communication operation is completed. Completion of the communication operation occurs when the loop current is held steady at 4 ma. for a 39~7 prede~ined time period (t) after which the transmitter 2 adjusts the loop current back to the former process variable level, e.g., the range of 4 to 20 ma. This communication format is shown in Figure 3.
The time between before the start bit period as shown in Figures 2 and 3 is a "signalling bit" which precedes the normal process variable transmission format of a "start bit", 8 data bits, parity bit and stop bit as shown in the communication waveshape format of Figures 2 and
3. This l'signalling bit" is used only at the beginning of a transmission in either direction. If a particular transmission requires more than one byte of data, the bytes are transmitted one immediately after the next without a time delay (t) therebetween until the communication operation is completed as shown in figure 4 for the communication operation between the transmitter 2 and the communication device 8.
. In Figure 5, there is shown a circuit schematic forthe implementation of the communication link in the ~o communication device 8. There are three basic sections in the circuit shown in Figure 5, the communications controller which includes a microprocessor, i.e., CPU, lO
and its associated circuits connected by a digital signal line ll to a parallel to serial converter and timing 2; circuit or universal asynchronous receiver transmitter (UART) 12, a current driver circuit 26 consisting of an attenuator/filter, a pulse width modulator including an operational amplifier and a power output transistor and a current receiver circuit 24 consisting of an input protection network, a filter and a comparator. The CPU's discussea herein for use in the transmitter 2 and ~ ~73~7 communication device 8 may include a conven-tional microprocessor having program and data memories. The reading of stored data, the storing of incoming data, the use of stored programs or algorithms in the microprocessor memory, the use of address and data busses anb tne operation of logic circuits in the CPU are conventional digital computer techniques performed by known CPU or microprocessor products. Further, the writing of programs or routines including microprogram and branching routines for directing the CPU operation to achieve desired CPU
functions to provide output signals for associated hardware systems is also well-known in the art.
Accordin~ly, further elaboration of the details of these known techniques beyond the discussion herein is believed to be unnecessary for a full understanding of tne present invention.
The CPU 10 has a "Tx Enable" output applied as one input to a two input NAND gate 14. A second input for the NAND gate 14 is obtained from the SDO (Serial data out) output of the UART 12.
The output of the NAND gate is applied through a resistor network Rl R2 and R3 to the non-inverting input of a first operational amplifier 16 and to one side of a first capacitor Cl having its other siae connected to ground. A feedback signal resistor R5 is connected at one end to the inverting input of the amplifier 16.
The output of the first amplifier 16 is connected through a resistor R6 to the gate electrode of a field effect transistor (FET 1). One electrode of the FET 1 is connected through a resistor R4 to the output terminals 17 while the other electrode of the FET 1 is connected ~ ~73~Z7 through a resist~r R7 to the other one of the output terminals 17.
Additionally one of the output terminals 17 is connected to ground while the other one is connected through a filter circuit including a resistor R8 and a capacitor C2 to circuit node between a pair of oppositely poled diodes Dl and D2. The other sides of the diodes Dl and D2 are connected to ground and to a positive source, +V, respectively. The circuit node between the diodes Dl, D2 is connected through a resistor R12 to the inverting input of a second . operational amplifier 18 and through a resistor R13 to the positive so~rce +V. The non-inverting input of the amplifier 18 is connected to its outpl~t through a feedback lS network of resistor Rg and Rlo while a resistor Rll connects the input to a source +V and forms a voltage divider with Rg across the source +V. The output of the amplifier 18 is also connected as a second input to the NAND gate 20 and as an input to the CPU 10 as an RXD
signal. The first input of the NAND gate 20 is connecte~
to the CPU 10 to receive an "RX enable" input. The output of the NAND gate 20 supplies an SDI (Serial Data In) input to the UART 12. It should be noted that for purposes of ` simplifying the illustration of Figure 5, digital memory elements for the CPU 10, external CPU inputs, synchronizing clock signals for the CPU 10 and UART 12 and digital displays for the CPU 10 have been omitte~. While such operational details are well-known to those skilled in the art and their specific inclusion is believed to be unnecessary for a complete understanding of the present invention, a more complete block diagram is shown in ~ .~'73g;27 Figure 8.
The driver circuit 26 operates ~y utilizing the "signaling bit" which is generated directly by the preprogrammed microprocessor CPU 10 by using the "TX
enable" output signal. This CPU output signal is set to a logical "O" which is summed by the NAND gate 14 with the "SDO" output signal from the U.A.R.T. 12 to generate a ! logic 1 at the output of the NAND gate 14. This output signal, in turn, causes the operational amplifier 16 to adjust the current flowing through the FET 1 so that the voltage drop across the resistor R4 is equal to 2/5 of the voltage at the gate 14 output, e.g., about 2 volts.
This operation results in a current flow of about 16 ma.
through the FET 1. This current is drawn directly from lS the transmitter loop current and is seen by the transmitter as a drop in voltage across its terminals as previously described. The microprocessor then sets the "TX enable" signal to a logic 1 level which causes the current in the current loop to decrease as the current flowing through the FET 1 drops to zero. The microprocessor 10 then loads the first byte to be tr~nsmitted into the U.A.R.T. 12 which converts the byte to serial digital data, appends a start, parity and stop bits and transmits the serial bits via the "SDO" output to the NAND gate 14. This signal transmission ultimately causes the communication loop current, by means of the FET 1 to vary as shown in Figure 6. The variation of the loop current is effected for each bit of serial information being transmitted to the transmitter 2 until the microprocessor 10 reaches the end of its data store.
" The receiver 24 operates to receive information for .
~739~
the communication device 8 from the system. Since the communication is controlled by the communication device 8 once the communication device 8 has started a transmission it expects to always detect a response. Once the communication from the communicat on device 8 to the transmitter 2 is completed, the microprocessor 10 in the communication device 8 monitors the "RXD" signal from the receiver circult 24. Specifically, the microprocessor 10 detects the transition from 20 ma. to 4 ma. ~hich occurs after the initial change from 4 ma. to 20 ma. The micro-processor 10, then, is alerted to the fact that the one bit time later the "start" bit will be supplied and the microprocessor 10 can proceed to enable the receiver 24 by setting the RXD enable bit to a logical 1. This signal is lS combined by the NAND gate 20 with the RXD signal from the receiver 24 to generate the correct logic level and polarity for the "SDI" input at the UART 12. The start bit is then received from the transmitter 2 and transmission of the digital data from the transmitter 2 ~0 commences. After the parity bit is transmitted, the communication is completed at a "Stop" bit wherein the loop current is reduced to 4 ma. The transmitter 2 after waiting for a preset time "t" adjusts the loop current back to the applicable process variable current level to produce the normal 4 ma. to ZO ma process variable data signals for transmission from the transmitter 2. A timing diagram for the operation of the communication device 8 is shown in Figure 6.
A block diagram for the transmitter driver/receiver circuits is shown in Figure 7. The receiver section for the transmitter 2 is a similar circuit to the receiver 24 , ` ~73~27 found in the communication device 8 and functions in a similar manner. The driver section for the transmitter 2 is an addition to the 4 to 20 ma. analog current (PVj controller 26 which is already present in the transmitter system in a conventional fashion to control the process variable output current. To make this circuit functian as a digital signal transmitter, the time constant of the output circuit is altered by the switching of a capacitor. In other words, the process variable output is 1q the average of a pulse-width modulated output of the D/A
converter 31 as averaged by an output capacitor. To provide a rapid digital output variation, the output capacitor is switched out of the circuit to allow high speed current changes. The switching is controlled by a CPU 22 in the transmitter 2 connected to a UART 23 having an SDO output and an SDI input. The SDI input is connected to a receiver circuit 24 arranged as mentioned above and used to receive the digital communications from the communications device 8 and to disregard the output of a 4 to 20 ma. current controller 24 connected to the output terminals 17. The SDO output of the UART 23 is connected to one input of a two input exclusive OR gate 28. A second input for the NAND gate 28 is applied from the CPU 22. The output of the OR gate 28 is applied to one contact of a single pole, double throw switch 30. The other contact of the switch 30 is connected to the output of a O/A converter 31. The switch arm of the switch 30 is connected to a control input of the current controller 26. A second switch 32 which is a single pole, single 3~ switch, is used to connect a time constant capacitor 34 to the current controller 26. The switches 30 and 32 are .`;
~ - 12 ~ .
~39~:~
concurrently operated by the CPU 22 for either analog (P~/) or digital signal transmission by the transmitter 2. The ; block diagram illustration shown in Figure 7 has, as in the case o~ Figure 5, been simpli~ied to omit conventional ` 5 details such as external CPU inputs including a process variable sensor, CPU memory devices and clock signals for synchronizing the CPU 22 and UART 23. Such details are shown in Figure lO and discussed hereinafter althought it is believed that their specific inclusion is unnecessary for a complete understanding of the present invention.
The control signal input to current controller 26 is switched from the D/A converter 3l output to the UART 23 SDO output signal by the CPU 22 for digital cGmmunication. In series with this SDO output signal is the exclusive OR gate 28 which allows for generation of a "signalling bit" under control of the microprocessor 22.
The time constant capacitor 34 which is switched out for digital communications by the switch, stores a value proportional to the last process variable current of the 4 ~o to 20 ma. type signal. When digital communications are completed, the capacitor 34 is switched back into the circuit by the switch 32 and the process variable (PV) current transmission is restored with minimal settling time of the system.
The following is a detailed list of the circuit components used in a preferred construction of the illustrated example of the present invention as shown in Figures S and 7:
CPU lO, 22 - RCA - Type l802 UART l2, 23 - RCA - Type l854 Rl - 30K ohms .
.~
~-~73~Z7 R2, R5, R6 - lOK ohms R3 - 20K ohms R4 ~ 124 ohms R7 312 ohms R8 - 1 K ohms Rg~ Rll - 250 ohms Rlo - 750 ohms R12 ~ 100 ohms 12 ~ 100 ohms R13 lM ohms 1~ D2 - lN4004 Cl - .ol.,q f C2 ~ .47~ f C3 ~ .0047.~ f C34 ~ 2.~mf Amp 16, 18 - ICL 7641 - Intersil NAND 14, 20 - Type 4011 - RCA
Exclusive OR 28 - Type 4030 - RCA
~V - 5V in series with 62 ohms FET 1 - VN98 - Intersil As shown in Figure 8, the communications device 8 may ~- include a keyboard 42 ~or supplying digital signals to the ~- CPU 10. Such digital signals and other digital data including stored programs may be stored in memory devices such as a RAM 42 and a ROM 44. The CPU 10 may also be arranged to operate a display 46 for displaying digital ~' signals present during its operation. A pictorial \: representation of a communications device 8 is shown in ~, Figure 9. As shown in the communications device 8 ;~ 30 includes a hand hela housing 50 having a display window 52 and selectively operable pushbuttons 54. The housing .:~
~39Z'7 :` includes a connection cable 56 which is arranged to be selectively connected to the communication lines 17 shown in Figure 1. The elements discussed above' with respect to Figures 5 and 8 would be found within the housing 50 to form the communications device 8. As shown in Figure 10, the transmitter 2 would include memory sources such as a ROM 60 and a RAM ~2 for the CPU 22. The storage devices may include digital data received over the communication line 17 as well as prestored programs and data to be used by the CPU 22. An external input to the CPU 22 incluaes a sensor 64 arranged to sense a process variable to be monitored and an A to D converter 66 for converting analog output of the sensor to a digital signal suitable for application to the CPU 22. A clock source 68 is arranged lS to synchronize the operation of the CPU 22 and the UART
23. In Figure 11, there is shown an expanded representation of the communication system shown ih Figure 1 to include an output representative of the analog signals developed across the resistor 6 in the communication lines 17. This analog signal is applied to and A to O converter over input lines connected across the resistor 6. The output of the A to D converter 70 is applied to subsequent utilization devices such as display 74. Thus, the communication of the analog signal is effected over the same lines used to supply power from the power supply 4 to the transmitter 2 and the communication ; device 8.
This method of implementing a 4 to 20 ma.
communications link for sending either analog process `~ 30 variable signals or digital signals utilizing the ; signalling protocols and circuits described herein ~` presents a cost effective and inherently more accurate and :~"
: , .
~ L73~'7 simplified method for interfacing a microprocessor based sensing instrument to a communication device 8. Such a sys~em by adding the digital communication capability upgrades the conventional analog 4 to 20 ma. systems, which are limited by their analog nature to .1% accuracy, to systems, which by virtue of their added capabilities, provide computation and control accuracy limited only by the digital accuracy resolution of the sensor being monitored by the transmitter 2.
lO Accordingly, it may be seen, that there has been provided, in accordance with the present invention~ an improved communication system having analog and digital signal transmission capabilities.
. In Figure 5, there is shown a circuit schematic forthe implementation of the communication link in the ~o communication device 8. There are three basic sections in the circuit shown in Figure 5, the communications controller which includes a microprocessor, i.e., CPU, lO
and its associated circuits connected by a digital signal line ll to a parallel to serial converter and timing 2; circuit or universal asynchronous receiver transmitter (UART) 12, a current driver circuit 26 consisting of an attenuator/filter, a pulse width modulator including an operational amplifier and a power output transistor and a current receiver circuit 24 consisting of an input protection network, a filter and a comparator. The CPU's discussea herein for use in the transmitter 2 and ~ ~73~7 communication device 8 may include a conven-tional microprocessor having program and data memories. The reading of stored data, the storing of incoming data, the use of stored programs or algorithms in the microprocessor memory, the use of address and data busses anb tne operation of logic circuits in the CPU are conventional digital computer techniques performed by known CPU or microprocessor products. Further, the writing of programs or routines including microprogram and branching routines for directing the CPU operation to achieve desired CPU
functions to provide output signals for associated hardware systems is also well-known in the art.
Accordin~ly, further elaboration of the details of these known techniques beyond the discussion herein is believed to be unnecessary for a full understanding of tne present invention.
The CPU 10 has a "Tx Enable" output applied as one input to a two input NAND gate 14. A second input for the NAND gate 14 is obtained from the SDO (Serial data out) output of the UART 12.
The output of the NAND gate is applied through a resistor network Rl R2 and R3 to the non-inverting input of a first operational amplifier 16 and to one side of a first capacitor Cl having its other siae connected to ground. A feedback signal resistor R5 is connected at one end to the inverting input of the amplifier 16.
The output of the first amplifier 16 is connected through a resistor R6 to the gate electrode of a field effect transistor (FET 1). One electrode of the FET 1 is connected through a resistor R4 to the output terminals 17 while the other electrode of the FET 1 is connected ~ ~73~Z7 through a resist~r R7 to the other one of the output terminals 17.
Additionally one of the output terminals 17 is connected to ground while the other one is connected through a filter circuit including a resistor R8 and a capacitor C2 to circuit node between a pair of oppositely poled diodes Dl and D2. The other sides of the diodes Dl and D2 are connected to ground and to a positive source, +V, respectively. The circuit node between the diodes Dl, D2 is connected through a resistor R12 to the inverting input of a second . operational amplifier 18 and through a resistor R13 to the positive so~rce +V. The non-inverting input of the amplifier 18 is connected to its outpl~t through a feedback lS network of resistor Rg and Rlo while a resistor Rll connects the input to a source +V and forms a voltage divider with Rg across the source +V. The output of the amplifier 18 is also connected as a second input to the NAND gate 20 and as an input to the CPU 10 as an RXD
signal. The first input of the NAND gate 20 is connecte~
to the CPU 10 to receive an "RX enable" input. The output of the NAND gate 20 supplies an SDI (Serial Data In) input to the UART 12. It should be noted that for purposes of ` simplifying the illustration of Figure 5, digital memory elements for the CPU 10, external CPU inputs, synchronizing clock signals for the CPU 10 and UART 12 and digital displays for the CPU 10 have been omitte~. While such operational details are well-known to those skilled in the art and their specific inclusion is believed to be unnecessary for a complete understanding of the present invention, a more complete block diagram is shown in ~ .~'73g;27 Figure 8.
The driver circuit 26 operates ~y utilizing the "signaling bit" which is generated directly by the preprogrammed microprocessor CPU 10 by using the "TX
enable" output signal. This CPU output signal is set to a logical "O" which is summed by the NAND gate 14 with the "SDO" output signal from the U.A.R.T. 12 to generate a ! logic 1 at the output of the NAND gate 14. This output signal, in turn, causes the operational amplifier 16 to adjust the current flowing through the FET 1 so that the voltage drop across the resistor R4 is equal to 2/5 of the voltage at the gate 14 output, e.g., about 2 volts.
This operation results in a current flow of about 16 ma.
through the FET 1. This current is drawn directly from lS the transmitter loop current and is seen by the transmitter as a drop in voltage across its terminals as previously described. The microprocessor then sets the "TX enable" signal to a logic 1 level which causes the current in the current loop to decrease as the current flowing through the FET 1 drops to zero. The microprocessor 10 then loads the first byte to be tr~nsmitted into the U.A.R.T. 12 which converts the byte to serial digital data, appends a start, parity and stop bits and transmits the serial bits via the "SDO" output to the NAND gate 14. This signal transmission ultimately causes the communication loop current, by means of the FET 1 to vary as shown in Figure 6. The variation of the loop current is effected for each bit of serial information being transmitted to the transmitter 2 until the microprocessor 10 reaches the end of its data store.
" The receiver 24 operates to receive information for .
~739~
the communication device 8 from the system. Since the communication is controlled by the communication device 8 once the communication device 8 has started a transmission it expects to always detect a response. Once the communication from the communicat on device 8 to the transmitter 2 is completed, the microprocessor 10 in the communication device 8 monitors the "RXD" signal from the receiver circult 24. Specifically, the microprocessor 10 detects the transition from 20 ma. to 4 ma. ~hich occurs after the initial change from 4 ma. to 20 ma. The micro-processor 10, then, is alerted to the fact that the one bit time later the "start" bit will be supplied and the microprocessor 10 can proceed to enable the receiver 24 by setting the RXD enable bit to a logical 1. This signal is lS combined by the NAND gate 20 with the RXD signal from the receiver 24 to generate the correct logic level and polarity for the "SDI" input at the UART 12. The start bit is then received from the transmitter 2 and transmission of the digital data from the transmitter 2 ~0 commences. After the parity bit is transmitted, the communication is completed at a "Stop" bit wherein the loop current is reduced to 4 ma. The transmitter 2 after waiting for a preset time "t" adjusts the loop current back to the applicable process variable current level to produce the normal 4 ma. to ZO ma process variable data signals for transmission from the transmitter 2. A timing diagram for the operation of the communication device 8 is shown in Figure 6.
A block diagram for the transmitter driver/receiver circuits is shown in Figure 7. The receiver section for the transmitter 2 is a similar circuit to the receiver 24 , ` ~73~27 found in the communication device 8 and functions in a similar manner. The driver section for the transmitter 2 is an addition to the 4 to 20 ma. analog current (PVj controller 26 which is already present in the transmitter system in a conventional fashion to control the process variable output current. To make this circuit functian as a digital signal transmitter, the time constant of the output circuit is altered by the switching of a capacitor. In other words, the process variable output is 1q the average of a pulse-width modulated output of the D/A
converter 31 as averaged by an output capacitor. To provide a rapid digital output variation, the output capacitor is switched out of the circuit to allow high speed current changes. The switching is controlled by a CPU 22 in the transmitter 2 connected to a UART 23 having an SDO output and an SDI input. The SDI input is connected to a receiver circuit 24 arranged as mentioned above and used to receive the digital communications from the communications device 8 and to disregard the output of a 4 to 20 ma. current controller 24 connected to the output terminals 17. The SDO output of the UART 23 is connected to one input of a two input exclusive OR gate 28. A second input for the NAND gate 28 is applied from the CPU 22. The output of the OR gate 28 is applied to one contact of a single pole, double throw switch 30. The other contact of the switch 30 is connected to the output of a O/A converter 31. The switch arm of the switch 30 is connected to a control input of the current controller 26. A second switch 32 which is a single pole, single 3~ switch, is used to connect a time constant capacitor 34 to the current controller 26. The switches 30 and 32 are .`;
~ - 12 ~ .
~39~:~
concurrently operated by the CPU 22 for either analog (P~/) or digital signal transmission by the transmitter 2. The ; block diagram illustration shown in Figure 7 has, as in the case o~ Figure 5, been simpli~ied to omit conventional ` 5 details such as external CPU inputs including a process variable sensor, CPU memory devices and clock signals for synchronizing the CPU 22 and UART 23. Such details are shown in Figure lO and discussed hereinafter althought it is believed that their specific inclusion is unnecessary for a complete understanding of the present invention.
The control signal input to current controller 26 is switched from the D/A converter 3l output to the UART 23 SDO output signal by the CPU 22 for digital cGmmunication. In series with this SDO output signal is the exclusive OR gate 28 which allows for generation of a "signalling bit" under control of the microprocessor 22.
The time constant capacitor 34 which is switched out for digital communications by the switch, stores a value proportional to the last process variable current of the 4 ~o to 20 ma. type signal. When digital communications are completed, the capacitor 34 is switched back into the circuit by the switch 32 and the process variable (PV) current transmission is restored with minimal settling time of the system.
The following is a detailed list of the circuit components used in a preferred construction of the illustrated example of the present invention as shown in Figures S and 7:
CPU lO, 22 - RCA - Type l802 UART l2, 23 - RCA - Type l854 Rl - 30K ohms .
.~
~-~73~Z7 R2, R5, R6 - lOK ohms R3 - 20K ohms R4 ~ 124 ohms R7 312 ohms R8 - 1 K ohms Rg~ Rll - 250 ohms Rlo - 750 ohms R12 ~ 100 ohms 12 ~ 100 ohms R13 lM ohms 1~ D2 - lN4004 Cl - .ol.,q f C2 ~ .47~ f C3 ~ .0047.~ f C34 ~ 2.~mf Amp 16, 18 - ICL 7641 - Intersil NAND 14, 20 - Type 4011 - RCA
Exclusive OR 28 - Type 4030 - RCA
~V - 5V in series with 62 ohms FET 1 - VN98 - Intersil As shown in Figure 8, the communications device 8 may ~- include a keyboard 42 ~or supplying digital signals to the ~- CPU 10. Such digital signals and other digital data including stored programs may be stored in memory devices such as a RAM 42 and a ROM 44. The CPU 10 may also be arranged to operate a display 46 for displaying digital ~' signals present during its operation. A pictorial \: representation of a communications device 8 is shown in ~, Figure 9. As shown in the communications device 8 ;~ 30 includes a hand hela housing 50 having a display window 52 and selectively operable pushbuttons 54. The housing .:~
~39Z'7 :` includes a connection cable 56 which is arranged to be selectively connected to the communication lines 17 shown in Figure 1. The elements discussed above' with respect to Figures 5 and 8 would be found within the housing 50 to form the communications device 8. As shown in Figure 10, the transmitter 2 would include memory sources such as a ROM 60 and a RAM ~2 for the CPU 22. The storage devices may include digital data received over the communication line 17 as well as prestored programs and data to be used by the CPU 22. An external input to the CPU 22 incluaes a sensor 64 arranged to sense a process variable to be monitored and an A to D converter 66 for converting analog output of the sensor to a digital signal suitable for application to the CPU 22. A clock source 68 is arranged lS to synchronize the operation of the CPU 22 and the UART
23. In Figure 11, there is shown an expanded representation of the communication system shown ih Figure 1 to include an output representative of the analog signals developed across the resistor 6 in the communication lines 17. This analog signal is applied to and A to O converter over input lines connected across the resistor 6. The output of the A to D converter 70 is applied to subsequent utilization devices such as display 74. Thus, the communication of the analog signal is effected over the same lines used to supply power from the power supply 4 to the transmitter 2 and the communication ; device 8.
This method of implementing a 4 to 20 ma.
communications link for sending either analog process `~ 30 variable signals or digital signals utilizing the ; signalling protocols and circuits described herein ~` presents a cost effective and inherently more accurate and :~"
: , .
~ L73~'7 simplified method for interfacing a microprocessor based sensing instrument to a communication device 8. Such a sys~em by adding the digital communication capability upgrades the conventional analog 4 to 20 ma. systems, which are limited by their analog nature to .1% accuracy, to systems, which by virtue of their added capabilities, provide computation and control accuracy limited only by the digital accuracy resolution of the sensor being monitored by the transmitter 2.
lO Accordingly, it may be seen, that there has been provided, in accordance with the present invention~ an improved communication system having analog and digital signal transmission capabilities.
Claims (10)
1. A data communication system comprising a power supply, a power supply current circuit, a data transmitting means connected to said power supply current circuit for introducing first power supply current variations in said circuit representative of analog data, and second power supply current variations in said circuit representative of digital data, said first and second current variations being alternate operations and data receiving means connected to said circuit for receiving said first and second current variations.
2. A data communication system as set forth in Claim 1 wherein said first current variations are each a current value representative of a corresponding analog quantity and said second current variations are each a variation between preset current limits to represent a digital bit.
3. A communication system as set forth in Claim 2 wherein said first and second current variations are between the same current limits.
4. A communication system as set forth in Claim 1 wherein said transmitting means and said receiving means are connected in parallel across said circuit to receive power therefrom.
5. A communication system as set forth in Claim 1 wherein said first and second current variations are separated by a fixed time.
6. A communication system as set forth in Claim 1 wherein said circuit includes a fixed resistor for introducing voltage drops thereacross in response to said first and second current variations.
7. A communication system as set forth in Claim 1 wherein said transmitting means and said receiving means include a preprogrammed microprocessor for controlling said first and second current variations.
8. A communication system as set forth in Claim 1 and further including a second transmitting means for introducing said first and second current variations and second receiving means for receiving said first and second current variations.
9. A method for alternate digital and analog data -communication comprising the steps of introducing into a power supply circuit first current variations having values representative of corresponding analog data, terminating the first current variations, introducing second current variations into the power supply circuit having a variation between preset current limits with each variation representing a digital bit, terminating the second current variations by introducing a preset delay represented by a fixed preset current level and reinstating the first current variations.
10. A method as set forth in Claim 9 wherein multiple bytes of digital bits are transmitted by having a delay less than the preset delay between bytes.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/317,083 US4520488A (en) | 1981-03-02 | 1981-11-02 | Communication system and method |
| US317,083 | 1981-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1173927A true CA1173927A (en) | 1984-09-04 |
Family
ID=23232038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000405695A Expired CA1173927A (en) | 1981-11-02 | 1982-06-22 | Communication system and method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS5885649A (en) |
| CA (1) | CA1173927A (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60119139A (en) * | 1983-11-30 | 1985-06-26 | Yokogawa Hokushin Electric Corp | Two-wire transmission unit |
| JPS60249441A (en) * | 1984-05-24 | 1985-12-10 | Yokogawa Hokushin Electric Corp | Two-wire data transmission equipment |
| JPH0744488B2 (en) * | 1984-12-07 | 1995-05-15 | 横河電機株式会社 | Two-wire data transmission device |
| US4607247A (en) * | 1985-08-12 | 1986-08-19 | The Babcock & Wilcox Company | On-line serial communication interface from a transmitter to a current loop |
| US4816703A (en) * | 1985-08-12 | 1989-03-28 | The Babcock & Wilcox Company | On-line serial communication interface from a current loop to a computer and/or terminal |
| US4729125A (en) * | 1985-08-12 | 1988-03-01 | The Babcock & Wilcox Company | On-line serial communication interface to a transmitter from a current loop |
| JPS6264804A (en) * | 1985-09-05 | 1987-03-23 | Yokogawa Electric Corp | Signal transmitter |
| JP2735174B2 (en) * | 1985-10-16 | 1998-04-02 | 株式会社日立製作所 | 2-wire communication method |
| JPS6295485A (en) * | 1985-10-22 | 1987-05-01 | Omron Tateisi Electronics Co | Detecting sensor device |
| JPS62213439A (en) * | 1986-03-14 | 1987-09-19 | Yamatake Honeywell Co Ltd | Communication system |
| JPS63167595A (en) * | 1986-12-27 | 1988-07-11 | Hitachi Ltd | Duplicated communicator |
| JPS63314700A (en) * | 1987-06-17 | 1988-12-22 | Yokogawa Electric Corp | Two-wire type pulse transmission system |
| JPH0633723Y2 (en) * | 1987-09-03 | 1994-08-31 | 山武ハネウエル株式会社 | Communication device |
| JPH01156418U (en) * | 1988-04-21 | 1989-10-27 | ||
| JPH0650555B2 (en) * | 1989-02-09 | 1994-06-29 | 株式会社日立製作所 | 4-wire field instrument device and its communication method |
| JP2580343B2 (en) * | 1989-10-13 | 1997-02-12 | 株式会社日立製作所 | Field instrument system and communicator |
| JP2007139793A (en) * | 2006-12-25 | 2007-06-07 | Hitachi Ltd | Gas flowmeter |
| DE102008041030A1 (en) * | 2008-08-06 | 2010-02-11 | Robert Bosch Gmbh | Device and method for detecting a measured variable |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS524209B2 (en) * | 1971-05-15 | 1977-02-02 | ||
| JPS50156463A (en) * | 1974-06-07 | 1975-12-17 | ||
| JPS5238807A (en) * | 1975-09-22 | 1977-03-25 | Hitachi Ltd | Signal transmission unit |
| JPS567588A (en) * | 1979-06-30 | 1981-01-26 | Matsushita Electric Works Ltd | Remote control unit for time sharing multiplex transmission |
-
1982
- 1982-06-22 CA CA000405695A patent/CA1173927A/en not_active Expired
- 1982-11-02 JP JP57193277A patent/JPS5885649A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0447358B2 (en) | 1992-08-03 |
| JPS5885649A (en) | 1983-05-23 |
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