CA1172701A - Data transceiving modem - Google Patents

Data transceiving modem

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Publication number
CA1172701A
CA1172701A CA000352494A CA352494A CA1172701A CA 1172701 A CA1172701 A CA 1172701A CA 000352494 A CA000352494 A CA 000352494A CA 352494 A CA352494 A CA 352494A CA 1172701 A CA1172701 A CA 1172701A
Authority
CA
Canada
Prior art keywords
data
modem
output
input terminal
nand gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000352494A
Other languages
French (fr)
Inventor
George A. Bowman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of CA1172701A publication Critical patent/CA1172701A/en
Expired legal-status Critical Current

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Abstract

ABSTRACT
A modem is disclosed for transmitting and receiving digital information having an oscillator and a switch connected to both the oscillator and to a data input signal for switchably controlling the oscillator to impress data on a transmission channel and a receiver also connected to the transmission channel for receiving data thereon to demodulate the data and supply it to a processor. The oscillator may be comprised of a ceramic filter and the switch may be connected through a ceramic filter to the transmission channel which filters are matched for supplying a predetermined frequency to the channel. A blocking cir-cuit may also be provided having a delay connected to a data input terminal so that the modem will block any data which it has transmitted.

Description

~17~

DATA TRANSCEIVI~G MODEM
.
BACKGROUND OF THE INVENTION
The present invention relates to modems ~or trans-mitting and receiving data over a transmission channel and, more particularly, to a simple and inexpensive modem which will make feasible the low cost transmission of such data.
As opposed to twisted pair or wireless transmis-sion channels, a coaxial transmission channel offers greater noise immunity, greater enhanced capacity, self-powering capability, stability, single entity distribution, and the possibility of coexistent multi-purpose modulation schemes.
Coaxial transmission channel allocations are not s~bject to governmental regulations as are wireless transmission channels and they require less circuit complexity and result in improved security from interference in eavesdropping. To achieve thesè~advantages of coaxial transmission channels, however, it is necessary to p~eserve cable environmental intesrity, reliability and data transmission transparency from interference.
As the data processing and transmission industry seeks a universal transmission medium, there must be consid-ered such diverse criteria as topology, reliability, integ-rity, security, safety, flexibility, standards, environment, functionality, redundancy, and, perhaps the most im~portant, cost. Recent integration of RF circuitry which allow both adequate performance and cost ef~ectiveness have provided the building blocks which can be used to make reliable, low cost, universal modems.
Thus, the modem according to the present invention is comprised of only three active integrated circuits ~ the transmitter, the -~22~-~W~-, and the switch/interface network.

This modem acts as a half-duplex transparent medium between " ~727~

peripheral devices over the coaxial transmission line. The data is preserved as an envelope on the RF waveform without the condi-tioning of Manchester, diphase or any additional error correcting codes.
Summary of the Invention The modem for transmitting and receiving digital infor-mation according to the present invention includes a data input terminal for receiving data to be transmitted, a channel terminal for supplying data to a transmission channel, an oscillator, a switch connected to both the data input terminal and the oscilla-tor for modulating data for supply to the transmission channe.l, a data output terminal for supplying received data to a processor or the like, and a receiver connected to the channel terminal and to the data output terminal for demodulating the received data and supplying the demodulated received data to the data output termin-al.
In accordance with the present invention, there is pro-vided a modem for transmitting and receiving digital information comprising data input terminal means for receiving digital data to be transmitted; channel terminal means for supplying digital data to a transmission channel; an oscillator providing an oscil-: lator output signal; switch means connected to said data input .
terminal means, said oscillator and said channel terminal means .- for modulating said oscillator output signal and for connecting said digital data to said channel terminal means; data output terminal means for supplying received digital data; and, receiver means connected to said channel terminal means and to said data output terminal means for demodulating said received digital data and supplying said demodulated received digital da-ta to said data :~ 30 output terminal means.
In accordance with the present invention, there is fur-ther provided a modem for transmitting and receiving digital in-~ ~7~7~ ~
formation having only three active integrated circuits consistingof a transmitter having an oscillator connected thereto which is modulated by said digital information, a receiver having a demod-ulator therein for demodulating received digital data, and a switch/interface means connecting a data input terminal to said transmitter, said switch/interface means connecting said trans-mitter to a channel terminal for transmitting digital data over a transmission medium, and means connecting said channel terminal to said receiver for demodulating said received digital data, said switch/interface means connecting said receiver to a data output terminal.
Brief Description of the ~rawinqs These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the single figure of the drawing which shows the modem according to the present invention.
Detailed Description The modem shown in the drawing comprises basically three active integrated circuits - the transmitter 10 in the form of a 74LS04 hex inverter, a receiver 20 in the form of a TDA440 AM re-ceiver, and switch/interface 30 in the form of a 74LS00 quad NAND
gate. Data input terminal ll receives data to be transmitted and is connected through resistor 12 and through two series connected buffer inverters 13 and 14 to one input of NAND gate switch 31.
An oscillator, in the - 2a -~ ~ 127~
form of parallel connected resistor 15, ceramic filter 16 and inverter 17, is connected through buffer inverter 18 to the other input of NAND gate switch 31. . The N~ND gate 31 amplitude modulates the signal from inverter 18 with data from inverter 14. .~he output from~NAND gate 31 is buffered - by inverter 19 and. connected through filter section 40 to .
channel terminal 41. Filter section 40 comprises the series connection of resistor 42, ceramic filter 43 and resistor 44. Since the output ~rom switch 31 through inverter 19 is rich in the harmonics of the basic frequency supplied by oscillator 15-17, filter 40, whose ceramic fi-lter 43 is matched in frequency to ceramic filter 16, hard limits all harmonics to the envelope of the filter. Thus, the carrier frequency supplied to channel terminal 41 matches the fre-quency supplied by oscillator 15-17.
Channel terminal 41 is connected to a transmission channel to which similar modems are connected. The signal supplied to the transmission channel is received at a head end which converts the first carrier frequency to a second caerier frequency to which the receive side, receiver 20, is tuned.
Thus, the data received by the modem in the drawing is connected through a selective resonant network 50 comprising capacitor 51 connected on one side to channel terminal 41 and on its other side to the parallel network of capacitor 52 and inductor 53 the other side of which network is connected to ground. The junction of.capacitor 51 and the parallel network 52-53 is connected through capacitor 54 to pin 1, the input pin, of receiver 20. In receiver 20, the data signal is amplified and applied to a resonator connected across pins 8 and 9 and comprised of the parallel combination of capacitor 21 and inductor 22. Pins 2 and 3 1 ~L727~
are connected together throu~h bypass capacitor 38 and pins 3 and 4 are connected together through the parallel combina-tion of capacitor 23 and resistor 24. Thus, the carrier is switched or rectified for feedback to an automatic gain con-.. .. . . .: ..
trol network inherent in ci-rcuit 20. The time constant of -thé automatic gain control is determined by capacitor 23 and resistor 24. Receiver 20 demodulates the data received at pin l and supplies the demodulated signal at pin l~ where the demodulated signal is applied to zener diode 25 for TT~
compatible level shifting. Other elements of receiver 20 include a gain control resistor 26 connected between pins 7 and ll, bypass capacitor 27 connected between pin 2 and pin 15r bypass capacitors 28, 29, 55 and 56 connected respec-tively from pins l6, l5, 1~ and 13 to ground. Pins 14 and 13 are interconnected to the power supply through bleeder resistor 57 and pin 12 lS connected through zener diode 25 and resistor 58 to.ground. .~Fur.ther.more, gain control resis-tor 59 connects pin l0 to ground. Supply pin 3 is also tied directly to ground. Transistor 60 has its collector connected to pin 13 and to a positive input voltage supply, its base connected to pin 14 and its emitter supplies volt-age to pin 14 of transmitter l0 and switch/interface 30.
Transistor 60 converts the 12 volt supply to a 5 volt sup-ply. The demodulated output from receiver 20 is taken at .
the junction of zener diode 25 and resistor 58 and is connected to the first input of N~ND gate 32 of switch/interface 30. The second input of NAND gate 32 is.
taken from the output of N~ND gate 33 which ha.s a.first input tied to a positive source and a second inp~t connected through delay network 70 from the output of inverter 71 which has its input tied to the data input terminal ll through inverter 13. Delay network~comprises resistor 72
2 7 ~ 1 and resistor 73 series connected between the outp~L of inverter 71 and the second input of NAND gate 33.
Capacitors 74 and 75 are series connected across resistor 73 with the junction of these two capacitors connected to ground. Pin 14 of transmitter 10 is connecte~ to a positlve supply and also through capacitor 76 to ground from emitter 60. Delay network 70 receives the data applied to data input terminal 11 and delays this data by an amount depen-dent upon the delay which results from transmitting the data down the transmission channel, converting it to the second carrier frequency at the head end, and transmitting the data back along the transmission line to the modem shown in the Figure. This delayed data i5 then applied to the second input of N~ND gate 33 and consequently to the second input of N~ND gate 32 for blocking the received data sup~lied by receiver 20 t~o the first input of NAND gate 32. Thus, t~e modem will block data which it has transmitted along the .. . . . ...... . . .
transmission channel from its data output terminal 81 but will allow data from all other modems online to be presented to data output terminal 81.
- The output from ~ND gate 32 is buffered by N~ND
gate 34 before data from it is supplied to data ou~put ter-minal 81. Pin 14 of switch/interface network 30 is connected to the positive supply from emitter 60 and it is àlso connected to ground through bypass capacitor 35. Pin 7 of switch/interface 30 is connected to ground as is pin 7 of transmitter 10. The junction of resistor 12 and pin 5 of ~--transmitter 10 is connected to ground through the reverse junction of signal clipping diode 82.
Thus, a simple modem is provided which can be arranged in a very small package and comprises very few parts. The modem provides proper filtering to insure that it transrnits a frequency whlch7~11 be recognized by the head end and will recognize the proper frequency transmitted by the head end. The modem also blocks data from the data output terminal data which the modem has transmitted itself.
- In some instances such a function may not be desirable for reasons of an automatic loopback feature. Such a feature is obtained by connecting pin 12 of switch network 30 to ground potential. In the preferred embodiment ~he ceramic filters used are Murata SFE 10.7MS2-Z units providing for operation between a transmit frequency of 10.7MHz and receive frequen-cy of 53.1MHz.

. : . . , : , . ..

': -~.

. .

Claims

The embodiments of the invention in which an exclusive property or right is claimed are defined as follows:

1. A modem for transmitting and receiving digital informa-tion comprising data input terminal means for receiving digital data to be transmitted;
channel terminal means for supplying digital data to a transmission channel;
an oscillator providing an oscillator output signal;
switch means connected to said data input terminal means, said oscillator and said channel terminal means for modulating said oscillator output signal and for connecting said digital data to said channel terminal means;
data output terminal means for supplying received digital data; and, receiver means connected to said channel terminal means and to said data output terminal means for demodulating said received digital data and supplying said demodulated received digital data to said data output terminal means.

2. The modem of claim 1 wherein said oscillator comprises a ceramic filter.
3. The modem of claim 2 wherein said switch means has an output means connected to said channel terminal means, said output means comprising a ceramic filter tuned to substantially the same frequency as the ceramic filter of the oscillator.

4. The modem of claim 3 wherein said switch means further comprises blocking means connected to said data input terminal means and to said receiver means for blocking from said data output terminal means the received data which has been transmitted by said modem.

5. The modem of claim 4 wherein said receiver means comprises a filter tuned to the frequency of the received data.

6. The modem of claim 5 wherein said switch means com-prises a first NAND gate having a first input terminal connected to said oscillator a second input terminal connected to said data input terminal means and an output connected to said output means.

7. The modem of claim 6 wherein said data input terminal means comprises two series connected inverters connected from a data input terminal to said first input terminal of said first NAND gate and said output means of said switch means comprises a third inverter connected between said output of said first NAND
gate and said ceramic filter of said switch means.

8. The modem of claim 7 wherein said oscillator comprises a parallel combination of an inverter, said ceramic filter of said oscillator and a resistor connected to the second input of said first NAND gate through a further inverter.

9. The modem of claim 8 wherein said receiver comprises a demodulator having an input terminal connected to said filter of said receiver means, an output terminal connected to a first input terminal of a second NAND gate a second input terminal of which is connected to said blocking means, said second NAND gate having an output means connected to said data output terminal means.

10. The system of claim 9 wherein said blocking means comprises a delay network for delaying the application of data to said second NAND gate of said receiver means to match the delay of said transmission channel to block from said data output terminal means data which has been transmitted by said modem.

11. The modem of claim 10 wherein said blocking means further comprises an inverter having an input connected to an output of one of the inverters of said data input terminal means and having an output connected to an input of said delay network, said delay network having an output connected to an input of a third NAND gate an output of which is connected to said second input of said second NAND gate.

11. The modem of claim 1 wherein said switch means com-prises blocking means connected to said data input terminal means and to said receiver means for blocking from said data output terminal means received data which has been transmitted by said modem.

13. The system of claim 12 wherein said blocking means comprises a delay network for delaying the application of data to said receiver means to match the delay of said transmission channel to block from said data output terminal means data which has been transmitted by said modem.

14. The modem of claim 13 wherein said blocking means further comprises an inverter having an input connected to said data input terminal means and having an output connected to an input of said delay network, said delay network having an output connected to an input of a NAND gate an output of which is connected to said receiver means.

15. The modem of claim 14 wherein said receiver means comprises a NAND gate having a first input for receiving said received data, a second input connected to said output of said NAND gate of said blocking means, and an output means connected to said data output terminal means.

16. The modem of claim 15 wherein said switch means com-prises a NAND gate having a first input terminal connected to said oscillator, a second input terminal connected to said data input terminal means, and an output means connected to said channel terminal means.

17. The modem of claim 1 wherein said switch means com-prises a NAND gate having a first input terminal connected to said oscillator, a second input terminal connected to said data input terminal means, and an output means connected to said channel terminal means.

18. The modem of claim 17 wherein said data input terminal means comprises two series connected inverters connected from a data input terminal to said first input terminal of said NAND
gate and said output means of said NAND gate comprises inverter means connected between an output terminal of said NAND gate and said channel terminal means.

19. The modem of claim 18 wherein said oscillator comprises a parallel combination of an inverter, a ceramic filter and a resistor connected to the second input of said NAND gate through a further inverter.

20. The modem of claim 1 wherein said receiver means comprises a filter tuned to the frequency of the received data.

21. The modem of claim 20 wherein said receiver comprises a demodulator having an input terminal connected to said filter of said receiver means, an output terminal connected to a first input terminal of a NAND gate a second input terminal of which is connected to said switch means, said NAND gate having an output means connected to said data output terminal means.

22. A modem for transmitting and receiving digital informa-tion having only three active integrated circuits consisting of a transmitter having an oscillator connected thereto which is modulated by said digital information, a receiver having a demodulator therein for demodulating received digital data, and a switch/interface means connecting a data input terminal to said transmitter, said switch/interface means connecting said trans-mitter to a channel terminal for transmitting digital data over a transmission medium, and means connecting said channel terminal to said receiver for demodulating said received digital data, said switch/interface means connecting said receiver to a data output terminal.

23. The modem of claim 22 wherein said transmitter is an inverter array and said switch/interface is a NAND gate circuit arrangement.

24. The modem of claim 23 wherein said inverter array is a 74LS04 hex inverter, said NAND circuit arrangement is a 74LS00 quad NAND gate, and said receiver is a TDA440 AM receiver.
CA000352494A 1979-07-02 1980-05-22 Data transceiving modem Expired CA1172701A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5387279A 1979-07-02 1979-07-02
US053,872 1979-07-02

Publications (1)

Publication Number Publication Date
CA1172701A true CA1172701A (en) 1984-08-14

Family

ID=21987119

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000352494A Expired CA1172701A (en) 1979-07-02 1980-05-22 Data transceiving modem

Country Status (1)

Country Link
CA (1) CA1172701A (en)

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