CA1159171A - High resolution video display system - Google Patents
High resolution video display systemInfo
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- CA1159171A CA1159171A CA000378860A CA378860A CA1159171A CA 1159171 A CA1159171 A CA 1159171A CA 000378860 A CA000378860 A CA 000378860A CA 378860 A CA378860 A CA 378860A CA 1159171 A CA1159171 A CA 1159171A
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Abstract
Abstract of the Disclosure A video display system is disclosed. Video signals are converted from analog to digital format.
Portions of the signal are selected for display and transmitted to the display elements. A high speed quality display is obtained by utilizing transmission circuits which can operate in real time at a rate suf-ficiently high to keep up with the incoming video signal.
This permits the system to utilize more video information than it has previously been possible to use. An addi-tional feature of the invention is the ability to simu-late a travelling sign display by causing a message to appear to move across the scoreboard.
Portions of the signal are selected for display and transmitted to the display elements. A high speed quality display is obtained by utilizing transmission circuits which can operate in real time at a rate suf-ficiently high to keep up with the incoming video signal.
This permits the system to utilize more video information than it has previously been possible to use. An addi-tional feature of the invention is the ability to simu-late a travelling sign display by causing a message to appear to move across the scoreboard.
Description
~ 15~3i71 Background of the Invention .his invention relates to the field of large video display systems of the type suitable for use in stadia. Such displays are usually formed by a large matrix of variable intensity display devices as, for example, incandescent light bulbs, fluorescent light sources, light-emitting diode sources, and the like. The display devices are driven by an electronic displa~7 system, usually computer controlled. The display system receives a video input such as the line feed from a network broad-cast, a video tape recording, or a signal from a live action camera. The display system digitizes the video input, producing data corresponding to the intensity level of each picture element which forms a line in a conventional television raster. The number of nicture elements or sampling points and the number of lines oE the raster which are digitiæed and subsequently used by the display system are limited by the capacity of the system to handle the incoming video data in real time.
Because the video data rates are so high it has not heretofore been possible to utilize all of the variable video information for disPlaying images on the scoreboard portion of the display system. Instead, large portions of the video information are simply discarded and, as a result, the display image was of rather low, although ~., ~ 15~i71 acceptable, resolution. For example, in some systems anproximately 75~,!, oE the available video data was dis-carded b~ the display system. That is, these systems utilized every other line of video data in one field.
As is well known in the television industry, a complete frame of video information includes two fields which are interlaced to form the comnlete frame.
In such prior systems, even with the reduced quantity of data,it was still necessary to provide a means for storin~ the selected data from each frame for a time sufficient to permit its transmission to the dis-play device. In early systems, the digitized data for a frame was stored in a computer memory and subsequently transferred from the memory to the display devices.
Typically, such systems em~loyed minicomputers of the type manufactured by ~igital Equipment Corporation, rlaynard, Massachusetts, such as PDP 8 and 11. Although such com-puters are relatively powerful devices, their data trans-fer rates are too low to transmit as much digitized video information, on a real-time basis, as is required for high resolution video displays. As a result, the com~uter represents a limiting element in the system with respect to the rate at which digitized data can be transferred to the display elements.
~ l~gl~31 One way of increasing the clata handling capacity of such systems is to substitute a high speed random access memory, often referred to as a full frame buffer for the com-puter storage~ This results in a speed increase which permits improved contrast, e.g., increased number of inten sity levels and better resolution, e.g., more video data utilized. In such systems, the computer retains control of the system but is removed from the data path to the display board.
This latter approach wherein a buffer is utilized produces an acceptable display image but is still not total-ly satisfactory from the standpoint of being able to use sufficient video information to provide high resolution and high quality video displays.
It is desirable to provide a display system which is capable of utilizing substantial portions of the available video data for each frame. In order to do so, it is necessary that the system be able to digitize and transmit the digitized video information to the display board on essentially a real time basis. By real time basis it is meant that the need for a full frame buffer memory or a full frame computer storage element is eliminated and the digit-ized data is -ransmitted directly to the display board after appropriate selection of the portions thereof to be displayed.
It is accordingly an object of an aspect of the present invention to provide a high resolution video display system which can recei~e video data, digitize it into the intensity level information, and transmit the digitized information to a display board on a real time basis.
It is an object of an aspect of the present invention to provide a system of the type mentioned in the preceding paragraph which does not require a full frame buffer memory interposed in the data path.
An object of an aspect of the present invention is the provision of a novel circuit, referred to herein as a rotator, which car cause a message to appear to travel across the video display in a manner which does not require the control computer to perform the data manipulation involved therewith.
An aspect of the invention is as follows:
A high resolution system for dis~laying video images on a plurality of variable intensity display devices in real time, said images representing selected portions of video frames received from a video source in raster (TV) format, said system comprising:
(a) a video converter receiving the raster lines of video information corresponding to each frame, said converter including quantizing means for generating digital data representative of the relative intensity of said video information at selected points on selected raster lines of said frames and means for selectin~ which lines and the number of said points per line for which digital data is generated, said digital data being generated at a first rate, sufficient to keep up with the rate at which the video information is received;
(b) transmitter means receiving said digital data at said first rate for transmitting it to said display devices in a modified raster line format without frame storage, said transmltter means including means for S dividing each line of digital data into at least two segments and means for transmitting in parallel the data for each of said segments to said display devices, whereby the line at a time raster format of the video information is retained but the effective rate of transmission of data to the display devices corresponding to each segment is reduced to a second rate approximately equal to said first rate divided by the number of said segments, the reduced data rate permitting display of an increased number of data points per raster line and/or the use of more raster lines from the video source;
(c) interface means for selectively connecting said converter to said transmitter means;
(d) means for controlling the operation of said interface means thereby directing the transfer of data betwween said converter and transmitter means.
Other objects and advantage of the invention will become apparent from the remaining portions of the specification.
-4a-l15~17~
Prior Art Statement Applicants state that the following patents represent the closest prior art of which ~hey are aware:
U.S. Patent Nos. 4,009,335; 3,941,926; 3,961,365; and 4,148,073. These patents disclose video display systems of the present type in which, however, video data is digitized and a complete frame is stored in either a computer memory or a full frame buffer memory. The data is then taken from the memory and transferred to the display board for illuminating the displav devices.
-4b-1 1~9 ~7 1 In the first mentioned patent, a four shades of gray device is clisclosed in which data is transmitted from the computer to the display board during a time window between processing cycles. In the second mentioned patent, a device capable of displaying eight or sixteen shades of gray is disclosed which also employs a computer memory although there is a suggestion of employing a random access memory to store a frame of digitized data. In the third mentioned patent, a color display system is disclosed similar to the second men-tioned patent which, however, employs parallel data handling systems to generate information for differently colored display devices which are clustered to generate a color display. In the last mentioned patent, a dis-play system is disclosed in which a full frame buffer is utilized to increase the speed of the display system.
The computer acts as a control device but is not directly in the data path. That patent also discloses techniques for creating an electronic enlargement by increasing the sampling rate of the incoming video information for a selected portion of the video picture.
Brief Description of the Drawings Figure 1 is a block diagram of the control logic, its relationship to the computer and display board logic according to the invention.
Figure 2 is a timing diagram useful i~ explaining the operation of the V/D interface.
Figure 3 illustrates the matrix board addressing scheme according to the invention.
Figure 4 is a block diagram of the transmitter according to the invention.
Figure 5 is a diagram of the display buffer image mat.
Figure 6 is a diagram useful in explaining opera-tion of the rotator circuit.
Figures 7a to 7c constitute a schematic diagram of the rotator circuit according to the invention.
Figure 8 is a timing diagram useful in under-standing the rotator circuit according to the invention.
1 ~$9171 THEORY OF OPERATION
The dis~lay system according to the present invention is made up of three major elements. The first consists of the com~uters, terminals, and video hardware.
The second includes the control logic which is required to interface the first element to the third. This equipment is mounted in the control room comPuter racks and junction boxes. The third element of the system is the video matrix display board.
THE COMPUTER CONTROL SYSTEM
The heart of the computer control system is a Digital Equipment Corporation PDP 11/04 mini-computer with 28k words of memory. For its mass memory storage medium there are two disk drives, 100 each with a capacity of 5.2 million bytes. These drives use a removable disk pack for easy loading and program expansion.
The operator interfaces with the computer through a display terminal. Using the keyboard and touch panel of the terminal the operator controls the flow of data.
The video system does not interfere directly with the computers. It interfaces with a video ~converter 110 which, in turn, interfaces with the computer. The video system is essentially a video input selector and signal conditioner. It provides the source video that may be displayed on the matrix display board.
~ ~5917~
CONTROL LO(7IC
The control logic provides the interfacing hardware necessary to allow the elements of the comRuter control system to generate displays on the video matrix board. In a simplified form it operates as follows:
In response to an operator's request, the computer co~mands the logic to perform an operation.
There are three basic types of operations:
1. Display a video image directly on the matrix board.
Because the video data rates are so high it has not heretofore been possible to utilize all of the variable video information for disPlaying images on the scoreboard portion of the display system. Instead, large portions of the video information are simply discarded and, as a result, the display image was of rather low, although ~., ~ 15~i71 acceptable, resolution. For example, in some systems anproximately 75~,!, oE the available video data was dis-carded b~ the display system. That is, these systems utilized every other line of video data in one field.
As is well known in the television industry, a complete frame of video information includes two fields which are interlaced to form the comnlete frame.
In such prior systems, even with the reduced quantity of data,it was still necessary to provide a means for storin~ the selected data from each frame for a time sufficient to permit its transmission to the dis-play device. In early systems, the digitized data for a frame was stored in a computer memory and subsequently transferred from the memory to the display devices.
Typically, such systems em~loyed minicomputers of the type manufactured by ~igital Equipment Corporation, rlaynard, Massachusetts, such as PDP 8 and 11. Although such com-puters are relatively powerful devices, their data trans-fer rates are too low to transmit as much digitized video information, on a real-time basis, as is required for high resolution video displays. As a result, the com~uter represents a limiting element in the system with respect to the rate at which digitized data can be transferred to the display elements.
~ l~gl~31 One way of increasing the clata handling capacity of such systems is to substitute a high speed random access memory, often referred to as a full frame buffer for the com-puter storage~ This results in a speed increase which permits improved contrast, e.g., increased number of inten sity levels and better resolution, e.g., more video data utilized. In such systems, the computer retains control of the system but is removed from the data path to the display board.
This latter approach wherein a buffer is utilized produces an acceptable display image but is still not total-ly satisfactory from the standpoint of being able to use sufficient video information to provide high resolution and high quality video displays.
It is desirable to provide a display system which is capable of utilizing substantial portions of the available video data for each frame. In order to do so, it is necessary that the system be able to digitize and transmit the digitized video information to the display board on essentially a real time basis. By real time basis it is meant that the need for a full frame buffer memory or a full frame computer storage element is eliminated and the digit-ized data is -ransmitted directly to the display board after appropriate selection of the portions thereof to be displayed.
It is accordingly an object of an aspect of the present invention to provide a high resolution video display system which can recei~e video data, digitize it into the intensity level information, and transmit the digitized information to a display board on a real time basis.
It is an object of an aspect of the present invention to provide a system of the type mentioned in the preceding paragraph which does not require a full frame buffer memory interposed in the data path.
An object of an aspect of the present invention is the provision of a novel circuit, referred to herein as a rotator, which car cause a message to appear to travel across the video display in a manner which does not require the control computer to perform the data manipulation involved therewith.
An aspect of the invention is as follows:
A high resolution system for dis~laying video images on a plurality of variable intensity display devices in real time, said images representing selected portions of video frames received from a video source in raster (TV) format, said system comprising:
(a) a video converter receiving the raster lines of video information corresponding to each frame, said converter including quantizing means for generating digital data representative of the relative intensity of said video information at selected points on selected raster lines of said frames and means for selectin~ which lines and the number of said points per line for which digital data is generated, said digital data being generated at a first rate, sufficient to keep up with the rate at which the video information is received;
(b) transmitter means receiving said digital data at said first rate for transmitting it to said display devices in a modified raster line format without frame storage, said transmltter means including means for S dividing each line of digital data into at least two segments and means for transmitting in parallel the data for each of said segments to said display devices, whereby the line at a time raster format of the video information is retained but the effective rate of transmission of data to the display devices corresponding to each segment is reduced to a second rate approximately equal to said first rate divided by the number of said segments, the reduced data rate permitting display of an increased number of data points per raster line and/or the use of more raster lines from the video source;
(c) interface means for selectively connecting said converter to said transmitter means;
(d) means for controlling the operation of said interface means thereby directing the transfer of data betwween said converter and transmitter means.
Other objects and advantage of the invention will become apparent from the remaining portions of the specification.
-4a-l15~17~
Prior Art Statement Applicants state that the following patents represent the closest prior art of which ~hey are aware:
U.S. Patent Nos. 4,009,335; 3,941,926; 3,961,365; and 4,148,073. These patents disclose video display systems of the present type in which, however, video data is digitized and a complete frame is stored in either a computer memory or a full frame buffer memory. The data is then taken from the memory and transferred to the display board for illuminating the displav devices.
-4b-1 1~9 ~7 1 In the first mentioned patent, a four shades of gray device is clisclosed in which data is transmitted from the computer to the display board during a time window between processing cycles. In the second mentioned patent, a device capable of displaying eight or sixteen shades of gray is disclosed which also employs a computer memory although there is a suggestion of employing a random access memory to store a frame of digitized data. In the third mentioned patent, a color display system is disclosed similar to the second men-tioned patent which, however, employs parallel data handling systems to generate information for differently colored display devices which are clustered to generate a color display. In the last mentioned patent, a dis-play system is disclosed in which a full frame buffer is utilized to increase the speed of the display system.
The computer acts as a control device but is not directly in the data path. That patent also discloses techniques for creating an electronic enlargement by increasing the sampling rate of the incoming video information for a selected portion of the video picture.
Brief Description of the Drawings Figure 1 is a block diagram of the control logic, its relationship to the computer and display board logic according to the invention.
Figure 2 is a timing diagram useful i~ explaining the operation of the V/D interface.
Figure 3 illustrates the matrix board addressing scheme according to the invention.
Figure 4 is a block diagram of the transmitter according to the invention.
Figure 5 is a diagram of the display buffer image mat.
Figure 6 is a diagram useful in explaining opera-tion of the rotator circuit.
Figures 7a to 7c constitute a schematic diagram of the rotator circuit according to the invention.
Figure 8 is a timing diagram useful in under-standing the rotator circuit according to the invention.
1 ~$9171 THEORY OF OPERATION
The dis~lay system according to the present invention is made up of three major elements. The first consists of the com~uters, terminals, and video hardware.
The second includes the control logic which is required to interface the first element to the third. This equipment is mounted in the control room comPuter racks and junction boxes. The third element of the system is the video matrix display board.
THE COMPUTER CONTROL SYSTEM
The heart of the computer control system is a Digital Equipment Corporation PDP 11/04 mini-computer with 28k words of memory. For its mass memory storage medium there are two disk drives, 100 each with a capacity of 5.2 million bytes. These drives use a removable disk pack for easy loading and program expansion.
The operator interfaces with the computer through a display terminal. Using the keyboard and touch panel of the terminal the operator controls the flow of data.
The video system does not interfere directly with the computers. It interfaces with a video ~converter 110 which, in turn, interfaces with the computer. The video system is essentially a video input selector and signal conditioner. It provides the source video that may be displayed on the matrix display board.
~ ~5917~
CONTROL LO(7IC
The control logic provides the interfacing hardware necessary to allow the elements of the comRuter control system to generate displays on the video matrix board. In a simplified form it operates as follows:
In response to an operator's request, the computer co~mands the logic to perform an operation.
There are three basic types of operations:
1. Display a video image directly on the matrix board.
2. Store a video image in disk memory.
3. Display a stored disk image on the matrix board.
The control logic decodes the command and, if possible, executes it. After execution, the logic informs the control system that it is done.
The control logic communicates with the computer via a DEC DRll-B interface module 112 contalned within the computer chassis.
COMPUTER INTERFACE
The computer interface 114 (Figure 1) is primarily used to transfer blocks of data between the computer memory and a full frame display buffer 116.
These blocks of data move in either direction at 1 159~7 1 approximately 1.2 usec per 16 bit word. Data coming from the com~uter is sent on the DRll-B's outPut bus (OB). Data going to the computer is sent on the input bus (IB). The OB and IB are also used to send command and status information between the computer and other devices making up the control logic system 106. It transmits other signals as well, in particular, the tunction (FNCT) signals, which are used to determine which device connected to the bus is to be selected.
Figure 3 is a table of functions and commands recognized by the control logic. For convenience all of the signals between the DRll-B and the control logic are referred to as control bus signals.
DISPLAY BUFFER
The display buffer 116 is essentially a random access memory (RAM). Its organization is 64 x 40~6;
however, it is constructable in lK increments. The display buffer is a memory that may hold an image which can be displayed on the matrix board. It may also hold an image which can be transferred to the computer memory.
In operation, the display buffer may be written to, or read from, by either the computer interface 114 or the V/D interface 118. A detailed description follows.
1 15~ :i 7 1 MESSA~,E ROTATOR
The message rotator 120 allows a message to travel from right to left across the matrix board. It does this without requiring the computer to read, shift, and write the entire frame, an operation which takes a great deal of com~uter time and yields rather slow travel rates. Details of this circuit are described in connection with Figures 5-7.
VtD INTERFACE
The V/D (video/display) interface 118 is used to transfer display data between the video converter 110, display buffer 116, and the video transmitter 122. It is the primary display control device and data router.
In addition, it controls a preview/display monitor 124 which allows an operator to preview material prior to displaying it on the matrix display board.
VIDEO CONVERTER
The video converter 110 is made up of three basic units: the quantizer 126, the video controller 128, the video control panel 130. The video converter transfers digitized video images to the V/D interface 118.
~ 159:~71 ~ he video ~uantizer 126 board performs the following functions:
1. Receives the video source signal.
2. Strips and regenerates sync signals from the video source signal.
3. Divides a video line into a series of sampling points.
The control logic decodes the command and, if possible, executes it. After execution, the logic informs the control system that it is done.
The control logic communicates with the computer via a DEC DRll-B interface module 112 contalned within the computer chassis.
COMPUTER INTERFACE
The computer interface 114 (Figure 1) is primarily used to transfer blocks of data between the computer memory and a full frame display buffer 116.
These blocks of data move in either direction at 1 159~7 1 approximately 1.2 usec per 16 bit word. Data coming from the com~uter is sent on the DRll-B's outPut bus (OB). Data going to the computer is sent on the input bus (IB). The OB and IB are also used to send command and status information between the computer and other devices making up the control logic system 106. It transmits other signals as well, in particular, the tunction (FNCT) signals, which are used to determine which device connected to the bus is to be selected.
Figure 3 is a table of functions and commands recognized by the control logic. For convenience all of the signals between the DRll-B and the control logic are referred to as control bus signals.
DISPLAY BUFFER
The display buffer 116 is essentially a random access memory (RAM). Its organization is 64 x 40~6;
however, it is constructable in lK increments. The display buffer is a memory that may hold an image which can be displayed on the matrix board. It may also hold an image which can be transferred to the computer memory.
In operation, the display buffer may be written to, or read from, by either the computer interface 114 or the V/D interface 118. A detailed description follows.
1 15~ :i 7 1 MESSA~,E ROTATOR
The message rotator 120 allows a message to travel from right to left across the matrix board. It does this without requiring the computer to read, shift, and write the entire frame, an operation which takes a great deal of com~uter time and yields rather slow travel rates. Details of this circuit are described in connection with Figures 5-7.
VtD INTERFACE
The V/D (video/display) interface 118 is used to transfer display data between the video converter 110, display buffer 116, and the video transmitter 122. It is the primary display control device and data router.
In addition, it controls a preview/display monitor 124 which allows an operator to preview material prior to displaying it on the matrix display board.
VIDEO CONVERTER
The video converter 110 is made up of three basic units: the quantizer 126, the video controller 128, the video control panel 130. The video converter transfers digitized video images to the V/D interface 118.
~ 159:~71 ~ he video ~uantizer 126 board performs the following functions:
1. Receives the video source signal.
2. Strips and regenerates sync signals from the video source signal.
3. Divides a video line into a series of sampling points.
4. Converts (quantizes) the analog video into a 4 bit digital value representative of one of 16 possible intensity levels for a variable intensity display device such as an incandes-cent light bulb.
The video controller 128 selects the Parameters for operation of the quantizer. lhe video controller con-tains an Intel 8085 microprocessor ~P). It monitors the video operator inputs, which include:
1. Joystick positi~n control for selecting desired portions of the video plcture to be displayed.
2. Image size selection controls.
3. Run/stop controls.
In additionJ it receives commands from the computer via the control bus and V/D interface.
1 1~917 1 The video control panel 130 is mounted in the operator's console~ It allows the video operator to select various display options which include: image size, image position, automatic gain, and automatic set-up (AGC and ASU).
TI~NSMITTER l22 The transmitter receives data from the V/D
interface 118, formats it and inserts the necessary addresses, then transmits the image to the video matrix board 132. The formating involves dividing each line of data into a left and right half, thereby reducing the data rate by half. An address header must be placed at the beginning of each line of data so that the matrix display logic at the board will know where to place each line it receives. The transmitter must also maintain a steady stream of lamp brightness data. The lamp bright-ness information, called ~ pulses, is generated by the generator 134 as determined by the four bit word from the quantizer 126. The ~ pulses are nultiplexed by the transmitter and continuously transmitted to both the left and right halves of the matrix board 13~. The details of this circuit are described in connection with Figures 1-4.
1 15g~7~
~ GEIIERATOR
The ~ génerator is used to generate three bursts of 15 pulses. Each burst is locked to one of the three power line phases: A, B, or C. Each pulse within a burst defines one of 15 lamp brightness intensity levels (the 16th level being the off condition). Adjustments on the ~ generator allow it to be set-up to render the desired brightness levels.
2~ATRIX DISPLAY BOAP~D 132 The matrix display is preferably made up of 40 watt incandescent lamps, arranged in a matrix M
lamps high by N lamps wide. The face of the display is formed by stacking modules of lamps, each module contain-ing a quantity of lamp trays. To the electronics involved in controlling the lamps, the precise number, placement, or size of the modules is unimportant. The electronics sees only an arrangement of lamp trays form-ing an electrical matrix of a predetermined size (21 x N).
Each lamp tray contains 24 lamps and is con-trolled by one triac control board card. Thirty triac cards are driven by one driver board. Two driver boards can be controlled by one controller board. The driver and controller board are connected to the high speed control cables via one I/O board. All of the above i 15~7~
(except the lamp tray) is contained within a control cabinet located at the board.
Each control cabinet has the capacity to drive 1,440 lamps. For reasons of packaging expedience, each cabinet can drive these lamps arranged only in an area 24 lamps wide by 60 lam~s high.
Each control cabinet is fed 3-phase power from a power distribution cabinet. The power feed is connected to a load center mounted on the side of each control cabinet. ~ithin each load center is a quantity of 20 amp circuit breakers, which provide power to the entire cabinet.
In reading the following detailed description of the transmitter it is important to remember:
All images displayed on the matrix board come either from the video converter or the display buffer, or both in combination. There is no direct path from the computer system to the transmitter.
The video converter generates images in a line-at-a-time process, scanning from top to bottom, left to right. This serial image construction will be called a "video format". The timing and number of sig-nals needed to control the image may change but this basic line-at-a-time, frame-by-frame process will always be the same.
The V/D interface under computer command routes the images.
The transmitter receives and sends the matrix images in a vi.deo format style. Except for minor buffer delays, tlle transmitter transmits to the video matrix display board in real time. Thus, one line received equals one line transmitted.
The matrix display board is divided into a left and right half. The display board control cabinets on the left side are daisy-chained to the left set of high speed cables; similarly, the right control cabinets are connected to the right set of high speed cables.
TRANSMITTER
The transmitter receives the output of the V/D
interface and ~ (phase) generator, formats and splits it into a left and right half, and then transmits the pixel address and lamp brightness information to the display board at a 3~z ner pixel rate.
The transmitter operates as both a master and slave device. It masters the AS~C (address sync), WCLK
(write clock), and ~M (multiplexed ~ pulses). These out-puts are generated as soon as power is applied. When pixel data is not being transmitted, the transmitter is in the idle state. The idle state maintains a steady 1 15~7 ~
flow of lamn brightness data, ~ pulses, in the form of ~1, to the display logic. The ~ nulses are derived fron the ~ ~en, to be described.
In the slave node the transmitter res~onds to the output of the V/D interface. When the V/D inter-face has an image to output to the display board, its output circuits generate the necessary timing and data in a video format. The transmitter responds by collect-ing the data and transmitting it to the matrix board.
When the transmitter begins to transmit pixel (or lamp data, LD) information it leaves the idle state and enters the transmit state. The operation of the transmitter can be best understood from a study of the pur~ose of its output signals.
TRANSMITTER OUTPUT
The output of the transmitter is arranged in essentially a video format. Thus it sends data in a horizontal line-at-a-time fashion. In this specifica-tion the terms "line" and "row" will be used inter-changeably. Line will most often be used to refer to the transmission of data. Row will usually be used when we are speaking of "rows of lamps". Three addi-tional terms, Lev, Mem and Line, will also be used in the description. These make up the three parts of the address which precedes each line of transmission.
Due to design limitations the output of data from the transmitter is set at 3~æ per pixel. The data received from the V/D interface may arrive at either 6.14Ml~z in tl~e x2 mode, or 4.09MIIz in the x1.3 mode.
The data arriving in the x2 mode has a line-to-line period of 63.5 usec. Since the transmitter's output operating at 3~z would take more than ~8 usec to pro-cess this line of data, it becomes necessary to divide each line into two halves. Thus the transmitter will have two independent sets of output signals, one to drive the left side of the matrix and one to drive the right.
Each output signal set will contain seven signal types. They are:
ASYNC - address sync; a 333ns Pulse which indicates that the next 12 LD3 data bits are to be inter-preted as an address.
WCLK - write clock; a 3MHz clock which occurs in bursts between ASY~C's. In the idle state 12 WCLK's make up a burst. In the transmit state the left output circuits generate a burst of 120 WCLK's while the right's burst contains 96 WCLK's. The front edge of each WCLK
pulseisused to sample the contents of the four LD signals, and the ~M line. WCLK bursts always occur in multiples of 12.
1 159~71 LD0 through LD3 - Lam~ data; contains the four bits of pixel data during the transmission of each line of data. LD3 will contain the line address which begins each line o~ transmission. In the idle state all the LD lines will contain zeros.
~ M - multiplexed ~ pulses; contains the six pulses obtained from the ~ gen, as well as the locally generated era (erase) signal, tine multiplexed under the last seven WCLK's of each multiple of 12 WCLI~'s.
ASYNC indicates the beginning of a 1~ WCLK cycle, but during a transmission, a local divide-by-12 will recycle the ~M data. Thus ~M data is continuously outputted, both during the idle and transmit states.
The top of timing diagram, Figure 2, shows the relationship between the ASYNC, WCKL, LD and ~M signals during both the idle and transmit states. The numbers written into each group of 12 WCLK's indicate the COL's of lamps within which the data belongs. Recall that the term COL refers to a positional address across each line of transmission. Its address is inferred by the matri~ board logic by simply dividing a line of WCLK's by 12 and incrementing a counter. Each display board control cabinet will be coded to look for its particular COL. The transmission shown in Figure 17 contains COL's 1 through 9 which would correspond to 108 lamps, which 1 15~73 would mean a transmission to the left side o.f the matrix board. A COL designation of zero indicates a ~eriod of 12 I~CLK's during which time an address is transmitted on the LD3 line. Notice the zero occurs after each ASYNC pulse.
To convert Figure 2 into a transmission to the right side of the matrix you would sim~ly delete COL's 8 and 9 and return to the idle state immediately following COL number 7.
Before sending a line of data to the matrix we must precede it with an address that will identify to the three levels of control cabinets where it belongs.
Figure 3 shows the matrix board as it appears in terms of transmitter addresses. The three comPOnent parts that make up the address are called:
LEV - level; indicating a level of cabinets numbered from one starting at the top of the matrix.
Each LEV can drive, for example, 60 rows of lamps.
MEM - memory; each LEV contains 3 MEM's numbered from the top as Ml, M2 and M3. Each MF.M may drive, for exam~le, 20 rows of lamps.
LINE - line; each MEM contains 20 lines or rows of lamps numbered 0-19. To identify which row the trans-mission belongs to, 5 bits of the address word are iden-tified with the LINE value.
The address is made uP of 12 bits of data, and organized in the following format.
All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0 spare LEV MEM LINE
0 0000 00 0000~
through through through This address word, combined with the COL, can locate every pixel on each half of the matrix board.
From Figure 3 it will be clear to those skilled in the art the purpose of the addressing method and its ability to address unique groups of twelve pixel rows on both the left and right side of the matrix.
TRANSMITTER OPERATION
As stated earlier, the transmitter will receive one line of data from the V/D interface and, because of data rate limitations, divide it into two lines of output data called "left" and "right". In front of both the left and right transmission halves the transmitter will insert an address. Since each line of 1ata has a unique address, the address stuck onto the left and right half of each line transmitted will be the same.
1 15gl73 The data received from the V/D interface is at either 6.14 M~lz or at 4.09 ~lz. When it departs the transmitter it is going at 3.0MHz. To accomplish this data rate reduction, FIFO (first in, first out) shift registers are used. One is needed for each of the left and right outputs. In the transmitter's block diagram, Figure 4, they can be seen identified as the left and right buffers.
This lays the groundwork necessary to under-stand the input and output flow of data through the transmitter. Using the block diagram of Figure 4 it is possible to trace the flow of data coming from the V/D
interface and departing the tranmitter's output. The conditions at the input will be those for a x2 image.
The SF~I (start frame) pulse arrives at the beginning of a frame and initializes the transmitter.
Via the address control logic 520 SFRM will set the LEV
portion of the address counter 522 to 0001. The three LSB's of LEV will go up to the select inputs of the level starting address multiplexer 524. The data inputs to the level starting address multi~lexer are the jumpered MEM
and LINE star~ing values for each level. Selecting the LEV OOll input will place the starting address needed for the first line of transmission into the address counter. SF~M goes to the MR (master reset) of the right and left buffers, setting them empty.
1 1~9171 The transmitter next receives the SLIN (start line) pulse from the V/D interface. SLIN goes to the input control logic 526 and sets the input shift regis-ter 528 to the parallel load mode. SLIN causes ACLK
(address clock) to be generated in the address control logic. The back edge of ACLK will cause the contents of the address counter 522 to paral.lel load into the input register 528. The back edge of ACLK will also cause the address counter to increnent, setting up the next line address to be transmitted. ACLK will also clear the parallel mode from the input shift register and allow the input control logic 526 to set the shift register to the shift right mode.
The transmitter is now ready to receive the VD0-VD3 data from the V/D interface. VTCLK (video-transmit clock) will accompany the data and make it possible for the transmitter to shift the data into the input shift register 528. The first twelve VTCLK's will shift twelve pixels of data into the register while simultaneously shifting the previously loaded address from the address counter 522 into both the left and right buffers 530 and 532.
As soon as the twelfth VTCLK has been counted by the input control logic it will no longer allow the VTCLK's to shift into both buffers; it will now direct the data to only the left buffer 530.
1 ~Sg~71 The next twelve VTCLK's will shift twelve more pixels of data into the inPUt register. As the new data comes in, the previous data flows out into the left buffer. As should be apparent, the left buffer is collecting the data which forms the first line of a transmission. It collected the address and then the lamp data.
The process continues until the left buffer is filled with twelve address bits andJ for example, 108 pixels. The inPut control logic has been faithfully counting the loading of the left buffer. When the 108th pixel is loaded, by the 120th VTCLK, the in~ut control logic will allow no more data into the left buffer. It will now route the VTCLK's to the right buffer. The right buffer will take the next, for example, 72 VTCLK's and load 72 additional pixels. After the 192nd VTCLK the input register will have the last twelve pixels of data still residing in it. Remember, the first twelve VTCLK's were used to load the address, so the buffer is always lagging the data by twelve VTCLK's. The input control logic will take the output of a 6 MHz xtal oscillator 53~ and use it to transfer the final twelve pixels into the right buffer.
This completes the input transfer of one line of data from the V/D interface. Within a few short 1 7 ~
microseconds the V/D interface will be sending the transmitter the second line of data. The next line will again be preceded by the SLI~I pulse. As before, the input register 528 will be loaded with the contents of the address counter 522, now holding the address of the second line. The next ACLK will again increment the address counter, this time to the address of the third line.
The VTCLK's and LD for the second line will pour in and again the left and right buffers will become the depository of the address and data for the second line: And so on until 144 lines of data have been received, addressed and shifted into the left and right buffers.
To keep track of the levels of Figure 3 the address counter is equipped with a detector circuit which identifies the end or last line of each level. At that time the LEV bits to the level starting address multi-plexer will address the next LEV and cause the subsequent ACLK to load the address counter with its output.
The left and right buffers, in most applications, are not of sufficient length to receive an entire line.
This means that the image received from the V/D interface cannot be entirely contained by the transmitter and, l 15917 1 therefore, the outputting of data from the transmitter ~ust begin as soon as possible to ~revent the buffers from overflowing. Since the control of data from the left and right buffers is virtually identical, the explanation will follow just the left buf,er.
Data shifted into the left buffer 530 will quickly bubble through to its output. It will remain there until a shift out pulse is received to remove it.
Each shift out will extract one pixel of data just as one shift in loaded one pixel.
When the data loaded into the buffer ap~ears at the output the LOR (left outnut ready) signal there-from will indicate to the left output control logic 536 that a transmission can begin. Prior to receiving LOR
the output control logic was in the idle state, sending out ASYNC, WCLK and ~M data through the left data selector 538 to the left side of the matrix board.
When LOR arrives the idle state will terminate with the next ASYNC pulse and the transmit state will begin. The output control logic 536 will begin to empty the buffer with each WCLK. One hundred twenty WCLK's will send the first line of pixels to the display logic on the left side of the matrix.
The output control logic will send exactly 120 WCLK's after which it will generate the next ASY~C
1 159 i7 l pulse. If the buffer is e~pty the ASYNC will cause the idle state to resume. Jf the next line of data is in the buffer, then the ASYNC will see the LOR set high once again. This will cause the begim~ing of the next trans-mit state to follow immediately after the previous one.
In this way the output control logic will process each line of data to the matrix board. Notice that it does not care about addresses. It ~just passes the data along exactly as it was received.
The left and right ~ pulse multiplexer 538 are identical. They each receive the six lines of ~
pulse data produced by the ~ gen. A board erase circuit 540 feeds the seventh piece of data to the multiplexer.
The output control logic generates the timing pulses necessary to drive their respective multiplexers. For every twelve WCLK's produced by the output control logic, one multiplexing cycle cf the seven data inputs will occur.
Summaring the description of the transmitter it will be appreciated that:
The transmitter always transmits com~lete lines of data. If for some reason the V/D interface sends a short line, the transmitter circuits will detect the condition and fill in the remainder of the line with off lamp data. The VTCLK signal initiates the transmission.
1 ~S9171 SFRM and SLIN alone will cause no output fron the trans-mitter. Transmission may end after any line has been received. The transmitter will not fill in the balance of a short frame as it does for a short line. When an image to be transnitted is derived from the V/D inter-face in the x1.3 resolution, it will be coming as two frames of interlaced data. This requires the address control logic to modify the way it increments the address counter. The FLDl (field one) and RESl. 3 (resolution x1.3) signals from the video converter will inform the address control logic that a x1.3 image is coming. In response the address control logic will start on either the first or second line of the display and increment by twos as each SLIN is received.
DIS~LAY BUFFER
The display buffer 116 is a R~I memory con-figured 64 x 2048. The display buffer includes the rotator circuits. The rotator is used to move messages across the video matrix board.
The display buffer is used as a temporary place to store an image. It is important to understand how the board image is mapped into the display buffer memory to perceive the operation of the rotator circuits.
'~ 1S9~71 The display buffer is used to contain pictorial images in a digital form. The organization of the image is arranged in such a way as to allow efficient design of the addressing circuits which must interface with it.
Since video data i5 received at high speeds, the most efficient interface techniques would favor an addressing scheme organized around data in a video format. This yields the arrangement shown in Figure 5.
The image is arranged in horizontal rows of addresses, with the address 0 in the upper left hand corner and the last address (in this case 3517 octal) in the lower right hand corner. The actual area of the image which appears on the display matrix is bounded by the corners defined in the drawing as addresses 0, 13, 3503 and 3516. The column 250 formed by addresses 14 to 3517 is called the "scratch" column, and is needed in the application of the rotator circuits.
The image is formed by columns and rows of 16 bit words. Since we are defining an image in sixteen shades of brightness and four bits are needed to define sixteen shades, we will need four levels of depth for every sixteen bit word. In other words, four sixteen bit words can define the brightness of sixteen lamps:
or, one 64 bit word consisting of four parts; A,B, C and D, will do the same job. The sixteen bits of the A level 1 15917~
of address 0 will define the 2 or (LSB) for the first sixteen lamps starting in the upper right hand corner.
The B level will define the 21 bits of the first sixteen lamps. The C level will define the 22 bits. The D level will define the 23 (MSB) data. IE we remove the fifteenth bit from the A, B, C and D levels and reassemble them into a four bit word, we would have a new word which would define (in binary) the brightness of the lamp in the upper left hand corner.
These four bit words are handy ways of order-ing the brightness data. This four bit word we will call a "pixel", as it completely defines the brightness of one picture element.
ROTATOR
The purpose of the rotator is to cause lines or text to move across the display buffer from right to left. The hardware allows the height and location of the line to be defined by the software. In addtion, the software controls the speed of travel and composition of the text. The hardware will, in response to a command, perform a single column left shift of all the data con-tained within a defined area of the buffer.
Figure 6 shows an area of the display buffer as it might be defined for rotation. (Figure 6 will detail -2g-J159~71 only the D-level but it should be understood that the action of rotation affects all levels of the display buffer simultaneously.~ In "I" the buffer and text area is empty.
In "II" the computer interface has loaded the scratch area with data that begins the text of a message. "III" shows the message after a rotation command has been issued.
"IV" shows it after the sixteenth rotation command. The scratch area is now empty and the next part of the message text must be loaded into it as shown in "V".
Another sixteen rotations and again the scratch column is empty. This process continues under software control until an entire message has travelled across the display buffer. Of course, after each rotation the resulting image would be transmitted to the matrix display board.
The image shifts in from the scratch column on the right. The data in the far left column shifts out the left side and is lost. Notice also that if something was left in the text area prior to starting the travelling message, it will shift out with the incoming data.
Referring to Figures 7a to 7c the operation of the rotator will be described. A command is issued by the computer Ifunction 3) which loads the starting address (upper right hand corner) of the area to be rotated.
This is always the top address in the scratch column ~, 1 ~5~171 This address is loaded into the SA (starting address) counter 252. At the same time the SA counter is loaded, its outputs provide the inputs to the CA (current address) counter 254 and it, too, is loaded. The width counter 256 is preset at this time. It loads the width of the display in columns.
A second command is issued which loads the height counter 258 with the binary value of the number of rows comprising the rotation area minus 1. At the same time the height is loaded, the rotate enable F/F
260 is set, beginning the rotation process.
The rotation process begins in the upper right hand corner. The contents of the display buffer are read into a set of four shift registers, 261-264; one each for the four levels A, B, C and D of the display buffer. We will confine our discussion to just the D
level, register 264. After the data is loaded, the con-trol logic will cause it to shift one bit to the left.
(Note that "left" is actually "right" on the schematic.
The left/right references used here pertain to what will be seen on the matrix display.) The leftmost bit is provided to a linking register formed by the F/F 266.
This will save it to be used as the right side input when we shift the next word. After shifting, the contents of the SR will be written back into the display buffer.
I ~9 17 ~
Next the CA counter 254 will be decremented, moving to the adjacent address on the left. The SA
counter 252 will be incremented. The width counter will be decremented 256. Again, the contents of the dis~lay buffer will be read into the SR, another shift cycle occurs, and then the data is written back into the display buffer. Notice the contents of the linking regis-ter became new data on the right side of the second word to be shifted. This process will continue moving the data across the display buffer until the last word in the row is processed. At that time the outPut of the width counter 256 will be zero, setting the end of row F/F 268. This causes the SA counter to increment to the starting address of the next row to be shifted, and the CA
counter will then load the new value from the SA. It will also decremen~ the height counter, reset the width counter, and clear the linking registers. We are now ready to begin shifting the second row of data.
The second and subsequent rows will be processed in the same way until the last word of the last row is shifted. At that time the height counter will generate the ROT DONE signal. This will case the ROT ENA F/F 260 to be reset and the ATTN F/F 270 to set, causing the BATTN
signal to tell the DRll-B that it has finished a rota-tion cycle.
~ 15~i71 The foregoing action is controlled by the timing circuits now to be described. When the ROT ENA
F/F 260 was set, a timing pulse generator formed bv a counter 272, a binary-to-decimal decoder 274, and a 4MHz xtal oscillator 276, was turned on. The results are a cyclical set of seven timing pulses emanating from decoder 274. These seven pulses are shown in Figure 8, numbered 1 to 7. They cause the read-shift-write process.
One cycle of pulses from 1 through 7 will shift the contents of one display buffer memory address.
Thirteen cycles will shift one row of data, 91 cycles will shift the seven rows of Figure 6.
Pulse 1 presets the two F/F's 278 and 27g.
F/F 278 sets the L/S (Load/Shift) mode of the SR's to load data from the DB. The F/F 279 sets the R/W of the display buffer to read. Pulse 1 also clears the end of row F/F 268.
Pulse 2 generates a load clock via OR gate 280. This causes the contents of the DB to be read into the SR's. It also clocks the end of row F/F 258 testing for the end of row condition.
Pulse 3 clears F/F 278 which controls the L/S
signal. This sets the SR's into the shift mode.
Pulse 4 generates a shift clock via OR gate 280 and buffer 282. This causes the contents of the SR and ~ 15917~
link registers 266 to shift one bit to the left. If the end of row F/F was set by pulse 2, then pul~se 4 is allowed through AilD gate 284 to provide an extra clock pulse to the SA counter.
Pulse 5 clears F/F 279 changing the R/W from the read to the write mode. The output of this F/F also causes the OC (output control) inputs of the SR's to go low via two OR gates 286 and 287. OC low places the con-tents of the SP~'s onto the DB, making its data available to be written into the display buffer.
Pulse 6 becomes the WSTBE pulse at tri-state buffer 288. This writes the data into the display buffer.
Pulse 7 via AND gate 290 decrements the CA
counter, and increments the SA counter. If the end of row F/F was set by pulse 2, then pulse 7 will have an alternate purpose. It will instead load the CA counter, decrement the height counter, load the width counter, and clear the linking registers. This is accomplished via AND gate 292 and 293, OR gates 294 and 296. If, in addition to being the end of row it is also the last row, then the height counter 258 will deliver pulse 7 as its borrow output generating the ROT DONE pulse. This termi-nates the rotators' operation by clearing the ROT ENA F/F
and setting the ATTN F/F.
The video controller 128 selects the Parameters for operation of the quantizer. lhe video controller con-tains an Intel 8085 microprocessor ~P). It monitors the video operator inputs, which include:
1. Joystick positi~n control for selecting desired portions of the video plcture to be displayed.
2. Image size selection controls.
3. Run/stop controls.
In additionJ it receives commands from the computer via the control bus and V/D interface.
1 1~917 1 The video control panel 130 is mounted in the operator's console~ It allows the video operator to select various display options which include: image size, image position, automatic gain, and automatic set-up (AGC and ASU).
TI~NSMITTER l22 The transmitter receives data from the V/D
interface 118, formats it and inserts the necessary addresses, then transmits the image to the video matrix board 132. The formating involves dividing each line of data into a left and right half, thereby reducing the data rate by half. An address header must be placed at the beginning of each line of data so that the matrix display logic at the board will know where to place each line it receives. The transmitter must also maintain a steady stream of lamp brightness data. The lamp bright-ness information, called ~ pulses, is generated by the generator 134 as determined by the four bit word from the quantizer 126. The ~ pulses are nultiplexed by the transmitter and continuously transmitted to both the left and right halves of the matrix board 13~. The details of this circuit are described in connection with Figures 1-4.
1 15g~7~
~ GEIIERATOR
The ~ génerator is used to generate three bursts of 15 pulses. Each burst is locked to one of the three power line phases: A, B, or C. Each pulse within a burst defines one of 15 lamp brightness intensity levels (the 16th level being the off condition). Adjustments on the ~ generator allow it to be set-up to render the desired brightness levels.
2~ATRIX DISPLAY BOAP~D 132 The matrix display is preferably made up of 40 watt incandescent lamps, arranged in a matrix M
lamps high by N lamps wide. The face of the display is formed by stacking modules of lamps, each module contain-ing a quantity of lamp trays. To the electronics involved in controlling the lamps, the precise number, placement, or size of the modules is unimportant. The electronics sees only an arrangement of lamp trays form-ing an electrical matrix of a predetermined size (21 x N).
Each lamp tray contains 24 lamps and is con-trolled by one triac control board card. Thirty triac cards are driven by one driver board. Two driver boards can be controlled by one controller board. The driver and controller board are connected to the high speed control cables via one I/O board. All of the above i 15~7~
(except the lamp tray) is contained within a control cabinet located at the board.
Each control cabinet has the capacity to drive 1,440 lamps. For reasons of packaging expedience, each cabinet can drive these lamps arranged only in an area 24 lamps wide by 60 lam~s high.
Each control cabinet is fed 3-phase power from a power distribution cabinet. The power feed is connected to a load center mounted on the side of each control cabinet. ~ithin each load center is a quantity of 20 amp circuit breakers, which provide power to the entire cabinet.
In reading the following detailed description of the transmitter it is important to remember:
All images displayed on the matrix board come either from the video converter or the display buffer, or both in combination. There is no direct path from the computer system to the transmitter.
The video converter generates images in a line-at-a-time process, scanning from top to bottom, left to right. This serial image construction will be called a "video format". The timing and number of sig-nals needed to control the image may change but this basic line-at-a-time, frame-by-frame process will always be the same.
The V/D interface under computer command routes the images.
The transmitter receives and sends the matrix images in a vi.deo format style. Except for minor buffer delays, tlle transmitter transmits to the video matrix display board in real time. Thus, one line received equals one line transmitted.
The matrix display board is divided into a left and right half. The display board control cabinets on the left side are daisy-chained to the left set of high speed cables; similarly, the right control cabinets are connected to the right set of high speed cables.
TRANSMITTER
The transmitter receives the output of the V/D
interface and ~ (phase) generator, formats and splits it into a left and right half, and then transmits the pixel address and lamp brightness information to the display board at a 3~z ner pixel rate.
The transmitter operates as both a master and slave device. It masters the AS~C (address sync), WCLK
(write clock), and ~M (multiplexed ~ pulses). These out-puts are generated as soon as power is applied. When pixel data is not being transmitted, the transmitter is in the idle state. The idle state maintains a steady 1 15~7 ~
flow of lamn brightness data, ~ pulses, in the form of ~1, to the display logic. The ~ nulses are derived fron the ~ ~en, to be described.
In the slave node the transmitter res~onds to the output of the V/D interface. When the V/D inter-face has an image to output to the display board, its output circuits generate the necessary timing and data in a video format. The transmitter responds by collect-ing the data and transmitting it to the matrix board.
When the transmitter begins to transmit pixel (or lamp data, LD) information it leaves the idle state and enters the transmit state. The operation of the transmitter can be best understood from a study of the pur~ose of its output signals.
TRANSMITTER OUTPUT
The output of the transmitter is arranged in essentially a video format. Thus it sends data in a horizontal line-at-a-time fashion. In this specifica-tion the terms "line" and "row" will be used inter-changeably. Line will most often be used to refer to the transmission of data. Row will usually be used when we are speaking of "rows of lamps". Three addi-tional terms, Lev, Mem and Line, will also be used in the description. These make up the three parts of the address which precedes each line of transmission.
Due to design limitations the output of data from the transmitter is set at 3~æ per pixel. The data received from the V/D interface may arrive at either 6.14Ml~z in tl~e x2 mode, or 4.09MIIz in the x1.3 mode.
The data arriving in the x2 mode has a line-to-line period of 63.5 usec. Since the transmitter's output operating at 3~z would take more than ~8 usec to pro-cess this line of data, it becomes necessary to divide each line into two halves. Thus the transmitter will have two independent sets of output signals, one to drive the left side of the matrix and one to drive the right.
Each output signal set will contain seven signal types. They are:
ASYNC - address sync; a 333ns Pulse which indicates that the next 12 LD3 data bits are to be inter-preted as an address.
WCLK - write clock; a 3MHz clock which occurs in bursts between ASY~C's. In the idle state 12 WCLK's make up a burst. In the transmit state the left output circuits generate a burst of 120 WCLK's while the right's burst contains 96 WCLK's. The front edge of each WCLK
pulseisused to sample the contents of the four LD signals, and the ~M line. WCLK bursts always occur in multiples of 12.
1 159~71 LD0 through LD3 - Lam~ data; contains the four bits of pixel data during the transmission of each line of data. LD3 will contain the line address which begins each line o~ transmission. In the idle state all the LD lines will contain zeros.
~ M - multiplexed ~ pulses; contains the six pulses obtained from the ~ gen, as well as the locally generated era (erase) signal, tine multiplexed under the last seven WCLK's of each multiple of 12 WCLI~'s.
ASYNC indicates the beginning of a 1~ WCLK cycle, but during a transmission, a local divide-by-12 will recycle the ~M data. Thus ~M data is continuously outputted, both during the idle and transmit states.
The top of timing diagram, Figure 2, shows the relationship between the ASYNC, WCKL, LD and ~M signals during both the idle and transmit states. The numbers written into each group of 12 WCLK's indicate the COL's of lamps within which the data belongs. Recall that the term COL refers to a positional address across each line of transmission. Its address is inferred by the matri~ board logic by simply dividing a line of WCLK's by 12 and incrementing a counter. Each display board control cabinet will be coded to look for its particular COL. The transmission shown in Figure 17 contains COL's 1 through 9 which would correspond to 108 lamps, which 1 15~73 would mean a transmission to the left side o.f the matrix board. A COL designation of zero indicates a ~eriod of 12 I~CLK's during which time an address is transmitted on the LD3 line. Notice the zero occurs after each ASYNC pulse.
To convert Figure 2 into a transmission to the right side of the matrix you would sim~ly delete COL's 8 and 9 and return to the idle state immediately following COL number 7.
Before sending a line of data to the matrix we must precede it with an address that will identify to the three levels of control cabinets where it belongs.
Figure 3 shows the matrix board as it appears in terms of transmitter addresses. The three comPOnent parts that make up the address are called:
LEV - level; indicating a level of cabinets numbered from one starting at the top of the matrix.
Each LEV can drive, for example, 60 rows of lamps.
MEM - memory; each LEV contains 3 MEM's numbered from the top as Ml, M2 and M3. Each MF.M may drive, for exam~le, 20 rows of lamps.
LINE - line; each MEM contains 20 lines or rows of lamps numbered 0-19. To identify which row the trans-mission belongs to, 5 bits of the address word are iden-tified with the LINE value.
The address is made uP of 12 bits of data, and organized in the following format.
All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al A0 spare LEV MEM LINE
0 0000 00 0000~
through through through This address word, combined with the COL, can locate every pixel on each half of the matrix board.
From Figure 3 it will be clear to those skilled in the art the purpose of the addressing method and its ability to address unique groups of twelve pixel rows on both the left and right side of the matrix.
TRANSMITTER OPERATION
As stated earlier, the transmitter will receive one line of data from the V/D interface and, because of data rate limitations, divide it into two lines of output data called "left" and "right". In front of both the left and right transmission halves the transmitter will insert an address. Since each line of 1ata has a unique address, the address stuck onto the left and right half of each line transmitted will be the same.
1 15gl73 The data received from the V/D interface is at either 6.14 M~lz or at 4.09 ~lz. When it departs the transmitter it is going at 3.0MHz. To accomplish this data rate reduction, FIFO (first in, first out) shift registers are used. One is needed for each of the left and right outputs. In the transmitter's block diagram, Figure 4, they can be seen identified as the left and right buffers.
This lays the groundwork necessary to under-stand the input and output flow of data through the transmitter. Using the block diagram of Figure 4 it is possible to trace the flow of data coming from the V/D
interface and departing the tranmitter's output. The conditions at the input will be those for a x2 image.
The SF~I (start frame) pulse arrives at the beginning of a frame and initializes the transmitter.
Via the address control logic 520 SFRM will set the LEV
portion of the address counter 522 to 0001. The three LSB's of LEV will go up to the select inputs of the level starting address multiplexer 524. The data inputs to the level starting address multi~lexer are the jumpered MEM
and LINE star~ing values for each level. Selecting the LEV OOll input will place the starting address needed for the first line of transmission into the address counter. SF~M goes to the MR (master reset) of the right and left buffers, setting them empty.
1 1~9171 The transmitter next receives the SLIN (start line) pulse from the V/D interface. SLIN goes to the input control logic 526 and sets the input shift regis-ter 528 to the parallel load mode. SLIN causes ACLK
(address clock) to be generated in the address control logic. The back edge of ACLK will cause the contents of the address counter 522 to paral.lel load into the input register 528. The back edge of ACLK will also cause the address counter to increnent, setting up the next line address to be transmitted. ACLK will also clear the parallel mode from the input shift register and allow the input control logic 526 to set the shift register to the shift right mode.
The transmitter is now ready to receive the VD0-VD3 data from the V/D interface. VTCLK (video-transmit clock) will accompany the data and make it possible for the transmitter to shift the data into the input shift register 528. The first twelve VTCLK's will shift twelve pixels of data into the register while simultaneously shifting the previously loaded address from the address counter 522 into both the left and right buffers 530 and 532.
As soon as the twelfth VTCLK has been counted by the input control logic it will no longer allow the VTCLK's to shift into both buffers; it will now direct the data to only the left buffer 530.
1 ~Sg~71 The next twelve VTCLK's will shift twelve more pixels of data into the inPUt register. As the new data comes in, the previous data flows out into the left buffer. As should be apparent, the left buffer is collecting the data which forms the first line of a transmission. It collected the address and then the lamp data.
The process continues until the left buffer is filled with twelve address bits andJ for example, 108 pixels. The inPut control logic has been faithfully counting the loading of the left buffer. When the 108th pixel is loaded, by the 120th VTCLK, the in~ut control logic will allow no more data into the left buffer. It will now route the VTCLK's to the right buffer. The right buffer will take the next, for example, 72 VTCLK's and load 72 additional pixels. After the 192nd VTCLK the input register will have the last twelve pixels of data still residing in it. Remember, the first twelve VTCLK's were used to load the address, so the buffer is always lagging the data by twelve VTCLK's. The input control logic will take the output of a 6 MHz xtal oscillator 53~ and use it to transfer the final twelve pixels into the right buffer.
This completes the input transfer of one line of data from the V/D interface. Within a few short 1 7 ~
microseconds the V/D interface will be sending the transmitter the second line of data. The next line will again be preceded by the SLI~I pulse. As before, the input register 528 will be loaded with the contents of the address counter 522, now holding the address of the second line. The next ACLK will again increment the address counter, this time to the address of the third line.
The VTCLK's and LD for the second line will pour in and again the left and right buffers will become the depository of the address and data for the second line: And so on until 144 lines of data have been received, addressed and shifted into the left and right buffers.
To keep track of the levels of Figure 3 the address counter is equipped with a detector circuit which identifies the end or last line of each level. At that time the LEV bits to the level starting address multi-plexer will address the next LEV and cause the subsequent ACLK to load the address counter with its output.
The left and right buffers, in most applications, are not of sufficient length to receive an entire line.
This means that the image received from the V/D interface cannot be entirely contained by the transmitter and, l 15917 1 therefore, the outputting of data from the transmitter ~ust begin as soon as possible to ~revent the buffers from overflowing. Since the control of data from the left and right buffers is virtually identical, the explanation will follow just the left buf,er.
Data shifted into the left buffer 530 will quickly bubble through to its output. It will remain there until a shift out pulse is received to remove it.
Each shift out will extract one pixel of data just as one shift in loaded one pixel.
When the data loaded into the buffer ap~ears at the output the LOR (left outnut ready) signal there-from will indicate to the left output control logic 536 that a transmission can begin. Prior to receiving LOR
the output control logic was in the idle state, sending out ASYNC, WCLK and ~M data through the left data selector 538 to the left side of the matrix board.
When LOR arrives the idle state will terminate with the next ASYNC pulse and the transmit state will begin. The output control logic 536 will begin to empty the buffer with each WCLK. One hundred twenty WCLK's will send the first line of pixels to the display logic on the left side of the matrix.
The output control logic will send exactly 120 WCLK's after which it will generate the next ASY~C
1 159 i7 l pulse. If the buffer is e~pty the ASYNC will cause the idle state to resume. Jf the next line of data is in the buffer, then the ASYNC will see the LOR set high once again. This will cause the begim~ing of the next trans-mit state to follow immediately after the previous one.
In this way the output control logic will process each line of data to the matrix board. Notice that it does not care about addresses. It ~just passes the data along exactly as it was received.
The left and right ~ pulse multiplexer 538 are identical. They each receive the six lines of ~
pulse data produced by the ~ gen. A board erase circuit 540 feeds the seventh piece of data to the multiplexer.
The output control logic generates the timing pulses necessary to drive their respective multiplexers. For every twelve WCLK's produced by the output control logic, one multiplexing cycle cf the seven data inputs will occur.
Summaring the description of the transmitter it will be appreciated that:
The transmitter always transmits com~lete lines of data. If for some reason the V/D interface sends a short line, the transmitter circuits will detect the condition and fill in the remainder of the line with off lamp data. The VTCLK signal initiates the transmission.
1 ~S9171 SFRM and SLIN alone will cause no output fron the trans-mitter. Transmission may end after any line has been received. The transmitter will not fill in the balance of a short frame as it does for a short line. When an image to be transnitted is derived from the V/D inter-face in the x1.3 resolution, it will be coming as two frames of interlaced data. This requires the address control logic to modify the way it increments the address counter. The FLDl (field one) and RESl. 3 (resolution x1.3) signals from the video converter will inform the address control logic that a x1.3 image is coming. In response the address control logic will start on either the first or second line of the display and increment by twos as each SLIN is received.
DIS~LAY BUFFER
The display buffer 116 is a R~I memory con-figured 64 x 2048. The display buffer includes the rotator circuits. The rotator is used to move messages across the video matrix board.
The display buffer is used as a temporary place to store an image. It is important to understand how the board image is mapped into the display buffer memory to perceive the operation of the rotator circuits.
'~ 1S9~71 The display buffer is used to contain pictorial images in a digital form. The organization of the image is arranged in such a way as to allow efficient design of the addressing circuits which must interface with it.
Since video data i5 received at high speeds, the most efficient interface techniques would favor an addressing scheme organized around data in a video format. This yields the arrangement shown in Figure 5.
The image is arranged in horizontal rows of addresses, with the address 0 in the upper left hand corner and the last address (in this case 3517 octal) in the lower right hand corner. The actual area of the image which appears on the display matrix is bounded by the corners defined in the drawing as addresses 0, 13, 3503 and 3516. The column 250 formed by addresses 14 to 3517 is called the "scratch" column, and is needed in the application of the rotator circuits.
The image is formed by columns and rows of 16 bit words. Since we are defining an image in sixteen shades of brightness and four bits are needed to define sixteen shades, we will need four levels of depth for every sixteen bit word. In other words, four sixteen bit words can define the brightness of sixteen lamps:
or, one 64 bit word consisting of four parts; A,B, C and D, will do the same job. The sixteen bits of the A level 1 15917~
of address 0 will define the 2 or (LSB) for the first sixteen lamps starting in the upper right hand corner.
The B level will define the 21 bits of the first sixteen lamps. The C level will define the 22 bits. The D level will define the 23 (MSB) data. IE we remove the fifteenth bit from the A, B, C and D levels and reassemble them into a four bit word, we would have a new word which would define (in binary) the brightness of the lamp in the upper left hand corner.
These four bit words are handy ways of order-ing the brightness data. This four bit word we will call a "pixel", as it completely defines the brightness of one picture element.
ROTATOR
The purpose of the rotator is to cause lines or text to move across the display buffer from right to left. The hardware allows the height and location of the line to be defined by the software. In addtion, the software controls the speed of travel and composition of the text. The hardware will, in response to a command, perform a single column left shift of all the data con-tained within a defined area of the buffer.
Figure 6 shows an area of the display buffer as it might be defined for rotation. (Figure 6 will detail -2g-J159~71 only the D-level but it should be understood that the action of rotation affects all levels of the display buffer simultaneously.~ In "I" the buffer and text area is empty.
In "II" the computer interface has loaded the scratch area with data that begins the text of a message. "III" shows the message after a rotation command has been issued.
"IV" shows it after the sixteenth rotation command. The scratch area is now empty and the next part of the message text must be loaded into it as shown in "V".
Another sixteen rotations and again the scratch column is empty. This process continues under software control until an entire message has travelled across the display buffer. Of course, after each rotation the resulting image would be transmitted to the matrix display board.
The image shifts in from the scratch column on the right. The data in the far left column shifts out the left side and is lost. Notice also that if something was left in the text area prior to starting the travelling message, it will shift out with the incoming data.
Referring to Figures 7a to 7c the operation of the rotator will be described. A command is issued by the computer Ifunction 3) which loads the starting address (upper right hand corner) of the area to be rotated.
This is always the top address in the scratch column ~, 1 ~5~171 This address is loaded into the SA (starting address) counter 252. At the same time the SA counter is loaded, its outputs provide the inputs to the CA (current address) counter 254 and it, too, is loaded. The width counter 256 is preset at this time. It loads the width of the display in columns.
A second command is issued which loads the height counter 258 with the binary value of the number of rows comprising the rotation area minus 1. At the same time the height is loaded, the rotate enable F/F
260 is set, beginning the rotation process.
The rotation process begins in the upper right hand corner. The contents of the display buffer are read into a set of four shift registers, 261-264; one each for the four levels A, B, C and D of the display buffer. We will confine our discussion to just the D
level, register 264. After the data is loaded, the con-trol logic will cause it to shift one bit to the left.
(Note that "left" is actually "right" on the schematic.
The left/right references used here pertain to what will be seen on the matrix display.) The leftmost bit is provided to a linking register formed by the F/F 266.
This will save it to be used as the right side input when we shift the next word. After shifting, the contents of the SR will be written back into the display buffer.
I ~9 17 ~
Next the CA counter 254 will be decremented, moving to the adjacent address on the left. The SA
counter 252 will be incremented. The width counter will be decremented 256. Again, the contents of the dis~lay buffer will be read into the SR, another shift cycle occurs, and then the data is written back into the display buffer. Notice the contents of the linking regis-ter became new data on the right side of the second word to be shifted. This process will continue moving the data across the display buffer until the last word in the row is processed. At that time the outPut of the width counter 256 will be zero, setting the end of row F/F 268. This causes the SA counter to increment to the starting address of the next row to be shifted, and the CA
counter will then load the new value from the SA. It will also decremen~ the height counter, reset the width counter, and clear the linking registers. We are now ready to begin shifting the second row of data.
The second and subsequent rows will be processed in the same way until the last word of the last row is shifted. At that time the height counter will generate the ROT DONE signal. This will case the ROT ENA F/F 260 to be reset and the ATTN F/F 270 to set, causing the BATTN
signal to tell the DRll-B that it has finished a rota-tion cycle.
~ 15~i71 The foregoing action is controlled by the timing circuits now to be described. When the ROT ENA
F/F 260 was set, a timing pulse generator formed bv a counter 272, a binary-to-decimal decoder 274, and a 4MHz xtal oscillator 276, was turned on. The results are a cyclical set of seven timing pulses emanating from decoder 274. These seven pulses are shown in Figure 8, numbered 1 to 7. They cause the read-shift-write process.
One cycle of pulses from 1 through 7 will shift the contents of one display buffer memory address.
Thirteen cycles will shift one row of data, 91 cycles will shift the seven rows of Figure 6.
Pulse 1 presets the two F/F's 278 and 27g.
F/F 278 sets the L/S (Load/Shift) mode of the SR's to load data from the DB. The F/F 279 sets the R/W of the display buffer to read. Pulse 1 also clears the end of row F/F 268.
Pulse 2 generates a load clock via OR gate 280. This causes the contents of the DB to be read into the SR's. It also clocks the end of row F/F 258 testing for the end of row condition.
Pulse 3 clears F/F 278 which controls the L/S
signal. This sets the SR's into the shift mode.
Pulse 4 generates a shift clock via OR gate 280 and buffer 282. This causes the contents of the SR and ~ 15917~
link registers 266 to shift one bit to the left. If the end of row F/F was set by pulse 2, then pul~se 4 is allowed through AilD gate 284 to provide an extra clock pulse to the SA counter.
Pulse 5 clears F/F 279 changing the R/W from the read to the write mode. The output of this F/F also causes the OC (output control) inputs of the SR's to go low via two OR gates 286 and 287. OC low places the con-tents of the SP~'s onto the DB, making its data available to be written into the display buffer.
Pulse 6 becomes the WSTBE pulse at tri-state buffer 288. This writes the data into the display buffer.
Pulse 7 via AND gate 290 decrements the CA
counter, and increments the SA counter. If the end of row F/F was set by pulse 2, then pulse 7 will have an alternate purpose. It will instead load the CA counter, decrement the height counter, load the width counter, and clear the linking registers. This is accomplished via AND gate 292 and 293, OR gates 294 and 296. If, in addition to being the end of row it is also the last row, then the height counter 258 will deliver pulse 7 as its borrow output generating the ROT DONE pulse. This termi-nates the rotators' operation by clearing the ROT ENA F/F
and setting the ATTN F/F.
Claims (8)
1. A high resolution system for displaying video images on a plurality of variable intensity display devices in real time, said images representing selected portions of video frames received from a video source in raster (TV) format, said system comprising:
(a) a video converter receiving the raster lines of video information corresponding to each frame, said converter including quantizing means for generating digital data representative of the relative intensity of said video information at selected points on selected raster lines of said frames and means for selecting which lines and the number of said points per line for which digital data is generated, said digital data being generated at a first rate, sufficient to keep up with the rate at which the video information is received;
(b) transmitter means receiving said digital data at said first rate for transmitting it to said display devices in a modified raster line format without frame storage, said transmitter means including means for dividing each line of digital data into at least two segments and means for transmitting in parallel the data for each of said segments to said display devices, whereby the line at a time raster format of the video information is retained but the effective rate of transmission of data to the display devices corresponding to each segment is reduced to a second rate approximately equal to said first rate divided by the number of said segments, the reduced data rate permitting display of an increased number of data points per raster line and/or the use of more raster lines from the video source;
(c) interface means for selectively connecting said converter to said transmitter means;
(d) means for controlling the operation of said interface means thereby directing the transfer of data betwween said converter and transmitter means.
(a) a video converter receiving the raster lines of video information corresponding to each frame, said converter including quantizing means for generating digital data representative of the relative intensity of said video information at selected points on selected raster lines of said frames and means for selecting which lines and the number of said points per line for which digital data is generated, said digital data being generated at a first rate, sufficient to keep up with the rate at which the video information is received;
(b) transmitter means receiving said digital data at said first rate for transmitting it to said display devices in a modified raster line format without frame storage, said transmitter means including means for dividing each line of digital data into at least two segments and means for transmitting in parallel the data for each of said segments to said display devices, whereby the line at a time raster format of the video information is retained but the effective rate of transmission of data to the display devices corresponding to each segment is reduced to a second rate approximately equal to said first rate divided by the number of said segments, the reduced data rate permitting display of an increased number of data points per raster line and/or the use of more raster lines from the video source;
(c) interface means for selectively connecting said converter to said transmitter means;
(d) means for controlling the operation of said interface means thereby directing the transfer of data betwween said converter and transmitter means.
2. The system according to Claim 1 wherein said display devices are operated by a three phase AC
power supply and said transmitter means includes a phase generator for producing signals for synchronizing the digital data to the correct phase of said AC power supply.
power supply and said transmitter means includes a phase generator for producing signals for synchronizing the digital data to the correct phase of said AC power supply.
3. The system according to Claim 1 wherein said system further includes a display buffer capable of storing digital data representative of selected portions of a complete frame of video information, said interface means permitting transfer of digital data from said converter to said buffer and transfer of data from said buffer to said transmitter means for transmission to said display devices, said buffer permitting the capture and storing of anima-tions, photographs and messages for processing and subse-quent display.
4. The system according to Claim 1 further including rotation means for manipulating selected digital data stored in said buffer to move data stored in selected memory locations of said buffer to successively displaced locations whereby when the display devices repetitively receive data from the buffer the data will cause the corresponding display to appear to move across the display devices in the manner of a travelling sign.
5. The system according to Claim 1 wherein said video converter includes:
(a) a quantizer having a phase lock loop (PLL) circuit operable at a selectable rate, said selectable rate determining the number of selected points on said raster line for which digital data is generated;
(b) means for selecting the rate at which said PLL operates.
(a) a quantizer having a phase lock loop (PLL) circuit operable at a selectable rate, said selectable rate determining the number of selected points on said raster line for which digital data is generated;
(b) means for selecting the rate at which said PLL operates.
6. The system according to Claim 1 wherein said line dividing means includes:
(a) an input register receiving said data;
(b) buffer means for each of said segments;
(c) logic means for cyclically and sequentially transferring said data from said input register to said segment buffers.
(a) an input register receiving said data;
(b) buffer means for each of said segments;
(c) logic means for cyclically and sequentially transferring said data from said input register to said segment buffers.
7. The system according to Claim 6 wherein said parallel transmitting means includes output control logic for the buffer means for causing the data segments in the buffer means to be transmitted in parallel to said display devices at said second rate whereby the entire line of data is transmitted to said display devices in real time without the need for full frame buffer storage.
8. The system according to Claim 4 wherein said rotation means includes:
(a) means for cyclically and sequentially addressing selected locations in said buffer to cause data to be read from and restored to said locations;
(b) shift register means receiving the data from each addressed buffer location for shifting said data a selected number of bits in a selected direction and restoring the shifted data to the same buffer location;
(c) linking register means operatively connected to said shift register means for receiving and temporarily storing the bits shifted out one side of the shift register means during each shift cycle and for inserting the shifted bits back into the other side of said shift register means during the next shift cycle corresponding to the next buffer address in the sequence, whereby the data in the addressed locations are shifted in a selected direction across the buffer so that a repetitive display of the data in the buffer, after each shift cycle is complete, will cause the data to appear to travel across the matrix in the manner of a travelling sign display.
(a) means for cyclically and sequentially addressing selected locations in said buffer to cause data to be read from and restored to said locations;
(b) shift register means receiving the data from each addressed buffer location for shifting said data a selected number of bits in a selected direction and restoring the shifted data to the same buffer location;
(c) linking register means operatively connected to said shift register means for receiving and temporarily storing the bits shifted out one side of the shift register means during each shift cycle and for inserting the shifted bits back into the other side of said shift register means during the next shift cycle corresponding to the next buffer address in the sequence, whereby the data in the addressed locations are shifted in a selected direction across the buffer so that a repetitive display of the data in the buffer, after each shift cycle is complete, will cause the data to appear to travel across the matrix in the manner of a travelling sign display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000378860A CA1159171A (en) | 1981-06-02 | 1981-06-02 | High resolution video display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000378860A CA1159171A (en) | 1981-06-02 | 1981-06-02 | High resolution video display system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1159171A true CA1159171A (en) | 1983-12-20 |
Family
ID=4120121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000378860A Expired CA1159171A (en) | 1981-06-02 | 1981-06-02 | High resolution video display system |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1159171A (en) |
-
1981
- 1981-06-02 CA CA000378860A patent/CA1159171A/en not_active Expired
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