CA1153831A - Field effect transistor with a short channel lenght - Google Patents
Field effect transistor with a short channel lenghtInfo
- Publication number
- CA1153831A CA1153831A CA000352698A CA352698A CA1153831A CA 1153831 A CA1153831 A CA 1153831A CA 000352698 A CA000352698 A CA 000352698A CA 352698 A CA352698 A CA 352698A CA 1153831 A CA1153831 A CA 1153831A
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- source
- region
- drain
- doping
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- 230000005669 field effect Effects 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000000576 coating method Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
ABSTRACT
Disclosed is a field effect transistor with a short effective channel length which can be realized with greater certainty than in known field effect transistors with two gate electrodes. Undesirable capacitances in the transistor can be made small. The transistor comprises a semi-conductor body with source and drain regions and first and second gates which each cover a part of the body between the source and drain regions.
The gates are insulated from the body. The first gate is on the source side and extends in the source-drain direction a distance corresponding to the effective channel length of the transistor. The second gate is parti-ally above the first gate and insulated from it. A region of the body between the source and drain which is not covered by the first gate is doped oppositely to the rest of the body.
Disclosed is a field effect transistor with a short effective channel length which can be realized with greater certainty than in known field effect transistors with two gate electrodes. Undesirable capacitances in the transistor can be made small. The transistor comprises a semi-conductor body with source and drain regions and first and second gates which each cover a part of the body between the source and drain regions.
The gates are insulated from the body. The first gate is on the source side and extends in the source-drain direction a distance corresponding to the effective channel length of the transistor. The second gate is parti-ally above the first gate and insulated from it. A region of the body between the source and drain which is not covered by the first gate is doped oppositely to the rest of the body.
Description
~$~3~-The invention concerns a field effect transistor with a short channel len~th.
BACKGROUND OF THE INVENTION
lield effèct transistors of this kind with a short active channel length are desired in the case of analog processing of electric signals where a high steepness and a high inner resistance is important. Also, where as small capacitances as possible are sought between the source region, the drain region and the gate on the one hand and the semiconductor body on the other hand.
Field effect transistors of this kind are known, for example, from the German OS 2,729,656, corresponding to United States Serial Number 913,835, assigned to the same assignee as the present invention. Therein, a first gate, which is applied to a semiconductor body, covers the semiconductor region which lies between the source region and the drain region with the exception of a strip-shaped semiconductor region which borders directly on the source region. A second gate, which is provided partially above the first and is separated from this by means of an insulating layer, covers this strip-shaped region. The second gate is connected with a control voltage, whereas the first gate is connected with a bias voltage source. In the case of a field effect transistor of this kind, nevertheless, the active channel length which coincides with the width of the strip-shaped region, measured in source-drain direction, depends upon the lateral limits of several partial structures which are applied in consecutive method steps, whereby the lateral tolerances which are pregiven in the definition of the same under certain circumstancks add to one another. These tolerances, which in particular go back to uncontrollable errors in the adjustment of photomasks, lead to the fact that the short channel length which is aimed for cannot be achieved with as great 1~5;~8;~
a certainty as would be desirable in many cases.
k,.".~,"
~` Other ~e~ field effect transistors with even shorter channel lengths are manufactured according to the DIMOS (double implanted MOSFET) technology which is described in the technical digest IEDM, 1977, pages 399-401.
Here, a double implantation of doping substances is undertaken after the place-ment of a gate which is designed especially with canted edges. Source and drain regions which lie directly next to the gate arise, whereby, under the source region, a zone is formed which obtains a doping which corresponds to base doping of the semiconductor body with respect to the conductivity type, nevertheless which displays a higher degree of doping. Under a canted edge of the gate, this zone displays a border region which extends up to the inter-face of the semiconductor body, which is covered by the insulating layer which bears the gate. The border region on its part which is next to the interface then represents the very short effective channel region of the transistor. In the case of these field effect transistors, nevertheless, a relatively large capacitance is present between the source region and the semiconductor body, and also a relatively large Miller capacitance between the gate and the drain region.
The invention is based upon the problem of providing a field effect transistor which represents an especially favorable compromise with respect to the effective channel length and the undesired Miller capacitance. For this, according to the invention, a field effect transistor of the kind is formed which displays the features defined by the claims.
BRIEF SUMMARY OF THE INVENTION
The advantage which can be attained with the present invention consists especially in that a short effective channel length can be realized wlth significantly greater certainty than in the case of the known field ~1$383t.
effect transistors with two gate electrodes, whereby, however, the undesired capacitances which occur between the source region and the gate on the one hand and the semiconductor body on the other hand as well as the capacitances between the gate and the drain regions are smaller than in the case of the transistors manufactured in DrMOS tecimology. Another advantage with respect to DIMOS transistors is to be seen in that the limiting effect which is present in the case of these with respect to the maximum drain current is dis-connected to a large extent by means of a sufficiently large bias voltage at the second gate, so that the short effective channel length can be fully utiliæed with respect to the attainable steepness. Further, the transistor according to the invention can be produced according to methods which are compatible with the double silicon gate technology, so that the simultaneous manufacturing of transistors according to the invention with other components prepared in the technology named is possible without difficulties. A second embodiment form of the invention is the case where the blocking layer capacitances of the transistor are further decreased. Still another embodi-ment is directed toward further designs of the invention which guarantee an especially high steepness of the transistor. Another embodiment of the transistor according to the present invention is one which possesses an especially high breakthrough voltage. Methods of forming the present inven-tion are herein disclosed, which are particularly advantageous for the manu-facture of field effect transistors according to the invention.
Thus, in accordance with a broad aspect of the invention there is provided a field effect transistor with a short channel length comprising a semiconductor body having a base doping of one conductivity type, said body having source and drain regions of the opposite conductivity type which lie at the interface of said semiconductor body, source and drain electrodes 1~53~B3~
respectively connected to said source and drain regions, first and second gates which each cover a part of said semiconductor body region which lies between said source and said drain regions and which gates are separated from said body by means of a first electrical insulating layer, said first gate being located at the source side and being connected with a control voltage, said second gate ~eing located on the drain side and being connected to a terminal of a bias voltage source, characterized by said first gate having a dimension in the source-drain direction which corresponds to the effective channel length of said field effect transistor, said second gate consisting of an electrically conducting coating which extends from said drain to said first gate and is partially above said first gate and is separated by means of a second electrically insulating layer from said first gate and that the part of said semiconductor region lying between said source and said drain which is not covered by said first gate being provided with a zone which is next to said interface, which zone displays a doping which is opposite to said base doping of said body, and said zone extending from said drain to the edge of said first gate nearest said drain and said first gate not extending over said zone, and said second gate not connected to said source region.
In accordance with another broad aspect of the invention there is provided a field effect transistor of the type having a short channel length, comprising a semiconductor body of one conductivity type having highly doped source and drain regions in one interface of said substrate of the opposite conductivity type, a zone region in said interface of the same conductivity type as said drain and source regions but less doped than said source and drain regions and which lies adjacent to said drain region and which extends from said drain region to a point short of said source region, thereby to provide a short channel between said source region and said zone region, a -3a-first non-electrical conducting coating of substantially uniform thickness on said interface, a first gate formed by a layer of electrical conducting material on said first non-electrical conducting material above a region of said body which provides a short channel, a second insulating layer covering said first gate electrode, a second gate electrode formed of electrically conducting material on said first non-conductive coating above said zone region which extends from adjacent said drain region to said short channel region, terminal means for connecting said first gate to a control voltage, terminal means for connecting a biasing potential to said second gate, terminal means for connecting said source region to a set reference potential, means for connecting said drain to a potential source, said second gate not connected to said source region.
In accordance with another broad aspect of the invention there is provided a method for the production of a field effect transistor character-ized in that a semiconductor body which is provided with a base doping is covered on an interface with a first electrically insulating layer, that upon this layer a first gate which defines an effective channel length is placed, that a zone region is formed in said interface by means of a doping process, said zone region being of the same conductivity type as source and drain regions of said transistor but less doped than said source and drain regions and extending from said drain region to a point short of said source region whereby the first gate forms a part of a first doping mask, that after the covering of said first gate by means of a second electrically insulating layer, forming a second gate on said first and second electrically insulating layer such that it partially overlaps the first gate, by means of a further doping process, said source and said drain regions are produced, whereby parts of said first and said second gate serve as parts of a second doping -3b-~S~33;1 mask, said source region, said drain reg:ion, and first and second gates are provided with electric leads.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawing, a longitudinal section through a fie].d effect transistor according to the present invention is depicted.
DESCRIPTION OF PREFERRED EMBODIMENTS
A semiconductor body 1 is provided which consists, for example, -3c-of p-doped silicon. At an interface of the same, which is designated as la, are located an n -doped source region 2 and an n -doped drain region 3. The semiconductor region lying between these regions is partially covered by a first gate 4 and a second gate 5, which gates are separated, by means of a thin electrically insulating layer 6~ from the interface la. Between the gate 4 and the gate 5, a second electrically insulating layer 7 is located.
In the illustrated embodiment being observed~ the insulating layers 6 and 7 preferably consist of SiO2. The regions 2 and 3 as well as the gate 4 and the gate 5 are provided with electric leads 8, 9, 10 and 11.
Under the gate 5 on the interface la, an n-doped zone 12 is provided which is directLy next to the region 3. The manufacture of this zone proceeds in a practical manner by means of a doping step which is undertaken after the placing of the gate 4 and in which the gate 4 serves as a doping mask. In this manner, the gate 4 with its length which is measured in source-drain direction determines the effective channel length L of the transistor, which reaches from the source region 2 to the next-lying border of the zone 12 with great precision. Only after the production of the zone 12 is then the gate 5 formed out of an electrically conducting coating which is applied upon the insulating layers 6 and 7. Thereby, a part of this coating overlaps the gate 4.
In a first case of operation, the lead 8 is placed at a set reference potential, for example, ground potential, the lead 9 at a positive voltage VD
and the lead 11 at a positive bias voltage V, while a gate voltage Ug, which controls the conductivity of the short partial channel which is designated as L, is supplied to the lead 10. Thereby, the gate voltage Ug controls the charge carrier transport between the regions 2 and 3. In another case of operation, the lead 9 lies at a supply voltage VDD and the lead 8 lies at a voltage Us, ~lS~3~
whereas a bias voltage V is supplied to the lead 11 and a gate voltage Ug which controls the conductivity of the partial channel is supplied to the lead 10 .
For the more precise explanation of the invention, in the follow-ing, several doping examples are cited. Thereby, first, a p-doped semi-conductor body is begun which displays a base doping, whereby an impurity concentration of approximately 1015 to 1016 cm 3 is present. The regions
BACKGROUND OF THE INVENTION
lield effèct transistors of this kind with a short active channel length are desired in the case of analog processing of electric signals where a high steepness and a high inner resistance is important. Also, where as small capacitances as possible are sought between the source region, the drain region and the gate on the one hand and the semiconductor body on the other hand.
Field effect transistors of this kind are known, for example, from the German OS 2,729,656, corresponding to United States Serial Number 913,835, assigned to the same assignee as the present invention. Therein, a first gate, which is applied to a semiconductor body, covers the semiconductor region which lies between the source region and the drain region with the exception of a strip-shaped semiconductor region which borders directly on the source region. A second gate, which is provided partially above the first and is separated from this by means of an insulating layer, covers this strip-shaped region. The second gate is connected with a control voltage, whereas the first gate is connected with a bias voltage source. In the case of a field effect transistor of this kind, nevertheless, the active channel length which coincides with the width of the strip-shaped region, measured in source-drain direction, depends upon the lateral limits of several partial structures which are applied in consecutive method steps, whereby the lateral tolerances which are pregiven in the definition of the same under certain circumstancks add to one another. These tolerances, which in particular go back to uncontrollable errors in the adjustment of photomasks, lead to the fact that the short channel length which is aimed for cannot be achieved with as great 1~5;~8;~
a certainty as would be desirable in many cases.
k,.".~,"
~` Other ~e~ field effect transistors with even shorter channel lengths are manufactured according to the DIMOS (double implanted MOSFET) technology which is described in the technical digest IEDM, 1977, pages 399-401.
Here, a double implantation of doping substances is undertaken after the place-ment of a gate which is designed especially with canted edges. Source and drain regions which lie directly next to the gate arise, whereby, under the source region, a zone is formed which obtains a doping which corresponds to base doping of the semiconductor body with respect to the conductivity type, nevertheless which displays a higher degree of doping. Under a canted edge of the gate, this zone displays a border region which extends up to the inter-face of the semiconductor body, which is covered by the insulating layer which bears the gate. The border region on its part which is next to the interface then represents the very short effective channel region of the transistor. In the case of these field effect transistors, nevertheless, a relatively large capacitance is present between the source region and the semiconductor body, and also a relatively large Miller capacitance between the gate and the drain region.
The invention is based upon the problem of providing a field effect transistor which represents an especially favorable compromise with respect to the effective channel length and the undesired Miller capacitance. For this, according to the invention, a field effect transistor of the kind is formed which displays the features defined by the claims.
BRIEF SUMMARY OF THE INVENTION
The advantage which can be attained with the present invention consists especially in that a short effective channel length can be realized wlth significantly greater certainty than in the case of the known field ~1$383t.
effect transistors with two gate electrodes, whereby, however, the undesired capacitances which occur between the source region and the gate on the one hand and the semiconductor body on the other hand as well as the capacitances between the gate and the drain regions are smaller than in the case of the transistors manufactured in DrMOS tecimology. Another advantage with respect to DIMOS transistors is to be seen in that the limiting effect which is present in the case of these with respect to the maximum drain current is dis-connected to a large extent by means of a sufficiently large bias voltage at the second gate, so that the short effective channel length can be fully utiliæed with respect to the attainable steepness. Further, the transistor according to the invention can be produced according to methods which are compatible with the double silicon gate technology, so that the simultaneous manufacturing of transistors according to the invention with other components prepared in the technology named is possible without difficulties. A second embodiment form of the invention is the case where the blocking layer capacitances of the transistor are further decreased. Still another embodi-ment is directed toward further designs of the invention which guarantee an especially high steepness of the transistor. Another embodiment of the transistor according to the present invention is one which possesses an especially high breakthrough voltage. Methods of forming the present inven-tion are herein disclosed, which are particularly advantageous for the manu-facture of field effect transistors according to the invention.
Thus, in accordance with a broad aspect of the invention there is provided a field effect transistor with a short channel length comprising a semiconductor body having a base doping of one conductivity type, said body having source and drain regions of the opposite conductivity type which lie at the interface of said semiconductor body, source and drain electrodes 1~53~B3~
respectively connected to said source and drain regions, first and second gates which each cover a part of said semiconductor body region which lies between said source and said drain regions and which gates are separated from said body by means of a first electrical insulating layer, said first gate being located at the source side and being connected with a control voltage, said second gate ~eing located on the drain side and being connected to a terminal of a bias voltage source, characterized by said first gate having a dimension in the source-drain direction which corresponds to the effective channel length of said field effect transistor, said second gate consisting of an electrically conducting coating which extends from said drain to said first gate and is partially above said first gate and is separated by means of a second electrically insulating layer from said first gate and that the part of said semiconductor region lying between said source and said drain which is not covered by said first gate being provided with a zone which is next to said interface, which zone displays a doping which is opposite to said base doping of said body, and said zone extending from said drain to the edge of said first gate nearest said drain and said first gate not extending over said zone, and said second gate not connected to said source region.
In accordance with another broad aspect of the invention there is provided a field effect transistor of the type having a short channel length, comprising a semiconductor body of one conductivity type having highly doped source and drain regions in one interface of said substrate of the opposite conductivity type, a zone region in said interface of the same conductivity type as said drain and source regions but less doped than said source and drain regions and which lies adjacent to said drain region and which extends from said drain region to a point short of said source region, thereby to provide a short channel between said source region and said zone region, a -3a-first non-electrical conducting coating of substantially uniform thickness on said interface, a first gate formed by a layer of electrical conducting material on said first non-electrical conducting material above a region of said body which provides a short channel, a second insulating layer covering said first gate electrode, a second gate electrode formed of electrically conducting material on said first non-conductive coating above said zone region which extends from adjacent said drain region to said short channel region, terminal means for connecting said first gate to a control voltage, terminal means for connecting a biasing potential to said second gate, terminal means for connecting said source region to a set reference potential, means for connecting said drain to a potential source, said second gate not connected to said source region.
In accordance with another broad aspect of the invention there is provided a method for the production of a field effect transistor character-ized in that a semiconductor body which is provided with a base doping is covered on an interface with a first electrically insulating layer, that upon this layer a first gate which defines an effective channel length is placed, that a zone region is formed in said interface by means of a doping process, said zone region being of the same conductivity type as source and drain regions of said transistor but less doped than said source and drain regions and extending from said drain region to a point short of said source region whereby the first gate forms a part of a first doping mask, that after the covering of said first gate by means of a second electrically insulating layer, forming a second gate on said first and second electrically insulating layer such that it partially overlaps the first gate, by means of a further doping process, said source and said drain regions are produced, whereby parts of said first and said second gate serve as parts of a second doping -3b-~S~33;1 mask, said source region, said drain reg:ion, and first and second gates are provided with electric leads.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawing, a longitudinal section through a fie].d effect transistor according to the present invention is depicted.
DESCRIPTION OF PREFERRED EMBODIMENTS
A semiconductor body 1 is provided which consists, for example, -3c-of p-doped silicon. At an interface of the same, which is designated as la, are located an n -doped source region 2 and an n -doped drain region 3. The semiconductor region lying between these regions is partially covered by a first gate 4 and a second gate 5, which gates are separated, by means of a thin electrically insulating layer 6~ from the interface la. Between the gate 4 and the gate 5, a second electrically insulating layer 7 is located.
In the illustrated embodiment being observed~ the insulating layers 6 and 7 preferably consist of SiO2. The regions 2 and 3 as well as the gate 4 and the gate 5 are provided with electric leads 8, 9, 10 and 11.
Under the gate 5 on the interface la, an n-doped zone 12 is provided which is directLy next to the region 3. The manufacture of this zone proceeds in a practical manner by means of a doping step which is undertaken after the placing of the gate 4 and in which the gate 4 serves as a doping mask. In this manner, the gate 4 with its length which is measured in source-drain direction determines the effective channel length L of the transistor, which reaches from the source region 2 to the next-lying border of the zone 12 with great precision. Only after the production of the zone 12 is then the gate 5 formed out of an electrically conducting coating which is applied upon the insulating layers 6 and 7. Thereby, a part of this coating overlaps the gate 4.
In a first case of operation, the lead 8 is placed at a set reference potential, for example, ground potential, the lead 9 at a positive voltage VD
and the lead 11 at a positive bias voltage V, while a gate voltage Ug, which controls the conductivity of the short partial channel which is designated as L, is supplied to the lead 10. Thereby, the gate voltage Ug controls the charge carrier transport between the regions 2 and 3. In another case of operation, the lead 9 lies at a supply voltage VDD and the lead 8 lies at a voltage Us, ~lS~3~
whereas a bias voltage V is supplied to the lead 11 and a gate voltage Ug which controls the conductivity of the partial channel is supplied to the lead 10 .
For the more precise explanation of the invention, in the follow-ing, several doping examples are cited. Thereby, first, a p-doped semi-conductor body is begun which displays a base doping, whereby an impurity concentration of approximately 1015 to 1016 cm 3 is present. The regions
2 and 3 display an n -doping with an impurity concentration of approximately 1017 cm 3, the zone 12 displays an n-doping with an impurtiy concentration of approximately 7.5 1014 to 5 1015cm 3. In one design of gate 4 with a length corresponding to the dimension L of approximately l,u to 2,um, a steepness gm of the transistor results which is larger than 10 A/V.
If one constructs the transistor upon a semiconductor body 1, which displays a p base doping with an impurity concentration of approximately 1-1014cm 3 to 1015cm 3 and only on its interface la does it possess a stronger p-doping 13 of approximately 5-1015cm 3 to 1.5 1016cm 3, and then the latter operates only in the partial channel of the length L which is covered by the gate 4. Thereby, the blocking layer capacitances of the regions 2 and 3 decrease with respect to the semiconductor body 1 with simultaneous decreas-ing of the substrate control effect, whereby the value of the steepness gwhich was mentioned above is also attained.
If in the case of the transistor described above and depicted in the drawing, the thickness of the insulating layer 6 under the gate 4 decreases, then the steepness gm rises. With the supplying of a bias voltage V with an adjustable size, one further succeeds in raising the steepness gm with increasing size of the bias voltage V.
In order to provide the transistor according to the invention ~S3~33~
with a high breakthrough voltage, it is practical to raise the n-doping of zone 12 to such an extent that it displays an impurity concentration of 10 to lol8Cm~3 In a deviation from the embodiment forms described previously, the transistor according to the invention can also be constructed upon an n-doped semiconductor body 1. ~lereby, then, the conductivity types of the ivdividual semiconductor regions reverse in each case, whereby also operating voltages of the opposing polarity are to be provided. The first gate 4 and the second gate 5 consist, in a practical manner, of strongly doped polycrystalline silicon, however, they can also be embodied as metal coatings.
In the case of the manufacture of a field effect transistor accord-ing to the present invention, in a practical manner, one begins with a semi-conductor body 1 which is provided with a p-doping, which on its interface la displays a higher p-doping than in its remaining parts. This semiconductor body is provided with an electrically insulating layer 6 which covers the interface la, for example, a gate oxide layer, which is surrounded in a lateral direction by a field oxide layer which borders the transistor region.
Under the latter, in general, another field implantation is located.
Proceeding from this, first a gate 4 which defines the effective channel length L is formed on the layer 6. Then, the zone 12 is produced by means of a doping step, for example, by an ion implantation, whereby the gate represents a first doping mask. After the application of an insulating layer 7 which covers the gate 4, an electrically conducting coating is applied upon the layers 6 and 7, from which the gate 5 is formed by means of photo-lithographic steps. A further doping step follows for the formation of the source and drain regions 2 and 3, whereby both the gate 4 as well as the gate 5 together with the field oxide layer represent parts of a second doping mask.
~s~q~
After this, the regions 2 and 3 as well as the gate 4 and the gate 5 are provided with the electri.c leads 8 through 11.
If a semiconductor body 1 is begun with which is doped homogene-ously~ and speci.fically with a degree of doping which corresponds approxi-mately to the p-doping on the interface la which was named above~ then the blocking layer capacitances rise between the regions 2 and 3 and the semi-conductor body 1.
It will be apparent to those skilled in the art that various modifications and variations may be effected without departing from the spirit and scope of the novel concepts of the present invention.
If one constructs the transistor upon a semiconductor body 1, which displays a p base doping with an impurity concentration of approximately 1-1014cm 3 to 1015cm 3 and only on its interface la does it possess a stronger p-doping 13 of approximately 5-1015cm 3 to 1.5 1016cm 3, and then the latter operates only in the partial channel of the length L which is covered by the gate 4. Thereby, the blocking layer capacitances of the regions 2 and 3 decrease with respect to the semiconductor body 1 with simultaneous decreas-ing of the substrate control effect, whereby the value of the steepness gwhich was mentioned above is also attained.
If in the case of the transistor described above and depicted in the drawing, the thickness of the insulating layer 6 under the gate 4 decreases, then the steepness gm rises. With the supplying of a bias voltage V with an adjustable size, one further succeeds in raising the steepness gm with increasing size of the bias voltage V.
In order to provide the transistor according to the invention ~S3~33~
with a high breakthrough voltage, it is practical to raise the n-doping of zone 12 to such an extent that it displays an impurity concentration of 10 to lol8Cm~3 In a deviation from the embodiment forms described previously, the transistor according to the invention can also be constructed upon an n-doped semiconductor body 1. ~lereby, then, the conductivity types of the ivdividual semiconductor regions reverse in each case, whereby also operating voltages of the opposing polarity are to be provided. The first gate 4 and the second gate 5 consist, in a practical manner, of strongly doped polycrystalline silicon, however, they can also be embodied as metal coatings.
In the case of the manufacture of a field effect transistor accord-ing to the present invention, in a practical manner, one begins with a semi-conductor body 1 which is provided with a p-doping, which on its interface la displays a higher p-doping than in its remaining parts. This semiconductor body is provided with an electrically insulating layer 6 which covers the interface la, for example, a gate oxide layer, which is surrounded in a lateral direction by a field oxide layer which borders the transistor region.
Under the latter, in general, another field implantation is located.
Proceeding from this, first a gate 4 which defines the effective channel length L is formed on the layer 6. Then, the zone 12 is produced by means of a doping step, for example, by an ion implantation, whereby the gate represents a first doping mask. After the application of an insulating layer 7 which covers the gate 4, an electrically conducting coating is applied upon the layers 6 and 7, from which the gate 5 is formed by means of photo-lithographic steps. A further doping step follows for the formation of the source and drain regions 2 and 3, whereby both the gate 4 as well as the gate 5 together with the field oxide layer represent parts of a second doping mask.
~s~q~
After this, the regions 2 and 3 as well as the gate 4 and the gate 5 are provided with the electri.c leads 8 through 11.
If a semiconductor body 1 is begun with which is doped homogene-ously~ and speci.fically with a degree of doping which corresponds approxi-mately to the p-doping on the interface la which was named above~ then the blocking layer capacitances rise between the regions 2 and 3 and the semi-conductor body 1.
It will be apparent to those skilled in the art that various modifications and variations may be effected without departing from the spirit and scope of the novel concepts of the present invention.
Claims (9)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Field effect transistor with a short channel length comprising a semiconductor body having a base doping of one conductivity type, said body having source and drain regions of the opposite conductivity type which lie at the interface of said semiconductor body, source and drain electrodes respectively connected to said source and drain regions, first and second gates which each cover a part of said semiconductor body region which lies between said source and said drain regions and which gates are separated from said body by means of a first electrical insulating layer, said first gate being located at the source side and being connected with a control voltage, said second gate being located on the drain side and being connected to a terminal of a bias voltage source, characterized by said first gate having a dimension in the source-drain direction which corresponds to the effective channel length of said field effect transistor, said second gate consisting of an electrically conducting coating which extends from said drain to said first gate and is partially above said first gate and is separated by means of a second electrically insulating layer from said first gate and that the part of said semiconductor region lying between said source and said drain which is not covered by said first gate being provided with a zone which is next to said interface, which zone displays a doping which is opposite to said base doping of said body, and said zone extending from said drain to the edge of said first gate nearest said drain and said first gate not extending over said zone, and said second gate not connected to said source region.
2. Field effect transistor of the type having a short channel length, comprising a semiconductor body of one conductivity type having highly doped source and drain regions in one interface of said substrate of the opposite conductivity type, a zone region in said interface of the same conductivity type as said drain and source regions but less doped than said source and drain regions and which lies adjacent to said drain region and which extends from said drain region to a point short of said source region, thereby to provide a short channel between said source region and said zone region, a first non-electrical conducting coating of substantially uniform thickness on said interface, a first gate formed by a layer of electrical conducting material on said first non-electrical conducting material above a region of said body which provides a short channel, a second insulating layer covering said first gate electrode, a second gate electrode formed of electrically conducting material on said first non-conductive coating above said zone region which extends from adjacent said drain region to said short channel region, terminal means for connecting said first gate to a control voltage, terminal means for connecting a biasing potential to said second gate,terminal means for connecting said source region to a set reference potential, means for connecting said drain to a potential source, said second gate not con-nected to said source region.
3. Field effect transistor according to claim 2, characterized in that the degree of doping of the part of the semiconductor body which is covered by said first gate at said interface is higher than the degree of doping of said zone region.
4. Field effect transistor according to claim 2 in which said first electrically insulating layer under said first gate has a smaller thickness than that under the second gate.
5. Field effect transistor according to claim 2, in which said bias voltage source which is connected with the second gate is adjustable with respect to the size of said bias voltage.
6. Field effect transistor according to claim 3, in which the impur-ity concentration of said part of said semiconductor body which is covered by said first gate at said interface lies approximately by two orders of magnitude over the value which corresponds to said base doping and that the impurity concentration of said zone lies above the value which corresponds to said base doping, whereby the concentration difference amounts approxi-mately up to one order to magnitude.
7. Field effect transistor according to claim 6, in which said zone below said second gate displays an impurity concentration which lies over the value which corresponds to the base doping, whereby the concentration difference amounts to up to four orders of magnitude.
8. A method for the production of a field effect transistor character-ized in that a semiconductor body which is provided with a base doping is covered on an interface with a first electrically insulating layer, that upon this layer a first gate which defines an effective channel length is placed, that a zone region is formed in said interface by means of a doping process, said zone region being of the same conductivity type as source and drain regions of said transistor but less doped than said source and drain regions and extending from said drain region to a point short of said source region whereby the first gate forms a part of a first doping mask, that after the covering of said first gate by means of a second electrically insulating layer, forming a second gate on said first and second electrically insulating layer such that it partially overlaps the first gate, by means of a further doping process, said source and said drain regions are produced, whereby parts of said first and said second gate serve as parts of a second doping mask, said source region, said drain region, and first and second gates are pro-vided with electric leads.
9. A method according to claim 8, characterized in that said semi-conductor body is doped on said interface which is covered with said first insulating layer with a higher degree of doping than in its remaining parts.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2921600.0 | 1979-05-28 | ||
| DE19792921600 DE2921600A1 (en) | 1979-05-28 | 1979-05-28 | FIELD EFFECT TRANSISTOR WITH SHORT CHANNEL LENGTH |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1153831A true CA1153831A (en) | 1983-09-13 |
Family
ID=6071852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000352698A Expired CA1153831A (en) | 1979-05-28 | 1980-05-26 | Field effect transistor with a short channel lenght |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0019758B1 (en) |
| JP (1) | JPS55157268A (en) |
| CA (1) | CA1153831A (en) |
| DE (1) | DE2921600A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2499769A1 (en) * | 1981-02-06 | 1982-08-13 | Efcis | IGFET for sampling gate or high gain amplifier - has auxiliary gate tied to static voltage with overlap on gate and source and drain ion implanted using gate metallisation as mask |
| NL8204855A (en) * | 1982-12-16 | 1984-07-16 | Philips Nv | FIELD-EFFECT TRANSISTOR WITH INSULATED STEERING ELECTRODES AND METHOD OF MANUFACTURING THESE. |
| JPH04122071A (en) * | 1990-09-12 | 1992-04-22 | Semiconductor Res Found | Insulated gate transistor |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1441133A (en) * | 1964-07-31 | 1966-06-03 | Rca Corp | Field effect transistor |
| US4058822A (en) * | 1975-05-30 | 1977-11-15 | Sharp Kabushiki Kaisha | High voltage, low on-resistance diffusion-self-alignment metal oxide semiconductor device and manufacture thereof |
| US4060808A (en) * | 1976-06-30 | 1977-11-29 | Rca Corporation | Antenna system with automatic depolarization correction |
| JPS5368581A (en) * | 1976-12-01 | 1978-06-19 | Hitachi Ltd | Semiconductor device |
| JPS53136489A (en) * | 1977-05-04 | 1978-11-29 | Hitachi Ltd | Mos semiconductor element of high dielectric strenght |
| DE2729656A1 (en) * | 1977-06-30 | 1979-01-11 | Siemens Ag | FIELD EFFECT TRANSISTOR WITH EXTREMELY SHORT CHANNEL LENGTH |
| DE2729657A1 (en) * | 1977-06-30 | 1979-01-11 | Siemens Ag | FIELD EFFECT TRANSISTOR WITH EXTREMELY SHORT CHANNEL LENGTH |
-
1979
- 1979-05-28 DE DE19792921600 patent/DE2921600A1/en not_active Ceased
-
1980
- 1980-05-06 EP EP80102474A patent/EP0019758B1/en not_active Expired
- 1980-05-26 CA CA000352698A patent/CA1153831A/en not_active Expired
- 1980-05-27 JP JP7071680A patent/JPS55157268A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0019758B1 (en) | 1983-10-05 |
| JPS55157268A (en) | 1980-12-06 |
| EP0019758A1 (en) | 1980-12-10 |
| DE2921600A1 (en) | 1980-12-04 |
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