CA1128669A - Method for producing and electrical thin layer circuit - Google Patents
Method for producing and electrical thin layer circuitInfo
- Publication number
- CA1128669A CA1128669A CA321,989A CA321989A CA1128669A CA 1128669 A CA1128669 A CA 1128669A CA 321989 A CA321989 A CA 321989A CA 1128669 A CA1128669 A CA 1128669A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- tantalum
- etching
- capacitor
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Abstract
ABSTRACT OF THE DISCLOSURE
A method is disclosed for producing an electric thin layer circuit comprising at least one capacitor and a conductor path and/or a resistor. The number of masks required for the production of such a thin layer circuit is reduced. First and second layers of tantalum-aluminum alloy where the second layer has a tantalum share lower than the first, are applied on an insulating base. In a first masking and etching technique, areas of the first and second layers are etched off outside the cir-cuit elements. At least the second layer is anodically oxidized and the anodically oxidized surface is covered with a silicon dioxide layer so as to form a two layer dielectric for the capa-citor. In a second masking and etching technique, not-required areas of the silicon dioxide layer external to the capacitor are removed. By utilizing the silicon dioxide layer remaining as an etching mask, the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor are removed. In a third etching and masking technique, a conductive surface layer is applied over the sili-con dioxide layer at the capacitor element to form a two-layer dielectric capacitor and over the first tantalum-aluminum layer to form the conductor path.
A method is disclosed for producing an electric thin layer circuit comprising at least one capacitor and a conductor path and/or a resistor. The number of masks required for the production of such a thin layer circuit is reduced. First and second layers of tantalum-aluminum alloy where the second layer has a tantalum share lower than the first, are applied on an insulating base. In a first masking and etching technique, areas of the first and second layers are etched off outside the cir-cuit elements. At least the second layer is anodically oxidized and the anodically oxidized surface is covered with a silicon dioxide layer so as to form a two layer dielectric for the capa-citor. In a second masking and etching technique, not-required areas of the silicon dioxide layer external to the capacitor are removed. By utilizing the silicon dioxide layer remaining as an etching mask, the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor are removed. In a third etching and masking technique, a conductive surface layer is applied over the sili-con dioxide layer at the capacitor element to form a two-layer dielectric capacitor and over the first tantalum-aluminum layer to form the conductor path.
Description
36~
BACKGROUND OF THE IN~IENTION
The invention relates to a method for produciny an electrical thin layer circuit comprising at least one capacitor and one conductor path and/or a resistor, in which a layer of a tantalum-aluminum alloy with a tantalum proportion of between 30 and 70 atomic % is first applied onto an insulating substrate in order to form these circuit elements, and thereupon an additional layer of a tantalum-aluminum alloy with a tantalum share having a magnitude of between 2 and ~ atomic % is applied. ~n interrup-tion is inserted into the two tantalum-aluminum layers with the aid of a first masking and etching technique at the location of a capacitor to be formed whereupon the tantalum-aluminum layers are anodically oxidized in order to produce a two-layer capacitor dielectric. A silicon-dioxide layer is applied onto the result-ing tantalum-aluminum oxide layer, and finally an electrically properly con~ucting surface layer is produced on the capacitor dielectric. This can be done in the area of existing conductor paths with the aid of an additional masking and etching technique.
Up to now the production of integrated RC thin layer circuits in tantalum technique was only possible with the high technological expense of photolithographic processes. Depending upon the specific technological requirements, up to 12 photo-lithographic processes were required. The essential reason therefore is that the ~ -tantalum provided in the tantalum technique as a base electrode for capacitors cannot selectively be etched from the tantalum-oxynitride developed for resistors !36~
on the basis oE its high chemical stability. Therefore, locally delimited etching barriers are required, which necessarily increase the number of photolithographic processes required.
Utilizing the tantalum-aluminum double-layer technique known, for example, from United States Letters Patent 3,949,275, this problem does not exist since the aluminum-rich tantalum-aluminum layer provided as a base electrode for capacitors can readily be selectively etched from the tantalum-aluminum layer provided for resistors.
An additional improvement of the aforementioned tantalum-aluminum double-layer technique was obtained by the introduction of a two-layer capacitor dielectric known from the German OS 2,506,065 of Munz, et al~ laid open September 2, 1976.
This two-layer capacitor dielectric consists of a tantalum- -aluminum oxide-layer produced by an anodic oxidation of the aluminum-rich tantalum aluminum layer and a silicon-dioxide layer advantageously produced by cathode sputteriny. For the RC thin layer circuits produced in accordance with this technology, the absolute values of the temperature coefficients of the resistors can be adjusted to the absolute ~alues of the temperature coefficients of the capacitance. This adjustment results via the relationship.
d 2 d ~l l 2 , whereby . .
~1 ~2 dl d2 . ._ ~Z86169 ~ = temperature coefficient T~C of the two-layer dielectric, C~l = temperature coefficient TKC of the tantalum-aluminum oxide layer, C~2 = temperature coefficient TKC of the silicon dioxide layer, 1 = dielectric constant of the tantalum-aluminum oxide layer, ~2 = dielectric constant of the silicon dioxide layer, dl = thickness of the tantalum-aluminum oxide layer, and d2 = thickness of the silicon dioxi~e layer.
With the aid of this relationship, a suitable thickness d2 of the silicon dioxide layer can be adjusted relative to each arbitrary thickness dl of the tantalum-aluminum oxide layer, so that the absolute value of the temperature coefficients of the capacitance corresponds with the absolute value of the tem-perature coefficient of a resistor.
The production of the thin layer circuits having a two-layer capacitor dielectric results in accordance with a method of the initially mentioned type, whereby the formation of the tantalum-aluminum oxide layer is applied with a local delimita-tion utilizing a dielectric puncture-resistant photomask. With a continued usage of this photomask and also using the lift-off technique, the desired two-layer dielectric consisting of tan- -talum-aluminum oxide and silicon oxide can be produced with the saving of an additional photomask. Thus, for the production of these thin layer circuits, four masks are required in all, where-by respectively a mask is required for the formation of the interruption, for the formation of resistors, and for the structuring of the surface layer in addition to the aforementioned mask. ~
61~;9 SUMMAR~ OF T~IE INVENTION
The present invention has the underlying objective -proceeding from the technique according to the German OS
BACKGROUND OF THE IN~IENTION
The invention relates to a method for produciny an electrical thin layer circuit comprising at least one capacitor and one conductor path and/or a resistor, in which a layer of a tantalum-aluminum alloy with a tantalum proportion of between 30 and 70 atomic % is first applied onto an insulating substrate in order to form these circuit elements, and thereupon an additional layer of a tantalum-aluminum alloy with a tantalum share having a magnitude of between 2 and ~ atomic % is applied. ~n interrup-tion is inserted into the two tantalum-aluminum layers with the aid of a first masking and etching technique at the location of a capacitor to be formed whereupon the tantalum-aluminum layers are anodically oxidized in order to produce a two-layer capacitor dielectric. A silicon-dioxide layer is applied onto the result-ing tantalum-aluminum oxide layer, and finally an electrically properly con~ucting surface layer is produced on the capacitor dielectric. This can be done in the area of existing conductor paths with the aid of an additional masking and etching technique.
Up to now the production of integrated RC thin layer circuits in tantalum technique was only possible with the high technological expense of photolithographic processes. Depending upon the specific technological requirements, up to 12 photo-lithographic processes were required. The essential reason therefore is that the ~ -tantalum provided in the tantalum technique as a base electrode for capacitors cannot selectively be etched from the tantalum-oxynitride developed for resistors !36~
on the basis oE its high chemical stability. Therefore, locally delimited etching barriers are required, which necessarily increase the number of photolithographic processes required.
Utilizing the tantalum-aluminum double-layer technique known, for example, from United States Letters Patent 3,949,275, this problem does not exist since the aluminum-rich tantalum-aluminum layer provided as a base electrode for capacitors can readily be selectively etched from the tantalum-aluminum layer provided for resistors.
An additional improvement of the aforementioned tantalum-aluminum double-layer technique was obtained by the introduction of a two-layer capacitor dielectric known from the German OS 2,506,065 of Munz, et al~ laid open September 2, 1976.
This two-layer capacitor dielectric consists of a tantalum- -aluminum oxide-layer produced by an anodic oxidation of the aluminum-rich tantalum aluminum layer and a silicon-dioxide layer advantageously produced by cathode sputteriny. For the RC thin layer circuits produced in accordance with this technology, the absolute values of the temperature coefficients of the resistors can be adjusted to the absolute ~alues of the temperature coefficients of the capacitance. This adjustment results via the relationship.
d 2 d ~l l 2 , whereby . .
~1 ~2 dl d2 . ._ ~Z86169 ~ = temperature coefficient T~C of the two-layer dielectric, C~l = temperature coefficient TKC of the tantalum-aluminum oxide layer, C~2 = temperature coefficient TKC of the silicon dioxide layer, 1 = dielectric constant of the tantalum-aluminum oxide layer, ~2 = dielectric constant of the silicon dioxide layer, dl = thickness of the tantalum-aluminum oxide layer, and d2 = thickness of the silicon dioxi~e layer.
With the aid of this relationship, a suitable thickness d2 of the silicon dioxide layer can be adjusted relative to each arbitrary thickness dl of the tantalum-aluminum oxide layer, so that the absolute value of the temperature coefficients of the capacitance corresponds with the absolute value of the tem-perature coefficient of a resistor.
The production of the thin layer circuits having a two-layer capacitor dielectric results in accordance with a method of the initially mentioned type, whereby the formation of the tantalum-aluminum oxide layer is applied with a local delimita-tion utilizing a dielectric puncture-resistant photomask. With a continued usage of this photomask and also using the lift-off technique, the desired two-layer dielectric consisting of tan- -talum-aluminum oxide and silicon oxide can be produced with the saving of an additional photomask. Thus, for the production of these thin layer circuits, four masks are required in all, where-by respectively a mask is required for the formation of the interruption, for the formation of resistors, and for the structuring of the surface layer in addition to the aforementioned mask. ~
61~;9 SUMMAR~ OF T~IE INVENTION
The present invention has the underlying objective -proceeding from the technique according to the German OS
2,506,065 - to indicate a way which facilitates an additional reduction of the masks required for the production of the thin layer cireuits.
This objective with a me~hod of the initially mentioned type is inventively resolved in that with the aid of the first masking and etching teehnique, the areas of the two tantalum-aluminum layers lying outside of the eircuit element areas are etehed off. Then the free-lying surfaces of the tantalum-aluminum layers are anodically oxidized over the total surface and are eoated with the silieon dioxide layer applied over the total surface. The areas of the silicon dioxide layer which are not required are removed with the aid of a second masking and etching technique and the areas of the tantalum-aluminum oxide layer which are not required and of the tantalum aluminum layer havingthe low tantalum proportion are selectively etched off utilizing the remaining silicon dioxide layer as an etching mas]c, and that subsequently the surface layer is applied.
Thus, with the inventive method not only the resistors but also the eapaeitor base electrodes are already struetured before the applieation of the surface layer required for the eapaeitor eountereleetrodes and the eonduetor paths. This faei-litates an anodie o~idation of the total structured tantalum-aluminum double-layer without a mask. Since silieon oxide can ~286~
readily be structured by etching, the silicon dioxide layer can also be applied over the total surface, i.e., without using the lift-off technique. The structured silicon dio~ide layer can then be used as an etching mask for the structuring of the tantalum-aluminum oxide layer and for the remaining tantalum-aluminum layer having the low tantalum proportion. Thus, for the production of the thin layer circuit only three mas]~s are required in all. Additionally, the mask required for the struc-turing of the silicon dioxide layer need only have the temperature stability required for the etching, i.e., it can be produced by utilizing the generally preferred positive photolac~uers. A
dielectric temperature strength of the mask as required for the locally delimited anodic oxidation is not required. As an additional advantage of the inventive method, no regard need be observed for the high heating of a mask in the total surface appli-cation of the silicon dioxide layer in contrast to the lift-off technique. Thus, high sputtering outputs a~d low sputtering times can be realizec for the application with the aid of ca-thode sputtering. However, for the mounting of the silicon dioxid~ layer with high sputtering rates, the oxygen loss is exceedingly low during sputtering so that exceedingly low loss factors occur with capacitors thus produced.
For the mask production in the second masking and etch-ing technique, a positive photolacquer is advantageously used.
The areas of the silicon dioxide layer which are not required are particularly advantageously removed by means of plasma-etching. It is additionally recommended to use a watery solu-tion of phosphoric acid and chromium acid for theetching-off ,. ", ~86~;~
of the tantalum-aluminum oxide-layer. The areas of the tantalum-aluminum layer wh.ich are not required having the low tantalum share or proportion are advantageously etched off in a watery, buffered fluorhydracid.
Thus, in accordance with one broad aspect of the -invention, there is provided a method for producing an electric thin layer circuit comprising circuit elements including at least one capacitor and a conductor path comprising the steps of:
a) providing an insulating layer and applying a first layer of a tantalum-aluminum alloy having a tantalum share of between 30 and 70 atomic % on the insulating layer;
b) applying a second layer of a tantalum-aluminum alloy having a tantalum share of between 2 and 20 atomic ~ on the first layer;
c) forming circuit elements by a first masking and etching technique by etching off areas of the fi.rst and second layers outside the circuit elements by at least one etching;
; d) anodically oxidizing an exposed surface of the ~0 first and second layers to form a tantalum-aluminum oxide layer, coating the anodically oxidized surface with a silicon dioxide layer;
e) removing by a second masking and ekching technique not-required axeas of the silicon dioxide layer external to the capacitor;
f) by utilizing the remaining silicon dioxide layer as an etching mask, selectively etching off the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor~ and g) by a third etching and masking technique applying a conductive surface layer over the slllcon dioxide layer at the - capacitor element to form a cwo-layer dielectric capacitor and . .
: - , .
over the first tantalum-aluminum layer to form the conductor path.
In accordance with another broad aspect of the invention, there is provided a method for producing an electric thin layer circuit comprising circuit elements including at least one capacitor and a conductor path, comprising the steps of:
a) providing an insulating base and depositing thereon ;~ a first tantalum-aluminum alloy layer having a tantalum content of 30 to 70 atomic ~ and depositing on the first layer a second tantalum-aluminum alloy layer having a tantalum content between 2 and 20 atomic %;
b) covering the base with a mask in a first photo-technique and etching off areas of the first and second alloy layers external to the capacitor and conductor path to be produced;
c) undertaking an anodic oxidation for transforming the surface area of the second alloy layer into a tantalum-aluminum oxide layer;
d) applying a sillcon dioxide layer onto the base; .
e) in a second phototechnique, mounting a second mask on the silicon dioxide layer so that areas of the silicon dioxide layer can be etched off external to a dielectric region ` of the capacitor, and the tantalum-aluminum oxide layer areas ~; `
external to the dielectric region can be etched off by using the remaining silicon dioxide layer as an etching mask; ~- .
f) applying a conductl~e surface layer over the base and in a third phototechnique, and by use of a third mask, the ~ :
conductive surface layer is structured so as to provide a conductor path and a capacitor counter electrode, In one preferred embodiment of the inventive method ~ the base electrode connection of the capacitor is carried out - 6a -:
9.~Z8~
via a narrow path of the tantalum-aluminum layer having the high tantalum share. It is thereby recommended to fashion the base electrode connection in a fork-shape in order to lay out the effective capacitor surface, and to also design the path in a fork-shapeO A particularly low-ohmic connection to the capacitor base electrode is obtained with this technique. Then, a width in the magnitude of 50 ~m is expediently obtained for the path.
BRIEF DESCRIPTION OF THE DRAWINGS
. .
Figure 1 illustrates a flow diagram of the method steps required in accordance with the inventive method;
Figure 2 shows a longitudinal sec-tion in the capacitor area through a thin layer circuit produced in accordance with the inventive method;
Figure 3 shows a section in accordance with lines III-III of Figure 2; and Figure 4 shows a top view of the thin layer circuit illustrated in Figures 1 and 2, in which the position of the mask necessary for the production is schematically shown.
- 6b -~ - "
~J~2~69 . .
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the subsequent description of the sample embodiment, one proceeds from the flow diagram illustrated in FIG. 1 with reference to the thin layer circuit illustrated in FIGS. 2 and
This objective with a me~hod of the initially mentioned type is inventively resolved in that with the aid of the first masking and etching teehnique, the areas of the two tantalum-aluminum layers lying outside of the eircuit element areas are etehed off. Then the free-lying surfaces of the tantalum-aluminum layers are anodically oxidized over the total surface and are eoated with the silieon dioxide layer applied over the total surface. The areas of the silicon dioxide layer which are not required are removed with the aid of a second masking and etching technique and the areas of the tantalum-aluminum oxide layer which are not required and of the tantalum aluminum layer havingthe low tantalum proportion are selectively etched off utilizing the remaining silicon dioxide layer as an etching mas]c, and that subsequently the surface layer is applied.
Thus, with the inventive method not only the resistors but also the eapaeitor base electrodes are already struetured before the applieation of the surface layer required for the eapaeitor eountereleetrodes and the eonduetor paths. This faei-litates an anodie o~idation of the total structured tantalum-aluminum double-layer without a mask. Since silieon oxide can ~286~
readily be structured by etching, the silicon dioxide layer can also be applied over the total surface, i.e., without using the lift-off technique. The structured silicon dio~ide layer can then be used as an etching mask for the structuring of the tantalum-aluminum oxide layer and for the remaining tantalum-aluminum layer having the low tantalum proportion. Thus, for the production of the thin layer circuit only three mas]~s are required in all. Additionally, the mask required for the struc-turing of the silicon dioxide layer need only have the temperature stability required for the etching, i.e., it can be produced by utilizing the generally preferred positive photolac~uers. A
dielectric temperature strength of the mask as required for the locally delimited anodic oxidation is not required. As an additional advantage of the inventive method, no regard need be observed for the high heating of a mask in the total surface appli-cation of the silicon dioxide layer in contrast to the lift-off technique. Thus, high sputtering outputs a~d low sputtering times can be realizec for the application with the aid of ca-thode sputtering. However, for the mounting of the silicon dioxid~ layer with high sputtering rates, the oxygen loss is exceedingly low during sputtering so that exceedingly low loss factors occur with capacitors thus produced.
For the mask production in the second masking and etch-ing technique, a positive photolacquer is advantageously used.
The areas of the silicon dioxide layer which are not required are particularly advantageously removed by means of plasma-etching. It is additionally recommended to use a watery solu-tion of phosphoric acid and chromium acid for theetching-off ,. ", ~86~;~
of the tantalum-aluminum oxide-layer. The areas of the tantalum-aluminum layer wh.ich are not required having the low tantalum share or proportion are advantageously etched off in a watery, buffered fluorhydracid.
Thus, in accordance with one broad aspect of the -invention, there is provided a method for producing an electric thin layer circuit comprising circuit elements including at least one capacitor and a conductor path comprising the steps of:
a) providing an insulating layer and applying a first layer of a tantalum-aluminum alloy having a tantalum share of between 30 and 70 atomic % on the insulating layer;
b) applying a second layer of a tantalum-aluminum alloy having a tantalum share of between 2 and 20 atomic ~ on the first layer;
c) forming circuit elements by a first masking and etching technique by etching off areas of the fi.rst and second layers outside the circuit elements by at least one etching;
; d) anodically oxidizing an exposed surface of the ~0 first and second layers to form a tantalum-aluminum oxide layer, coating the anodically oxidized surface with a silicon dioxide layer;
e) removing by a second masking and ekching technique not-required axeas of the silicon dioxide layer external to the capacitor;
f) by utilizing the remaining silicon dioxide layer as an etching mask, selectively etching off the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor~ and g) by a third etching and masking technique applying a conductive surface layer over the slllcon dioxide layer at the - capacitor element to form a cwo-layer dielectric capacitor and . .
: - , .
over the first tantalum-aluminum layer to form the conductor path.
In accordance with another broad aspect of the invention, there is provided a method for producing an electric thin layer circuit comprising circuit elements including at least one capacitor and a conductor path, comprising the steps of:
a) providing an insulating base and depositing thereon ;~ a first tantalum-aluminum alloy layer having a tantalum content of 30 to 70 atomic ~ and depositing on the first layer a second tantalum-aluminum alloy layer having a tantalum content between 2 and 20 atomic %;
b) covering the base with a mask in a first photo-technique and etching off areas of the first and second alloy layers external to the capacitor and conductor path to be produced;
c) undertaking an anodic oxidation for transforming the surface area of the second alloy layer into a tantalum-aluminum oxide layer;
d) applying a sillcon dioxide layer onto the base; .
e) in a second phototechnique, mounting a second mask on the silicon dioxide layer so that areas of the silicon dioxide layer can be etched off external to a dielectric region ` of the capacitor, and the tantalum-aluminum oxide layer areas ~; `
external to the dielectric region can be etched off by using the remaining silicon dioxide layer as an etching mask; ~- .
f) applying a conductl~e surface layer over the base and in a third phototechnique, and by use of a third mask, the ~ :
conductive surface layer is structured so as to provide a conductor path and a capacitor counter electrode, In one preferred embodiment of the inventive method ~ the base electrode connection of the capacitor is carried out - 6a -:
9.~Z8~
via a narrow path of the tantalum-aluminum layer having the high tantalum share. It is thereby recommended to fashion the base electrode connection in a fork-shape in order to lay out the effective capacitor surface, and to also design the path in a fork-shapeO A particularly low-ohmic connection to the capacitor base electrode is obtained with this technique. Then, a width in the magnitude of 50 ~m is expediently obtained for the path.
BRIEF DESCRIPTION OF THE DRAWINGS
. .
Figure 1 illustrates a flow diagram of the method steps required in accordance with the inventive method;
Figure 2 shows a longitudinal sec-tion in the capacitor area through a thin layer circuit produced in accordance with the inventive method;
Figure 3 shows a section in accordance with lines III-III of Figure 2; and Figure 4 shows a top view of the thin layer circuit illustrated in Figures 1 and 2, in which the position of the mask necessary for the production is schematically shown.
- 6b -~ - "
~J~2~69 . .
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the subsequent description of the sample embodiment, one proceeds from the flow diagram illustrated in FIG. 1 with reference to the thin layer circuit illustrated in FIGS. 2 and
3 and also the schematic illustration of FIG. 4. In accordance with FIG. 1, an insulating base is provided as an initial base, which, for example, can be produced by means of applying an oxide onto a non-conducting carrier. As assumed in FIGS. 2 and 3, one can also proceed from a completed insulating base 1 which, for example, consists of glass, quartz, sapphire or a fine-grained polished ceramic. A TaAl double layer is applied to the base 1, which consists of a tantalum-aluminum alloy layer 2 having tanta-lum content of 30 through 70, advantageously 60 atomic ~ and a tantalum-aluminum alloy layer 3 having a tantalum content in the magnitude of between 2 and 20, advantageously 7 atomic %. The application of the tantalum-aluminum alloy layers 2 and 3 proceeds in a manner per se known, for example, with the aid of cathode sputtering.
The base thus prepared is now covered with a mask which, for example, can be produced photolithographically with the aid of a positively effecting photolacquerO This mask production is referenced phototechnique I, whereby the position of the mask is indicated by the dashed line FI in the top view of FIG. 4.
The mask covers all of the areas corresponding with the capacitor base electrodes, resistors and conductor paths to be produced, so that the remaining areas of the tantalum-aluminum alloy layers 2 and 3 can be etched-off by one etching step or by two successive etching steps. With two subsequent selective etchin~ steps an - \
~z~
underetching of the tantalum-aluminum alloy layers 2 and 3 is avoided. A watery buffered fluorhydracid, for example, can be used for the structuring of the tantalwn-aluminum alloy layer 3, whereas a water~l hydrofluoric acid - nitric acid solution can be used as etching means for the structuring of the tantalum-alumi-num alloy layer 2.
After removing the mask formed by phototechnique I, a total surface anodic oxidation is undertaken in which the surface area of the tantalum-aluminum alloy layer 3 is transformed into a tantalum-aluminum oxide layer 4. In the interruption following the capacitor area, the tantalum-aluminum oxide~ayer 4 in accord-ance with FIG. ~ also extends over the free frontal side of the tantalum-aluminum alloy layer 2. The production of the tantalum-aluminum oxide layer 4 by anodic oxidation is undertaken, for example, in a watery citric acid solution having a constant current density of 1 mA/cm2 until a formation voltage of approxi-mately 200 volts is formed.
After the anodic oxidation, a total-surace silicon dioxide layer 5 is applied onto the base, advantageously with the aid of cathode sputtering.
Subsequently a second mask is mounted onto the silicon dioxide layer 5, said mask which is advantageously photolitho- ~~
graphically produced with the aid of a positively-acting photo-lacquer. This mask production is referenced photolacquer II, whereby the position of the second mask is indicated by the dotted line F II. The second mask covers the dielectric region of the capacitors to be produced so that the remaining areas of Z~669 the silicon dioxide layer 5 and of the tantalum-aluminum oxide layer 4 can be etched off by two successive selective etching steps. The structuring of the silicon dioxide layer 5 can also be undertaken wet-chemically, but advantageously proceeds via plasma etching. A corresponding structuring of the tantalum-aluminum oxide layer 4 results after wet-chemically removing the second photomask, ~or example, in a watery solution of 5% phos-phoric acid (H3PO~) and 3~ chromium acid (CrO3) at a temperature o~ 85 C. For this etching process the remaining silicon dioxide layer 5 is used as an etching mask.
The residual areas of the tantalum-aluminum alloy layer 3 not required for the capacitor base electrodes are etched off in an additional selective etching process whereby the remaining silicon-dioxide layer 5 is again used as an etching mask. The watery buffered fluorhydracid already mentioned can be used as an etching means. The removal of the second mask can also pro-ceed after this selective etching process as it covers the same areas as the remaining silicon dioxide layer 5.
In the subsequent method step an electrically properly conducting surface layer is mounted over the total surface in order to form the conductor paths and the capacitor counter-electrodes. This mounting is undertaken, for example, by a ~-~
successively resulting vaporization of a nickel-chromium layer 6 and a gold layer 7.
The surface layer is structured during the last method step. A third mask is applied onto ~e gold layer 7, said mask which, for example, can photolithographically be produced with the aid of a positively acting photolacquer. This mask produc-tion is referenced photolacquer III, whereby the position of the ~;
_ g _ ':
.
~Z8~i~i9 :
third mask is indlcated by dash-dotted lines FIII inthe top view o~ FIG. 4. The third mask ~vers the areas of the conductor p~th and of the capacitor counter electrodes so thatthe remaining areas of the gold layer 7 and of the nickel-chromium layer 6 can be etched off. The structuring of the gold layer 7 results, for example~ in a watery potassium-iodide-iodine solution as etching means, whereas the structuring of the nickel-chromium layer 6 can be undertaken in a watery cer-sulfate solution. After these selective etching processes only the third mask need be removed in order to complete the thin layer circuit.
As is obvious from FIGS. 2 and 3, the base electrode connection of the capacitor is designed in a fork-shape in order to obtain a low-ohmic connection, whereby the connection of the corresponding areas of the nickel-chromium layer 6 and of the gold layer 7 proceeds with the area o~ the tantalum-aluminum alloy layer 3 remaining as a capacitor base electrode via a narrow, for example, 50~ m wide path of the tantalum-al~inum alloy layer 2.
No resistors are illustrated in FIGS. 2 and 3 as they receive the ~esign conventional for thin layer technique and are known, for example, from U. S. Patent 3,949,275. As is clear-ly obvious from the aforementioned specification, they are formed ; ;~
from the tantalum-aluminum alloy layer 2 and are already struc-tured ~ the phototechnique I. The previously mentioned path of the tantalum-aluminum alloy layer 2 can, for example, also be considered a resistor arranged in series with the capacitor with a correspondingly wide design.
. . , . . . : .
The inventlve method facilitates the production of ~hin layer circuits with a particularly economical production technique, said circuits which are particularly suited for the low frequency range. In a thin layer circuit designed in accordance with FIGS.
2 and 3, in which the tantalum-aluminum alloy layer 2 consists of 60 atomic % Ta and of 40 atomic ~ Al, the tantalum-aluminum alloy layer 3 consists of 7 atomic ~O Ta and 93 atomic gO Al. The tantalum-aluminum oxide layer 4 is designed with a thickness of 280 nm with a formation voltage of 200 vdts. The silicon dioxide layer 5 exhibits a thickness of 300 nm, the nickel-chromium layer 6 exhibits a thickness of 50 nm, and the gold layer 7 exhi-bits a thickness of 500 nm. In the above structure, the follow-ing technical data, for example, is realized:
Resistors: Surface resistance RF = 100 ~ /~
TKR = - 110 - 20 ppm/C.
Capacitors: Specific capacitance Cspec = 10 nF/cm Loss angle ~g ~lkH
TKC = + 110 - 20 ppm/ C.
TKR and TKC refer to the temperature coefficients of the resistors or capacitors.
Although varlous mlnor modifications may be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent warranted hereon, all `
such embodiments as reasonably and properly come within the scope of our contribution to the art.
'
The base thus prepared is now covered with a mask which, for example, can be produced photolithographically with the aid of a positively effecting photolacquerO This mask production is referenced phototechnique I, whereby the position of the mask is indicated by the dashed line FI in the top view of FIG. 4.
The mask covers all of the areas corresponding with the capacitor base electrodes, resistors and conductor paths to be produced, so that the remaining areas of the tantalum-aluminum alloy layers 2 and 3 can be etched-off by one etching step or by two successive etching steps. With two subsequent selective etchin~ steps an - \
~z~
underetching of the tantalum-aluminum alloy layers 2 and 3 is avoided. A watery buffered fluorhydracid, for example, can be used for the structuring of the tantalwn-aluminum alloy layer 3, whereas a water~l hydrofluoric acid - nitric acid solution can be used as etching means for the structuring of the tantalum-alumi-num alloy layer 2.
After removing the mask formed by phototechnique I, a total surface anodic oxidation is undertaken in which the surface area of the tantalum-aluminum alloy layer 3 is transformed into a tantalum-aluminum oxide layer 4. In the interruption following the capacitor area, the tantalum-aluminum oxide~ayer 4 in accord-ance with FIG. ~ also extends over the free frontal side of the tantalum-aluminum alloy layer 2. The production of the tantalum-aluminum oxide layer 4 by anodic oxidation is undertaken, for example, in a watery citric acid solution having a constant current density of 1 mA/cm2 until a formation voltage of approxi-mately 200 volts is formed.
After the anodic oxidation, a total-surace silicon dioxide layer 5 is applied onto the base, advantageously with the aid of cathode sputtering.
Subsequently a second mask is mounted onto the silicon dioxide layer 5, said mask which is advantageously photolitho- ~~
graphically produced with the aid of a positively-acting photo-lacquer. This mask production is referenced photolacquer II, whereby the position of the second mask is indicated by the dotted line F II. The second mask covers the dielectric region of the capacitors to be produced so that the remaining areas of Z~669 the silicon dioxide layer 5 and of the tantalum-aluminum oxide layer 4 can be etched off by two successive selective etching steps. The structuring of the silicon dioxide layer 5 can also be undertaken wet-chemically, but advantageously proceeds via plasma etching. A corresponding structuring of the tantalum-aluminum oxide layer 4 results after wet-chemically removing the second photomask, ~or example, in a watery solution of 5% phos-phoric acid (H3PO~) and 3~ chromium acid (CrO3) at a temperature o~ 85 C. For this etching process the remaining silicon dioxide layer 5 is used as an etching mask.
The residual areas of the tantalum-aluminum alloy layer 3 not required for the capacitor base electrodes are etched off in an additional selective etching process whereby the remaining silicon-dioxide layer 5 is again used as an etching mask. The watery buffered fluorhydracid already mentioned can be used as an etching means. The removal of the second mask can also pro-ceed after this selective etching process as it covers the same areas as the remaining silicon dioxide layer 5.
In the subsequent method step an electrically properly conducting surface layer is mounted over the total surface in order to form the conductor paths and the capacitor counter-electrodes. This mounting is undertaken, for example, by a ~-~
successively resulting vaporization of a nickel-chromium layer 6 and a gold layer 7.
The surface layer is structured during the last method step. A third mask is applied onto ~e gold layer 7, said mask which, for example, can photolithographically be produced with the aid of a positively acting photolacquer. This mask produc-tion is referenced photolacquer III, whereby the position of the ~;
_ g _ ':
.
~Z8~i~i9 :
third mask is indlcated by dash-dotted lines FIII inthe top view o~ FIG. 4. The third mask ~vers the areas of the conductor p~th and of the capacitor counter electrodes so thatthe remaining areas of the gold layer 7 and of the nickel-chromium layer 6 can be etched off. The structuring of the gold layer 7 results, for example~ in a watery potassium-iodide-iodine solution as etching means, whereas the structuring of the nickel-chromium layer 6 can be undertaken in a watery cer-sulfate solution. After these selective etching processes only the third mask need be removed in order to complete the thin layer circuit.
As is obvious from FIGS. 2 and 3, the base electrode connection of the capacitor is designed in a fork-shape in order to obtain a low-ohmic connection, whereby the connection of the corresponding areas of the nickel-chromium layer 6 and of the gold layer 7 proceeds with the area o~ the tantalum-aluminum alloy layer 3 remaining as a capacitor base electrode via a narrow, for example, 50~ m wide path of the tantalum-al~inum alloy layer 2.
No resistors are illustrated in FIGS. 2 and 3 as they receive the ~esign conventional for thin layer technique and are known, for example, from U. S. Patent 3,949,275. As is clear-ly obvious from the aforementioned specification, they are formed ; ;~
from the tantalum-aluminum alloy layer 2 and are already struc-tured ~ the phototechnique I. The previously mentioned path of the tantalum-aluminum alloy layer 2 can, for example, also be considered a resistor arranged in series with the capacitor with a correspondingly wide design.
. . , . . . : .
The inventlve method facilitates the production of ~hin layer circuits with a particularly economical production technique, said circuits which are particularly suited for the low frequency range. In a thin layer circuit designed in accordance with FIGS.
2 and 3, in which the tantalum-aluminum alloy layer 2 consists of 60 atomic % Ta and of 40 atomic ~ Al, the tantalum-aluminum alloy layer 3 consists of 7 atomic ~O Ta and 93 atomic gO Al. The tantalum-aluminum oxide layer 4 is designed with a thickness of 280 nm with a formation voltage of 200 vdts. The silicon dioxide layer 5 exhibits a thickness of 300 nm, the nickel-chromium layer 6 exhibits a thickness of 50 nm, and the gold layer 7 exhi-bits a thickness of 500 nm. In the above structure, the follow-ing technical data, for example, is realized:
Resistors: Surface resistance RF = 100 ~ /~
TKR = - 110 - 20 ppm/C.
Capacitors: Specific capacitance Cspec = 10 nF/cm Loss angle ~g ~lkH
TKC = + 110 - 20 ppm/ C.
TKR and TKC refer to the temperature coefficients of the resistors or capacitors.
Although varlous mlnor modifications may be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent warranted hereon, all `
such embodiments as reasonably and properly come within the scope of our contribution to the art.
'
Claims (10)
1. A method for producing an electric thin layer cir-cuit comprising circuit elements including at least one capacitor and a conductor path comprising the steps of:
a) providing an insulating layer and applying a first layer of a tantalum-aluminum alloy having a tantalum share of between 30 and 70 atomic % on the insulating layer;
b) applying a second layer of a tantalum-aluminum alloy having a tantalum share of between 2 and 20 atomic % on the first layer;
c) forming circuit elements by a first masking and etching technique by etching off areas of the first and second layers outside the circuit elements by at least one etching;
d) anodically oxidizing an exposed surface of the first and second layers to form a tantalum-aluminum oxide layer,coating the anodically oxidized surface with a silicon dioxide layer;
e) removing by a second masking and etching tech-nique not-required areas of the silicon dioxide layer external to the capacitor;
f) by utilizing the remaining silicon dioxide layer as an etching mask, selectively etching off the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor; and g) by a third etching and masking technique applying a conductive surface layer over the silicon dioxide layer at the capacitor element to form a two-layer dielectric capacitor and over the first tantalum-aluminum layer to form the conductor path.
a) providing an insulating layer and applying a first layer of a tantalum-aluminum alloy having a tantalum share of between 30 and 70 atomic % on the insulating layer;
b) applying a second layer of a tantalum-aluminum alloy having a tantalum share of between 2 and 20 atomic % on the first layer;
c) forming circuit elements by a first masking and etching technique by etching off areas of the first and second layers outside the circuit elements by at least one etching;
d) anodically oxidizing an exposed surface of the first and second layers to form a tantalum-aluminum oxide layer,coating the anodically oxidized surface with a silicon dioxide layer;
e) removing by a second masking and etching tech-nique not-required areas of the silicon dioxide layer external to the capacitor;
f) by utilizing the remaining silicon dioxide layer as an etching mask, selectively etching off the not-required areas of the tantalum-aluminum oxide layer and the second tantalum-aluminum layer external to the capacitor; and g) by a third etching and masking technique applying a conductive surface layer over the silicon dioxide layer at the capacitor element to form a two-layer dielectric capacitor and over the first tantalum-aluminum layer to form the conductor path.
2. A method according to claim 1 comprising the step of using a positive photolacquer for mask production in the se-cond masking and etching technique.
3. A method according to claim 1 comprising the step of removing the not-required areas of the silicon dioxide layer by plasma-etching.
4. A method according to claim 1 comprising the step of etching off the not-required areas of the tantalum-aluminum oxide layer in a watery solution of phosphoric acid and chromic acid.
5. A method according to claim 1 comprising the step of etching off the not-required areas of the second tantalum-alumi-num layer having the low tantalum share in a watery buffered fluorhydracid.
6. A method according to claim 1 comprising the step of providing a base electrode connection of the capacitor with a narrow path of the first tantalum-aluminum layer having the high tantalum share.
7. A method according to claim 6 comprising the step of laying out the base electrode connection as a narrow path about an effective capacitor surface in a fork-shape.
8. A method according to claim 7 comprising the step of selecting a width in the magnitude of 50? m for the narrow path.
9. The method of claim 1 wherein the conductor path is provided as a resistor.
10. A method for producing an electric thin layer circuit comprising circuit elements including at least one capa-citor and a conductor path, comprising the steps of:
a) providing an insulating base and depositing thereon a first tantalum-aluminum alloy layer having a tantalum content of 30 to 70 atomic % and depositing on the first layer a second tantalum-aluminum alloy layer having a tantalum content between 2 and 20 atomic %;
b) covering the base with a mask in a first photo-technique and etching off areas of the first and second alloy layers external to the capacitor and conductor path to be produced;
c) undertaking an anodic oxidation for transform-ing the surface area of the second alloy layer into a tantalum-aluminum oxide layer;
d) applying a silicon dioxide layer onto the base;
e) in a second phototechnique, mounting a second mask on the silicon dioxide layer so that areas of the silicon dioxide layer can be etched off external to a dielectric region of the capacitor, and the tantalum-aluminum oxide layer areas external to the dielectric region can be etched off by using the remaining silicon dioxide layer as an etching mask;
f) applying a conductive surface layer over the base and in a third phototechnique, and by use of a third mask, the conductive surface layer is structured so as to provide a conductor path and a capacitor counter electrode.
a) providing an insulating base and depositing thereon a first tantalum-aluminum alloy layer having a tantalum content of 30 to 70 atomic % and depositing on the first layer a second tantalum-aluminum alloy layer having a tantalum content between 2 and 20 atomic %;
b) covering the base with a mask in a first photo-technique and etching off areas of the first and second alloy layers external to the capacitor and conductor path to be produced;
c) undertaking an anodic oxidation for transform-ing the surface area of the second alloy layer into a tantalum-aluminum oxide layer;
d) applying a silicon dioxide layer onto the base;
e) in a second phototechnique, mounting a second mask on the silicon dioxide layer so that areas of the silicon dioxide layer can be etched off external to a dielectric region of the capacitor, and the tantalum-aluminum oxide layer areas external to the dielectric region can be etched off by using the remaining silicon dioxide layer as an etching mask;
f) applying a conductive surface layer over the base and in a third phototechnique, and by use of a third mask, the conductive surface layer is structured so as to provide a conductor path and a capacitor counter electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA321,989A CA1128669A (en) | 1979-02-21 | 1979-02-21 | Method for producing and electrical thin layer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA321,989A CA1128669A (en) | 1979-02-21 | 1979-02-21 | Method for producing and electrical thin layer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1128669A true CA1128669A (en) | 1982-07-27 |
Family
ID=4113593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA321,989A Expired CA1128669A (en) | 1979-02-21 | 1979-02-21 | Method for producing and electrical thin layer circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1128669A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7080896B2 (en) | 2004-01-20 | 2006-07-25 | Lexmark International, Inc. | Micro-fluid ejection device having high resistance heater film |
-
1979
- 1979-02-21 CA CA321,989A patent/CA1128669A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7080896B2 (en) | 2004-01-20 | 2006-07-25 | Lexmark International, Inc. | Micro-fluid ejection device having high resistance heater film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4410867A (en) | Alpha tantalum thin film circuit device | |
| US4337115A (en) | Method of forming electrodes on the surface of a semiconductor substrate | |
| US3988824A (en) | Method for manufacturing thin film circuits | |
| US4433319A (en) | Moisture sensor and method of manufacturing the same | |
| US4251326A (en) | Fabricating an RC network utilizing alpha tantalum | |
| US5240868A (en) | Method of fabrication metal-electrode in semiconductor device | |
| JPS58200566A (en) | Method of producing semiconductor device | |
| US4450048A (en) | Method of manufacturing capacitors integrated in microelectronic structure | |
| JPH0250625B2 (en) | ||
| US4482882A (en) | Moisture sensor with valve metal composition electrodes | |
| IL45045A (en) | Thin-film electrical circuit | |
| NL8002199A (en) | METHOD FOR MAKING INTEGRATED CIRCUITS USING A MULTI-LAYER MASK AND DEVICES OBTAINED BY THIS METHOD | |
| US4344223A (en) | Monolithic hybrid integrated circuits | |
| US4283485A (en) | Conductor crossovers for integrated RC-circuits | |
| US4200502A (en) | Method for producing an electrical thin layer circuit | |
| CA1128669A (en) | Method for producing and electrical thin layer circuit | |
| US4496435A (en) | Method of manufacturing thin film circuits | |
| US3544287A (en) | Heat treatment of multilayered thin film structures employing oxide parting layers | |
| US3997411A (en) | Method for the production of a thin film electric circuit | |
| US3778689A (en) | Thin film capacitors and method for manufacture | |
| US3726733A (en) | Method of manufacturing thin-film integrated circuits | |
| US4385966A (en) | Fabrication of thin film resistors and capacitors | |
| JPS5961160A (en) | Manufacture of thin-film hybrid integrated circuit | |
| JPS5821310A (en) | Manufacture of planar type magnetic bubble element | |
| JPH0114701B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |