CA1119666A - Voltage reduction circuits - Google Patents

Abstract

ABSTRACT
A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the recti-fied AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transform-ers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner. An over-current sensing and control device prevents damage to components. A power on/fail circuit signals the load as to the status of the regulated load volt-age and guarantees power for orderly shutdown after an input power outage.

Description

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This invention relates to the convcrsion of elec~rical power from high to low voltage levels, in order to supply a digital computing system.
Most electronic devices operate from an AC powcr source of either 110 volts and 60 hertz, or 220 volts and 50 hertz. It is often the case that these electronic de~ices must in turn produce a constant low-level DC power.
This is most often accomplished by an internal power supply which first con-verts the AC power to a high-level voltage which is subsequently converted to a lower level voltage.
The conversion rrom high-level OC voltage to low~-level DC voltage is often accomplished by applying the higher level DC voltage to the primary winding of a step-down transformer. The application of high-level DC voltage is moreover usually accomplished at a high frequency so as to cut down on the size and weight of the step-down transformer. Such a high frequency applica-tion to the relatively small transformer core can result in magnetic saturation - unless the magnetic energy in the core is relèased by an opposite or cancelling flu.~. This is usually accomplished by closely regulating the high frequency application of the DC voltage level so as to allow for the subsequent cancel-lation of ~he magnetic flux build-up prior to saturation.
The prior art has the problem that in the event of an overcurrent ~0 conditionJ the main power ~ransform~r goes into saturation with ensuing collec-tor current spikes of the switching transistors. These spikes degrade the switching transistor life.
Also, the prior art monitors the AC line voltage and trips a one-shot if there is a voltage outage. Such prior art systems attempt to monltor an AC power outage at the AC input. Such systems are susceptible to minor fluctuations in AC line voltage so as to thereby result in frequent shutdol~ns.
This has somewhat been alleviated by providing one-shot cycles which provide .
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for an orderly shutdown only if the AC line voltage is still out at the end of the one-shot cycle. These systems none-theless trigger prematur~ shutdowns which may not be yet necessary at the various critical load points wherein power is being supplied.
It is an object of this invention to provide a power supply that is improved in these respects.
According to one aspect of the present invention, there is provided a power supply system for converting AC
voltage to a low-level DC voltage, said system comprising:
means for converting the AC voltage to a first DC
voltage level, means for transforming the first DC voltage level to the low-level DC voltage, said transforming means including a primary winding having first and second terminals and at least one secondary winding; and means for applying the first DC voltage level to said means for transforming the first DC voltage level to the low-level DC voltage, said means for applying comprising:
first and second transistor switching means, each of said switching means including first and second terminals, said first terminal of said first switching means beina connected to said second terminal of said second switching means in common with said first terminal of said primary winding, and said second terminal of first switching means being connected to said second terminal of said primary winding and to said first terminal of said second switching means; and control means for controlling the switchipg action of said first and second switching means, said control m~ans including:
first circuit means inductively coupled to said first and second terminals of said ~irst transistor switching means;
second circuit means inductively coupled to said first and second terminals of said second transistor switching means;
third means connected to said first and second circuit means, said third means being operative to generate first and second sets of pulse signals to be applied to said first circuit means and second circuit means respectively, said first switching means and said second switching means being alternately enabled and disabled in a push-puIl mode for operation by said first and second sets of pulse signals respectively.
In accordance with another aspect of the present invention, there is provided a power supply system for transmitting a low-level voltage to a plurality of loads, said power supply system comprising:
transforming means for applying the low-level voltage to said plurality of loads, said transforming means com-prising a primary winding and at least one secondary winding;
first transistor switching means coupled to said primary winding of said transforming means and being opera-tive to conduct current in a first direction through said primary winding;
second transistor switching means coupled -to said primary winding of said transforming means and being opera-tive to conduct current in a second direction through said - 2a -primary winding, the second current direction being opposite the first current direction; and means, coupled to said first and second switching means for controlling the switching action of said first and second switching means, said control means comprising:
two control transformers each with a primary winding and at least two secondary winclings;

- 2b -;6i6 said secondary windings from said Eirst control transformer con-nected in series ~ith said first switchin~ means, said secondary windings from said second control transformer connected in series with said second switchlng means, and means for alternately producing pulse conditions in the primary windings of each of said control transformers.
In the preferred embodiment, a power supply which rec~ives a stan-dard AC power source and is operative to first rectify the AC voltage and thereafter step down the resulting DC voltage level to an appropriate low-level DC voltage. The rectified voltage is thereafter applied to the primary winding of a step-down transformer under the control of a high frequency switch. The secondary windings of the transformer constitute parts of one or more circuits which filter and average the voltage induced across the second-ary windings so as to obtain a constant low-level DC output voltage. The high frequency switch controls the application of the rectified DC voltage to the primary winding of the step-down transformer in accordance with the sensing of the low-level DC output voltage. Magnetic saturation of the transformer core is prevented by not allowing any net direct current through the primary wind-ing of the step-down transformer.
In today's competitive computer environment, computing systems must operate in higher temperature environments than did systems in the past. This requires that in new designs the minimum off-time (the minimum time the switch-ing transistors are both off) be increased at higher ambients.
Without the temperature compensating circuits~ the minimum off-time must be set much higher thereby reducing power supply ride through. Ride through is the ability of the power supply to keep its outputs in regulation

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during the periods of time in which input AC voltage is removed and no "power fail" signal issued.
Temperature compensation in our circuitry greatly reduced the pro-bability of component failure during start-up in a high ambient temperature environment.
Lower ride through during shutdown at very high ambient temperatures --.3 --~`

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also results because the temperature compensation circui-ts double the switch-ing transistor off-time. This prevents catastrophic failure of the switching transistors at the highest ambient.
Our arrangement also prevents the output transformer from saturating by slowly increasing the volt-m~crosecond stress (pulse width) when turning on again after an overcurrent condition.
The circuitry provides for the monitoring of the rectified output transformer secondary winding voltage. It gives more accurate control over the ride through by anticipating the exact moment load voltages lose regula-tion and signals the digital computing system using this power supply to go into an orderly shutdown mode.
Our circuitry also gives the system more ride through and enables the system to be operative over longer intervals of line outage for varying loads.
Arragements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:-Figure 1 illustrates the overall configuration of the power supply.
Figure 2 illustrates the voltage doubler and 20KHz chopper circuits and the main power transformer.
Figure 3 illustrates the detailed circuitry of the control loop circuit, the base drive control circuit and the 20KH~ square wave oscillator of Figure 1.
Figure 4 illustrates the pertinent timing of the power supply.
Figure 5 illustrates ~he comparison with the prior art of ride through versus temperature.
Figure 6 illustrates the overcurrent circuits of Figure 1.
Figure 7 illustrates the power on/fail circuits of Figure 1.

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Figure S illustrates the power on/fail amplifier circuit of Figure 7.
Figure 9 illustrates the timing of the power on/fail circuits of Figure G.
Fi~ure 1 is a general block diagram of the power supply. The prim-ary source 120V 12A 60 hertz inputs the voltage doubler and switching transis-tor circuits 100 and the bias voltage circuits 500.
The chopped output of the voltage doubler and switching transistor circuits 100 passes through the primary windings of the main power transformer 101 and the overcurrent transformer 102. The secondary winding 106 of the main power transfo~mer 101 inputs into the ~ 18V voltage source 103. The +18V voltage source 103 feeds the +12V voltage source 104. The +18V voltage source 103 and +12V voltage source 104 are made up of conventional circuits.
Since they are not pertinent to the invention, they will not be dcscribed in detail.
The output of main power transformer 101, appearing in the second-ary winding 107, is rec~ified and filtered in +5V load voltage source 105 to ~, provide ~5 volts for the load 127.
The secondary winding output of overcurrent transformer 102 is sensed by overcurrent circuit 300 which signals the control loop circuit 200 of an overcurrent condition.
The voltage circuits 600 monitor the +5V and +12V outputs of +5 load voltage source 105 and +12V voltage source 104 and signal the control loop circuits 200 when an overvoltage condition occurs. Since the overvoltage circuits 600 are not pertinent to this invention, they will not be described in further detail.
The power on/fail circuit 400 signals that the voltage ou~puts are ~, :

'' ~ "~' ' i6 in regulation. If the voltage doubler and switching -transistor circuit 100 are out o~ tolerance, the power on/fail circuit 400 signals that the +5V, the +12V and the +l~V will shut down in two 1nilliseconds. The signal is given by logic level signal power on/fail signal 406.
The temperature compensation circuit 203 senses the ambient tempera-ture and signals the control loop circuits 200. This will also be described in detail hereinafter.
The bias voltage circuit 500 takes the 120V input voltage, steps it down, rectifies and filters it, and generates a +12.1V service supply to the control loop circuit 200, the base drive control circuit 201, the 20~lz square wa~e oscillator 202, overcurrent circuit 300 and the temperature compensation circuit 203. Also, the bias voltage circuit 500 generates the +5V reference supply to feed the control loop circuit 200. The 20KHz square wave oscillator 202 feeds the control loop circuit 200 with three wave shape signals. Figure 4 shows these three signals 202-1, 202-2 and 202-3 which will be explained in more detail below.
The base drive control circuit 201 controls the timing of the switch-ing transistors 115 and 116, Figure 2, in the voltage doubler and switching transistor circuits 100. Wave shapes 115-1 and 116-1 of Figure 4 show the timing of those switching transistors 115 and 116, Figure 2.
The control loop circuit 200 controls the timing of the base drive control circuit 201. This is described in detail in Figure 3.
The control loop circuit 200 receives input signals from the tempera-ture compensation circuit 203, the overvoltage circuit 600, and the overcurrent circuit 300, which adjusts the timings in control loop circuit 200. These changes in timings are reflected in the base drive control circuit 201, the voltage doubler and switching transistor circuits 100 and ultimately in the :; - .

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+5V load voltage source 105.
Figure 2 shows the voltage doubler and switching transistor circuits 100. The 120V 60~z input voltage comes in Oll lines 110 and 111. When the AC voltage on line 100 is positive, the current will proceed from line 110 through diode 112, capacitor 113 and back on line 111. Assuming a negative voltage on input line llO, the current will flow from input line 111, through capacitor 114, diode 115 and back on line 110. In this mannerJ either capaci-tor 113 or 114 is separately charged depending upon the polarity of the AC
voltage applied to the input lines 110 and 111. The resulting voltages across capacitors 113 and 114 combine to form a constant DC voltage equal to approx-imately twice the peak AC voltage on the input lines 110 and 111. This DC
voltage of approximately 300 volts provides an energy source for the switching power supply and supplies the ride through energy to allow an orderly shut-down after a power outage.
The circuit which provides control of switching transistors 115 and 116 and energy through the primary coil 119 of power transformer 101 is con-nected as follows. Capacitors 120 and 121 appear in series across the +300V
DC line. Also, diodes 131 and 132 also appear in series across the ~300V DC
line~ One terminal of the primary coil 119 of power transformer lOl connects 2Q to the junction of capacitors 120 and 121. The other terminal connects to one terminal of the primary winding of overcurrent transformer 102. The other terminal of the primary wind mg of overcurrent transformer 102 connects to the junction of diodes 131 and 132. A resistor 133 and a capacitor 134 are in series and connected across primary winding 119 of power transformer 101 and the primary winding of overcurrent transformer 102. The collector of switching transistor 115 connec~s to the ~300V DC line~ The base connects to terminal 3 of windi~g 136 of base drive transformer 117. The emitter connects :::

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19~i~6 to terminal 1 of the junction of windings 11~ and 136 of base drive transform-er 117. Terminal 2 of winding llS connects to the j~mction of diodes 131 and 132 as does the collector of switching trallsistor 116. The base connects to terminal 3 of winding 137 of base drive transformer 122. The emitter connects to terminal 1, the j~mction of windings 137 and 23 of base drive transformer 122, Terminal 2 of winding 123 connects to -~30W ~C return.
In Figure 2, when switching transistor 115 is conducting, the cir-cuit is completed from the ~300V DC line, switching transistor 115, coil 118 of base drive transformer 117, primary winding 119 of output power transform-er 101, and the primary winding of overcurrent transformer 102 to the junction of capacitors 120 and 121 (+150V DC). ~Yhen switching transistor 116 is con-ducting, the circuit is completed from the junction of capacitors 120 and 121, primary winding 119 of power transformer 101, the primary winding of overcurrent transformer 102, switching transistor 116, coil 123 of base drive transformer 122 to the ~300V DC return. Capacitors 120 and 121 are in series ; and split the ~300V DC to ~150V DC across each capacitor. They also isolate the circuit from any DC components preventing saturation of the main power transformer 101. Diodes 131 and 132 provide energy returns for the power transformer 101 during reduced output load conditions.
Resistor 133 and capacitor 134 provide a return path for the leakage inductance energy thereby preventing switching transistors 115 and 116 from being driven into the inverted transistor mode.
The ~5V load voltage source 105 provides the ~5V load voltage for a load 127. Figure 2 shows the center tapped secondary winding 107 of power transformer 101. Terminals 3 and 5 of secondary winding 107 of power tr~ns~
former 101 connect to the anodes of diodes 124 and 126 respectively. The cathodes of diodes 124 and 126 are connected in common to one side of an in-ductor 125. The other end of the inductor 125 connects to one end of the load .~

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127. Terminal 4 of secondary winding 107 connects to the other end of load 127. A resistor 130 and a capacitor 129 are each in parallel with the load 127.
The center tapped secondary winding 107 of power transformer 101 steps down the voltage generated across primary winding 119. When terminal

3 of center tapped secondary winding 107 is positive, the circuit is completed .
through diode 12~, inductor 125, through the load 127 to terminal 4. When terminal 5 of secondary winding 107 is positive, the circuit is completed through diode 126, inductor 125, through the load 127 back to terminal 4.
Figure 4 ~Yave shape 128 shows the voltage signal at point A, the junction of the cathodes of diodes 124 and 126. Wave shape 129 of Figure 4 shows the voltage across the load 127 which is regulated by inductor 125 and capacitor 129.
Resistor 130 acts as a bleeder resistor for capacitor 129 under no load conditions.
Secondary winding 106 of power transformer 101 provides the input energy for the +18V voltage source 103 which drives the +12V voltage source 104.
Figure 3 shows the control loop circuits 200, square wave circuitry 202 and the base drive control circuits 201. The power supply achieves the regulation of the +5V output to the load 127 by controlling the conduction time of the high vol~age switching transistors 115 and 116, Figure 2, by means of the control loop circuit 200 and the base drive control circuit 201.
Figure 4 shows the timing diagrams of various points in the circuit which accomplish this control.
The square wave circuitry 202, Figure 3, generates 3 outputs, a 20KHz square wave signal 202-1, a negated 20KHz ~20KHz) square wave signal _ g _ ::
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66~ii 20~-~ delayed 200ns from the 20KHz square wave signal 202-1, and a ~OKC trig-ger 202-~ The 20~Hz signal 202-1 appears at pin 1 of one input of a NAND
circuit of dual NAND gate 204. Tile 20~ 202-2 appears at pin 7 of the other NAND circuit of dual NAND gate 204.
The dual NAND gate 2~4 with an open collector output is preferably a 75~52 ~hich is commercially available and ~ully described in the Integrated Circuits Catalog for Design Engineers (page 3-250) by Texas Instruments Inc.
of Dallas, Texas. The other inputs on pins 2 and 6 of dual NAND gate 204 are formed as described hereinafter.
The P5V reference amplifier 205 is a commercially available voltage regulator L723-1 described fully in "The Voltage Regulator Applications Hand-boo~"3 1974, published by Fairchild Semiconductor, 464 Ellis S~reet, Mountain View, California 94042. The P5V reference amplifier 205 has an internal dif-ferential amplifier. This differential amplifier compares the +5V power supply load 127 on pin 4 through a resistor 209 with a reference voltage generated internally in the P5V reference amplifier 205 and raises or lowers the output at pin 10 of the P5V reference amplifier 205. If the load 127 +5V decreased, the pin 10 voltage increases and vice versa.
In the P5V reference amplifier 205, pin 4 and pin 5 are inputs to the internal differential amplifier. The output of pin 6 is the internally generated reference voltage of 7.2V. Pin 7 is a~ ground. The 7.2V output of pln 6 is divided do~in through a resistor 206~ a potentiometer 207, and a resistor 208 to ground. The potentiometer 207 is adjusted to set pin 5, one input to the differential amplifier, to +5V. The +5V load 127 is sensed at pin 4 through the biasing resistor 209. The ratio of resistor 235 and resistor 209 limits the gain of the differential amplifier. The output of pin 10 is divided down by resistors 210 and 211 to ground. The junction of resistors - 10 - .
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210 and 211 varies between 2.3V and 7.5V as the +5V load 127 varies and appears at pin 5 of one-shot 212. The one-shot 212 is commercially available as a 555-2 timer described fully in the application "Signetics Digital Linear MOS
Applications" 1974, by Signetics Corporation, 811 E. Arquen Avenue, Sunnyvale, California. The DC voltage at pin 5 of one-shot 212 is used in this power supply to modify the duty cycle of switching transistors 115 and 116 of Figure 2. Control is achieved by the output of pin 7 of one-shot 212 which is NANDed with the 20K~z signal 202-1 and the 20KHz signal 202-2 in dual NAND
gate 204. The NAND outputs at pins 3 and 5 of dual NAND gate 204 control the duty cycle of transistors 213 and 214.
As stated above, the divided down output of pin lO o~ the P5V refer-ence ampli~ier 205 appears at pin 5 of one-shot 212 and varies inversely as the ~5V load 127. The 40~Hz trigger output 202-3 appears at pin 2 of one-shot 212. This negative-going signal ~Figure 4, 202-3) switches one-shot 212 pin 3 high and pin 7 open.
The control of one-shot 212 comes from the circuit of a resistor 236 connected to one side of a potentiometer 237 and also to its movable tap.
The other side of potentiometer 237 connects to pin 6 of one-shot 212 and a resistOr 238. The other side of resistor 238 connects to the junction of a capacitor 215 and the anode of a diode 216. The cathode of diode 216 connects to pin 3 of one-shot 212. The other side of capacitor 215 connects to ground.
Capacitor 215 charges from the network of +12.1V, the resistor 236, the potentiometer 237, the resistor 238, the capacitor 215 to ground, until the vol~age at pin 6 becomes greater than the control voltage of pin 5 of one-shot 212. Figure 4 wave shape 212-1 shows the vol~age at pin 6 of one-shot 212. Note that if the +5V to load 127 goes low ~pin 4 of P5V reference ampli-fier 205) then the output, pin 10 of the reference amplifier goes high.

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~his causes pin 5 of one-shot 212 to go hi~h, causing capacitor 215 to charge for a longer time thereby keeping the one-shot 212 on for a longer time, shown by wave shape 212-2. ~s is sho~n below. this increases the duty cycle of switching transistors 115 and 116, Figure 2, increasing the ~5V at load 127.
Wave shape 212-3 shows the affect of -the 5V load 127 being too high, then capacitor 215 charges for a lesser period of time decreasing the duty cycle of switching transistors 115 and 116, Figure 2, thereby decreasing the +5V load 127.
Capacitor 215 is a commercially available temperature compensating capacitor. A preferred capacitor is that of No. 5016-N2200-43-1-J available from AVX Ceramics, Myrtle Beach, South Carolina. This capacitor 215 has a negative temperature coefficient of 2200 parts per million per C. At start-up with the ambient temperature high, the capacitance of capacitor 215 is decreased, decreasing the ~ime constant of charge. This causes the voltage at pin 6 of one-shot 212 to reach the pin 5 voltage sooner decreasing ~he duty cycle of switching transistors 115 and 116, Figure 2, as shown by wave shape 212-4, Figure 4.
If the ambient temperature were low, the capacitance of capacitor 215 increases, increasing the time constant as shown in wave shape 212-5, Figure 4, increasing the duty cycle of switching transistors 115 and 116, Figure 2.
~Yhen one-shot 212, pin 6 voltage equals pin 5 voltage, the output pins 3 and 7 go to ground and remain at ground until the next 40KHz trigger pulse 202-3. Pin 3 going to ground discharges capacitor 215 through diode 216. The temperature affects on pulse width of the one-shot 212 are only in effect at maximum pulse width, or when the output of the P5V reference ampli-fier pin 10 is saturated high. At all other times, the power supply is in , ... .

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-9~i6 reg~llation and the pulse width supplied by the one-shot 212 is what is re-quired to keep +5V load voltage at 5.0 volts.
The output of pin 7 of one-shot 212 appears at thc input pins 2 and 6 of both NANDs of dual NAND gate 204 where it is NANDed with the 20KHz signal 202-1 on pin 1 and the 20KHz signal 202-2 on pin 7. The pin 3 output of dual NAND gate 204 controls transistor 214 and the pin 5 output controls transis~or 21~. ~igure 4 shows the wave shapes 204-1, 204-2, and 204-3 at pins 6 and 2, 3 and 5 respectively.
The circuit which controls transistor 213 is made up of a resistor 217 connected to a junction of one side of -the parallel combination of a resis-tor 218 and a capacitor 219 and pin 5 of dual NAND gate 204. The other side of the parallel combination of resistor 218 and capacitor 219 connects to the base of transistor 213. The collector of transistor 213 is controlled by *he circuit from terminal 7 to terminal 8 of secondary winding 106 of power trans-former 101, a resistor 221, which connects to the anode of a diode 222. The cathode of diode 222 connects to the junction of terminal 6 of a secondary winding 135 of base drive transformer 122, the cathodes of a zener diode 224 and a diode 225 and a capacitor 223. The other side of the parallel combina-tion of zener diode 224, diode 225 and capacitor 223 connects to ground. The other side of secondary winding 135, terminal 5 connects to the collector of transistor 213. The emitter of transistor 213 connects to ground.
Transistor 213 is biased l'on" from 12.1V source supply, resistor 217, resistor 218, base of transistor 213, and emitter of transistor 213 to ground. Capacitor 219 charges through this circuit. When pin 5 of dual NAND
gate 204 switches to ground, the current path through resistor 217 is now 12.1V, resistor 21'7, pin 5 of dual NAND gate 204, pin 4 to ground thereby shutting off transistor 213. Capacitor 219 discharges at this time decreasing 6!E;

the cut-off time of transistor 213. Figure 4 wave shape 213-1 shows the volt-age at the transistor 213 collector. Just before transistor 213 shuts off, current is flowing through diode 225, winding 135, terminal 6, terminal 5, then through the collector of transistor 213 to ground. When transistor 213 shuts off, the voltage at terminal 5 of winding 135 becomes positive with respect to the voltage at terminal 6 because of the inductive energy in wind-ing 135. This causes the voltage at Figure 2 terminal 3 of winding 137 to become positive to the voltage at terminal 1. Therefore, the energy stored in winding 135 is transferred to winding 137 turning switching transistor 116 on. When switching transistor 116 turns on, the current path through winding 123 reinforces and provides the base drive to winding 137 to keep switching transistor 116 in saturation. Switching transistor 116 stays on as long as the pin 5 output of dual NAND gate 204 is at ground. Figure 4 wave shape 116-1 shows the collector current of switching transistor 116.
As shown previously, switching transistor 116 Figure 2 being "on"
delivers power ~o load 127 through power transformer 101 secondary winding 107. During the "on" time of switching transistor 116, current fTom power transistor 101 secondary winding 106 pin 6 flows in Figure 3 through resistor 221, diode 222, charging capacitor 223 to approximately 12-17V. Zener diode 224 limits the voltage across capacitor 223 to 17V maximum. Diode 225 clamps capacitor 223 to ground during discharge of capacitor 223.
~Yhen capacitor 215 is charged so that the voltage at pin 6 of one-shot 212 equals ~he voltage at pin 5~ then the output of pin 7 goes to ground.
~his brings pin 6 of dual NAND gate 204 to ground, shutting off transistor 225 in dual NAND gate 204. The circuit is then completed from ~12.1V, resis-tor 218 in parallel to capacitor 219 to the base of transistor 213, turning transistor 213 "on". Prior to transistor 213 turned on, capacitor 223 had , 6~

been charged via resis~or 21 and diode 222 to 12 to 17.0 volts DC. When transistor 213 turnson, the energy stored in capacitor 223 is transferred from transformer windin~ 135 of transformer 122 to winding 137 reverse bias-ing switching transistor 116 and shutting it off. (Terminal 3 of winding 135 is low at this time setting terminal 3 of winding 137 is low.) During the discharge of capacitor 223, diode 222 isolates capacitor 223 from the power transformer 101 circuits.
The circuit which controls transistor 214 is made up of a resistor 227 connected to a junction of one side of the parallel combination of a resistor 228 and a capacitor 229 and pin 3 of dual NAND gate 204. The other side of the parallel combination of resistor 228 and capacitor 229 connects to the base of transistor 214. The collector of transistor 214 is controlled by the circuit from terminal 7 to terminal 6 of secondary winding 106 of power transformer 101, a resistor 239 which connects to the anode of a diode 240.
The cathode of diode 240 connects to the junction of terminal 6 of a second-ary winding 138 of base drive transformer 117, the cathodes of a ~ener diode 243 and a diode 241 and a capacitor 242. The other side of the parallel com-bination of zener diode 243, diode 241 and capacitor 242 connects to ground.
The otner side of secondary winding 138 terminal 5 connects to the collector of transistor 214. The emitter of transistor 214 connects to ground.
Transistor 214 is biased "on" from 12.1V source supply~ resistor 227, resistor 228, base of transistor 214 and emitter of transistor 214 to ground. Capacitor 229 charges through this circuit.
When pin 3 of dual NAND gate switches to ground, the current path through resistor 227 is now +12.1V, resistor 227~ pin 3 of dual NAND gate 204, pin 4 to ground thereby shutting off transistor 214. Capacitor 229 discharges at this time decreasing the cut-off time of transistor 214. Just before ~' . . ~ ' ' :
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transistor 214 shuts off, current is flowing through diode 241, winding 138terminal 6, terminal 5, then through the collector of transistor 214 to ground.
~en transistor 214 shuts off, the voltage at terminal 5 of winding 138 be-comes positive with respect to the voltage at terminal 6 because of the induc-tive energy in winding 13S. This causes the voltage at Figure 2 terminal 3 of winding 138 to become positive to the l~oltage at terminal 1, therefore, the energy stored in winding 138 is trans:Eerred to winding 136 turning switch-ing transistor 115 on. ~hen switching transistor 115 turns on, the current path through winding 118 reinforces and pro~ides the base drive to winding 136 to keep switching transistor 115 in saturation. Switching transistor 115 stays on as long as the pin 3 output of dual NAND gate 204 is at gro~md.
~witching transistor 115 being "on" delivers power to load 127 through power transformer 101 secondary winding 107. Switching transistor 115 shuts off in a manner similar to that described for the shut-off of switching transistor 116.
The output of dual N~ND gate 204 pin 5 at ground controls the shut-down of transistor 213 and pin 3 at ground controls the shutdown of transistor 214.
The complete cycle operates as follows. The 40~1z trigger 202-3 starts one-shot 212 which switches pin 3 and pin 7 of one-shot 212 high. Pin 3 of one-shot 212 high allows capacitor 215 to charge. ~hen pin 7 of one-shot 212 goes high setting pins 2 and 6 of dual NAND gate 204 high~ ~hen transistor 226 of dual NAND gate 204 conducts when the 20KHz 202-1 is high. Transistor 225 of dual NAND gate 204 conducts when the 20~1z 202-2 goes high. When transistor 225 conducts> pin 5 of dual NAND gate 204 goes to ground shutting off transistor 213. When transistor 226'conducts, pin 3 of dual NAND gate 204 goes to ground shutting off transistor 214.

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~ hen capacitor 215 is charged up sufficiently for the voltage at pin 6 of one-shot 212 to equal the voltage at pin 5 of one-shot 212, then pin 7 of one-shot 212 goes low, setting pins 2 and 6 of dual NAND gate 204 low, shutting off either transistor 225 or 226 of dual NAND ga~e 204. This raises the voltage of pin 3 or pin 5 allowing the appropriate transistor 213 or 214 to begin conducting again.
When pins 1 and 2 of dual NAND gate 204 are high, transistor 226 conducts and the circuit is completed from 12.lV service voltage, resistor 227 pin 3 of dual NAND gate 204, transistor 226, pin 4 to ground. This sets pin 3 of dual N~ND gate 204 to ground cutting off transistor 214.
~igure 4 202-1 shows the 20KHz square wave which appears at one leg of a NAND of dual NAND gate 204 pin 1. 202-2 shows the 20KHz square wave which appears at one leg of the other NAND of daul NAND gate 204 pin 7. 202-3 shows the 40KHz trigger which starts capacitor 215 to charge when one-shot 212 pin 2 is pulsed by the negative going 40KHz trigger 202-3. 212-1 shows the voltage rise at one-shot 212 pin 6 as capacitor 215 charges. 212-2 (shaded area) shows the wave shape if the +5V load 127 voltage is low. 212-3 ~shaded area) shows the wave shape if the +5V load is high. Wave shape 204-1 shows the power pulse width, that is the approximate time unrectified power is applied to load 127. 204-2 (shaded area) is grea~er for +5V load 127 voltage low and 204-3 (shaded area) is less for +5V load 127 voltage high.
204-10 shows ~he NAND output of 20~1z square wave 202-1 and the one-shot 212 output pin 7. 204-11 shows the NAND output of ou~put square wave 20KHz and the one-shot 212 output pin 7. The rise and fall of 204-12 shows the low +SV load 127 voltage width and 204-13 shows the high ~5V load 127 voltage width.
Wave shape 214-1 shows the voltage at the collector of transistor .

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214. ~ave shape 213-1 shows the voltage at the collector of transistor 213 with 213-2 sho~ing the off-time width during low +5V load 127 voltage and 212-3 showing the off-time wid~h during high +5V load 127 voltage.
I~ave shape 115-1 shows the colle!ctor current of switching transis-tor 115.
Wave shape 116-1 shows the collector current of switching transis-tor 116 with 116-2 showing thc wave shape width for low +5V load 127 voltage and 116-3 showing the wave shape width for high +5V load 127 voltage. Poten-tiometer 217 in the charging circuit of capacitor 215 is adjusted for the 5 microseconds time at 25C when both switching transistors are off under nomi-nal conditions. If the 5 microsecond gap approaches ~ero, then large stresses are put on switching transistors 115 and 116 increasing probability of catas-trophic transistor failure.
Wave shape 128 shows the load power pulses at the cathod of the rec-tifier diodes. 1~8-2 (shaded) shows low +5V load 127 voltage and 128-3 ~shaded) shows hlgh +5V load 217 voltage ripple 129 shows the l-5V load 127 voltage after regulation.
Assuming that the +5V to load 127 is low, capacitor 215, Figure 3 ; will charge for a longer time period until the pin 6 voltage of one-shot 212 equals the pin 5 voltage ~less than 5V). Pulse 212-2 shows a pulse of longer duration. This results in a wider pulse 204-2 as the output of one-shot 212, pin 7, Figure 3. As a result, pulse 204-12, Figure 4, is wider causing tran-sistor 213 to be off for the duration shown in pulse 213-2 causing switching transistor 116 to be on for the pulse period 116-2. This results in more energy provided load 127 since pulse 128-2 is wider.
Changes in ambient temperature can be followed through Figure 4 in a similar manner by noting dotted line changes in 212-4 and 212-5. But again, - , ; ~ . ' ,- ' .
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. . : .. :, . :
- ~. : . .,: , -the temperature affects on pulse widt}l occur during power supply turn on before output vol~a~es are in regulation, and during turn off ~fter output voltages fall out of regulation and before the large power supply storage capacitors 113 alld 11~l of Figure 2 are fully discharged.
Figure 5 shows a curve of ride through in milliseconds versus am-bient temperature. Ride through is the time the DC output power is on after the AC input power goes off. In the normal operating temperatures, the ride through with temperature compensation as described in this invention is greater than the prior art which is very desirable. In ambient temperature aoove the normal operating range, the ride through with temperature compensa-tion is less than the prior art which is also desirable. At higher tempera-tures, storage, the rise and fall times of transistors greatly increase, possibly causing crossfire current spikes. The prior art circuitry causes stress provoking spikes under this condition of high ambient temperature which increases the rate of component catastrophic failure. This invention by de-creasing the ride through, decreases the probability of stress provoking spikes by avoiding crossfire conditions in the circuitry thereby increasing component life.
Figure 6 shows the overcurrent circuit 300. The primary winding 119 of main power transformer 101 is in series with the primary winding of the overcurrent transformer 102. The secondary winding circuit of oveTcurrent transformer 102 is connected as follows. Terminal 1 connectsto the junction of a diode 306 cathode and a diode 301 anode. Terminal 2 connects to the iunction of a diode 304 cathode and a diode 305 anode. The junction of the diode 306 anode and the diode 304 anode connects to ground. The junction of the diode 305 cathode and the diode 301 cathode connects to the junction of a resistor 302, a capacitor 303 and pins 6 and 2 of overcurrent amplifier 307~

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6~6 The other side of resistor 302 and capacitor 303 connects to ground. A capa-citor 309 in parallel with the anode of a zener diode 308 connec-ts between overcurrent ampli~ier 307, pin 5 and ground. Pin 1 connects to ground. Pins

4 and 8 connect to the j~nction of a resistor 310 and the cathode of a diode 311. Resistor 310 connects to ~18V and diode 311 anode connec~s to ~12V.
Pin 7 connects to the junction of capacitor 234, the cathode of diode 233 and resistor 231.
Overcurrent amplifîer 307 is a 555-2 amplifier that was described previously.
Overcurrent transformer primary winding 102 senses the current through the primary winding 119 of output transformer 101. The current is stepped do~ in the secondary winding of overcurrent transformer 102. When the voltage at terminal 1 is high, the circuit is completed through diode 301 and the parallel combination of resistor 302 and capacitor 303, diode 304 to terminal 2 of overcurrent transformer 102. When the voltage at terminal 2 is high, the circuit is completed through diode 305, the parallel combina-tion of resistor 302 and capacitor 303, diode 306 to ~erminal 1. In both cases, the voltage drop across resistor 302 in parallel with capacitor 303 appears at pins 2 and 6 of overcurrent amplifier 307 and is proportional to load power. Overcurrent amplifier pin 5 is biased at 6.2V by zener diode 308.
Capacitor 309 reduced the zener diode noise. If load power exceeds a pre-determined value, the voltage a~ overcurrent amplifier 307, pins 2 and 6 ex-ceeds the voltage at pin 5, thus pin 7 grounds junction 244 Figure 3, dis-charging capacitor 234 Figure 3. Normally, capacitor 234 is charged to 12.lV
through resistor 231. Also, diode 233 is back biased. Capacitor 234 dis-charging sinks current out of pin 13 of P5V reference amplifier 205 through resistor 232 and diode 233. Pin 13 of the P5V reference amplifier 205 has a .
' . . ~ ~ . :
: .. , .. ' ` ( ~96~6 higll outp-lt impedance and sinking current out of pin 13 and sets pin 10 of P5V reference amplifier 205 low setting pin 5 of one-shot 212 low. Then as capacitor 215 starts to charge when the 40KHz trigger 202-3 signal connected to pin 2 of one shot 212 goes low, pin 7 goes high almost immediately, keep-ing transistors 213 and 214 off for a very short time, turning switching transistors 115 and 116 on for a very short -time. Figure ~, 212-6, 204-6, 204-16, 214-6, 115, 6 and 128-6 show the greatly reduced power to load 127.
As the output power decreases, the current through the primary winding of overcurrent transformer 102 decreases, decreasing the voltage in-duced in the secondary winding of overcurrent transformer 102, decreasingthe voltage across resistor 302 and capacitor 303 in parallel. This decreases the voltage at pins 2 and 6 of overcurrent amplifier 307 below the 6.2 volts of pin 5, switching pin 7 to open removing the ground on junction 244. This causes capacitor 23~ Figure 3 to charge to 12.1V through resistor 231. The DC voltage on capacitor 234 control the maximum available power pulse width by sinking current out of pin 13 of the P5V reference amplifier 205 through resistor 232 and diode 233. Therefore, as capacitor 234 charges, the voltage at pin 10 of the P5V reference amplifier 205 rises gradually increasing the power pulse width to maintain the l5V load 127 voltage. This ~echnique slowly increases the volt microsecond stress on main power transformer 101 and pre-vents collector current spikes in switching transistors 115 and 116 Figure 2 thereby preventing the saturati~g of main power transformer 101.
Diode 311 and resistor 310 assure that the voltage on pins ~ and 8 of overcurrent amplifier 307 is operative in the event that the +12V supply is shorted to ground. In that event, current will flow from ~15V, through resistor 310 to pins ~ and 8. Diode 311 is back biased at this time, blocking the current flow to the grounded ~12V supply.

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Figure 7 illustrates power on/fail circuit ~00. Power on/fail sig-nal 406 is a logic level which interrupts the digital computer. It is to be understood that electronic computer systems are in general equipped with appropriate logic which allows for an orderly shutdown upon receiving such a signal. Such logic does not form a part of this invention except insofar as being the recipient of the signal herein developed. This signal is at ground during power-up and power-down and is at +5 volts after all of the voltages are in regulation. During any AC input voltage outage, the power on/fail status signal 406 switching to ground tells the system to go into an orderly shutdown and guarantees at least two more milliseconds of DC power.
Figure 2 shows the circuit which monitors the output of secondary winding 106 of power transformer 101 and rectifies this output through diodes 407 and 408.
In Figure 7, the power on/fail circuit 400 is connected from terminal 6 of the secondary winding 106 of main power transformer 101 to the anode of diode 407. Terminal 8 connects to the anode of diode 405. Terminal 7 connects to ground. The cathodes of diodes 407 and 408 connect to a resistor 409 which connects to the cathode of a zener diode 410. The anode connects to the anode of a diode 411. The cathode connects to the junction of a resistor 412, a capacitor 413 and the anode of a diode 414. The cathode of diode 414 connects to ~ c~pacitor 415 and the anode of a diode 418. The other side of resistor 412 and capacitors 413 and 415 connect to ground. The cathode of diode 418 connects to the +12V 420 supply as do pins 4 and 8 of a power on/fail amplifier 401 which is a 555-2 timer that was described previously. Pin 1 connects to groundJ pi~s ~ and 6 connect to the junction of resistor 412, capacitor 413, and diode 411. Pin 3 connects to a ~esistor 41~ which connects to the base of a transistor ~2. P}n 5 co~ec~s ~o ~ne si~e o t~e c~ f relay 404 and , . . : . : - :

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9~6~i the cathode of zener diode 417. The anode connects to ground, and the other side of the coil of relay 416 connects to +12V 420. The emitter of transistor 402 connects to ground, the collector connects to the junction o~ one contact of the normally closed switch 4~5 of relay 404, a resistor 403 and power Oll/
fail st~tus signal 406. ~e other ~o~tact o~ normally closed switch 405 con-nects to ground. Th~ other side o~ Tesistor 403 connects to the +5V supply.
Figure 5 illustrates the power on/fail amplifier 401 which is a commercially available 555 timer which was previously described. Figure 9 illustrates the timing relationships of the power on/fail amplifier 401 and the power on~fail status signal 406.
When the power supply system is turned on, normally closed contact ~05 of relay 404 holds the power on/fail status signal 406 at ground. Then the +12V 420 of the +12V voltage source 104 starts to rise and as the voltage at pin 8 of power on/fail amplifier 401 reaches +4V, which is the minimum operating voltage of the power on/fail amplifier 401, current flows from pin 3 of the power on/fail amplifier 401 through resistor 419 into the base of transistor 402, turning it on and holding the power on/fail status signal 4~6 at ground.
The pin 3 of power on/fail amplifier 421 is high whenever pin 5 is at a higher voltage than pin 6. In this case, ~ener 410 is back biased and pre~ents any flow of current through resistor 412 keeping pins 2 and 6 near ground potentiQl. The circuit to pin 5 is completed from +12V 420 ~+4Y at this time), relay coil 416 pin 5, resistor 426 Figure 8, resistor 427, to ground pin 1. This puts pin 5 at essentially 4V since resistors 426 and 4~7 have a high i~pedance relative to relay coil 416. The ~oltage of pin 5 bigher than pin 6 results in an output from comparator 421 setting flip-flop 423 whi~h sets the output stage 424, pin 3~ high.

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Figure 9 shows pin 3 rising at Tl time when the pin 5 voltage is appro~imately ~V. The circuit holdillg the power on/~ail status signal at ground is +5V 421, resistor 403, collector of transistor 402, emitter to ground. Resistor 41~ limits the transistor 402 base current.
I~en the ~12V ~2~ reac~es approximately lOV, relay 404 energizes from +12V 420, relay coil 416, zener diodc 417 to ground. This opens normal-ly closed contacts 405 o~ relay ~04, however, the power on/fail status signal 406 remains at ground since transistor 402 still conducts. This circuit also clamps pin 5 to 6.2V by zener diode 417.
~hen the positive voltage at terminal 6 of secondary winding is above the breakdol~n Yoltage of 2ener 410, the circuit is completed through diode 407, resistor ~09, zener diode 410, diode 411 and the parallel network of resistor 412 and capaci~or 413 to terminal 7 of secondary winding 106.
Capaci~or 415 is also charging through diode 414. When the ~oltage across capacitors 413 and 415 reaches 6.2V, which appears a~ pins 2 and 6 of the power on/fail amplifier 401, then the output of pin 3 switches to ground turn-ing transistor 402 off. This sets the power on/fail status signal 406 high through +5V 421 through pull-up resistor 403. In Figure 8, pin S is no~ at 6.2V. When pin 6 goes greater than 6.2V, then the comparator 421 output re-sets flip-flop 423 setting pin 3 of output stage 424 low.
Figure 9 shows pin 3 going low at T2 time ~hen pins 2 and 6 are at 6.2V setting the power on/fail status signal ~06 lligh.
In the preferred embodiment~ the time constants of the circui~ are selected such $hat the +5V load voltage sources 105 Figure 1 is in regulation ~or at least 4 ~illiseconds before the power on/fail status signal 406 goes to +5~ 421. ~i~de ~14 and ~apacito~ 415 inorease the time constant of the network of resistor ~112 and o~aeit4r 41~ ~uring turn-on. Diode 414 blocks , -'~

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the discharge of capacitor 415. Diode 411 blocks the discharge of capacitor 413 during the half cycles that the secondary winding 106 is at ground. The æener diode 410 was selected at 22V to assure that with resistors 409 and 412 and diode 411, the power on/fail status signal 406 is issued during turn-on when the AC input voltage is as low as 100 volts. At AC input power failure, the power supply is operative as long as the AC input voltage is greater than 90 volts. During turn-off, be it deliberate by the operator or a power out-age, the power on/fail status signal 406 will go to ground at least two milli seconds before the DC voltages lose regulation.
At loss of AC line power, capacitor 413 starts to discharge because the voltage across secondary winding 106 decreases. When the voltage across capacitor 413 reaches a lower value which is preferably set at 3.1V, pin 3 of the power on/fail amplifier 401 switches high turning on transistor 402 and pulling the power on/fail status signal 406 to ground. In Figure 8, the pin 2 voltage is lowered and when it equals 3.1V, it compares with the pin 5 volt-age of 6.2V, divided down by resistors 426 and 427 to 3.1V, causing the compa-rator 422 output to set flip-flop 423 setting the output stage 424, pin 3, high.
Figure 9 shows pin 3 high at T3 time when pins 2 and 6 are at 3.1V
set.ing power on/fail status signal 406 low.
Diode 418 removes the charge from capacitor 415 when +12 volts 420 has discharged. The components are selected that the DC output voltages are in regulation for two milliseconds aftçr the power on/fail status signal 406 goes to ground.
When the +12V 420 decays below 7V, relay 40~1 de-energizes releasing its normally closed contacts 405, clamping the power on/fail status signal 406 at ground. The leading and trailing edges of the power on/fail status signal 406 are guaranteed bounceless because trans stor 402 controlled by po~er on/fail amplifier 401 has at least three volts of hysteresis and does all the voltage switching.
During turn-on, the power on/fail status signal 406 will be issued when the square wave voltage of secondary winding 106 is greater than V zener 417 (1 + R41029) ~ V zener 410 + 1.5V
During turn-off, the power on/fail status signal will switch to ground when the square wave voltage of secondary winding 106 is less than V zener 417 (1 + R410-29) + V zener 410 + 1-5V

During turn-on, the capacitors 413 and 415 and the parallel combi-nation of resistors 409 and 412 contribute to the 4 millisecond time between the DC voltages in regulation and the power on/fail status signal 406 trans-ferring to +5V 421.
During turn-off, the discharge of capacitor 413 and the parallel combination of resistors 409 and 412 contribute to the 2 milliseconds that the DC voltages are in regulation after the power on/fail status signal 406 switches to ground.
The above circuits in conjunction with the capacitors 113 and 114 of Figure 2 contribute to the aforementioned time intervals.

,

Claims (13)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A power supply system for converting AC voltage to a low-level DC voltage, said system comprising:
means for converting the AC voltage to a first DC
voltage level, means for transforming the first DC voltage level to the low-level DC voltage, said transforming means including a primary winding having first and second ter-minals and at least one secondary winding; and means for applying the first DC voltage level to said means for transforming the first DC voltage level to the low-level DC voltage, said means for applying comprising:
first and second transistor switching means, each of said switching means including first and second terminals, said first terminal of said first switching means being connected to said second terminal of said second switching means in common with said first terminal of said primary winding, and said second terminal of first switching means being connected to said second terminal of said primary winding and to said first terminal of said second switching means; and control means for controlling the switching action of said first and second switching means, said control means including:
first circuit means inductively coupled to said first and second terminals of said first transistor switching means;
second circuit means inductively coupled to said first and second terminals of said second transistor switching means;

third circuit means connected to said first and second means, said third means being operative to generate first and second sets of pulse signals to be applied to said first means and second means respectively, said first switching circuit means and said second switching circuit means being alternately enabled and disabled in a push-pull mode for operation by said first and second sets of pulse signals respectively.

2. The system of claim 1 wherein said control means for controlling the switching action of said first and second switching means comprises:
a first control transformer and a second control transformer, each with a primary winding and a first and second secondary winding;
said first and second secondary windings of said first control transformer connected to said first and second terminals of said first transistor switching means and said first and second secondary winding of said second control transformer connected to said first and second terminals of said second transistor switching means;
said first secondary winding of said first control transformer enabling for operation said first transistor switching means;
said second secondary winding of said first control transformer maintaining for operation said first transistor switching means, and said first and second secondary windings disabling for operation said first transistor switching means, then alternately said first secondary winding of said second control transformer enabling for operation said second transistor switching means, said second secondary winding of said second control transformer maintaining for operation said second transistor switching means and said first and second secondary windings disabling for operation said second transistor switching means; and means for alternately producing pulse conditions in the primary windings of each of said control trans-formers.

3. The system of claim 2 wherein said means for alter-nately producing pulse conditions comprises:
comparison means for detecting a relative voltage difference between low-level DC voltage applied to a load and a reference voltage, said comparison means being operative to produce a variable signal which varies in accordance with the detected relative voltage difference;
means, responsive to the variable signal from said comparison means, for producing a train of pulses having variable widths proportional to the voltage difference between the low-level DC voltage applied to said load and the reference voltage; and means for alternately applying the variable width pulses to the primary windings of each of said control transformers.

4. The system of claim 3 wherein said means for alter-nately producing pulse conditions further comprises:
variable capacitive means connected to said means for producing variable width pulses, said variable capacitive means being operative to define the width of the variable width pulses as a function of ambient temperature during power start-up and shutdown.

5. The system of claim 3 wherein said means for alter-nately applying the variable width pulses comprises:
a pair of gating means for receiving the variable width pulses; and timing means for producing two trains of complementary pulses, one of the trains of complementary pulses being applied to one of said pair of gating means, the other train of complementary pulses being applied to the other of said pair of gating means so as to alternately enable each of said gating means in accordance with the frequency of the trains of complementary pulses.

6. The system of claim 5 wherein said timing means further produces a third train of pulses, the frequency of the third train of pulses produced by said timing means being double the frequency of either of the first two trains of complementary pulses, said means for producing the variable width pulses being responsive to the third train of pulses produced by said timing means so as to produce the train of variable width pulses in response thereto.

7. The system of claim 5 further comprising:
first and second circuit means, responsive to outputs from said pair of gating means, for alternately applying the variable width pulses to the primary windings of said pair of control transformers.

8. A power supply system for transmitting a low-level voltage to a plurality of loads, said power supply system comprising:
transforming means for applying the low-level voltage to said plurality of loads, said transforming means comprising a primary winding and at least one secondary winding;
first transistor switching means coupled to said primary winding of said transforming means and being operative to conduct current in a first direction through said primary winding;
second transistor switching means coupled to said primary winding of said transforming means and being operative to conduct current in a second direction through said primary winding, the second current direction being opposite the first current direction; and means, coupled to said first and second switching means for controlling the switching action of said first and second switching means, said control means comprising:

two control transformers each with a primary winding and at least two secondary windings;
said secondary windings from said first control transformer con-nected in series with said first switching means, said secondary windings from said second control transformer con-nected in series with said second switching means, and means for alternately producing pulse conditions in the primary windings of each of said control transformers.

9. The power supply system of claim 8 wherein each of said plurality of loads is connected to a secondary winding of said transforming means and said means for controlling said switching means comprises:
means for detecting the low-level voltage applied to at least one of said plurality of loads by said transforming means, said detection means being operative to compare the detected low-level voltage with a reference voltage; and means, responsive to the detection of a difference between the low-level voltage and the reference voltage for alternately enabling said first and second switching means.

10. The power supply system of claim 9 wherein said means for alternate-ly enabling said first and second switching means comprises:
means for producing the train of pulses having varible widths pro-portional to the voltage difference between the low-level voltage applied to said load and the reference voltage; and means for selectively gating the train of variable width pulses to said first switching means and said second switching means so as to alter-nately enable each of said switching means.

11. The power supply system of claim 10 wherein said means for producing a train of pulses having variable widths comprises:
capacitive means connected to said means for detecting the low-level voltage, said capacitive means being operative to reflect the voltage difference between the low-level voltage and the reference voltage, and means for generating pulses having elapsed time durations proportional to the voltage difference reflected by said capacitive means.

12. The power supply system of claim 11 wherein said capacitive means has a capacitance that varies with respect to the ambient temperature of the power supply system during power start-up and shutdown.

13. The power supply system of claim 12 wherein said means for selectively gating the train of variable width pulses comprises:
a pair of gating means for receiving the train of variable width pulses; and timing means for producing two trains of complementary pulses, one of the train of complementary pulses being applied to one of said pair of gating means, the other train of complementary pulses being applied to the other of said pair of gating means so as to alternately enable each of said gating means in accordance with the common frequency of the trains of complementary pulses.