CA1108302A - I/o terminal identification - Google Patents

Abstract

26260 I/O TERMINAL IDENTIFICATION Abstract of the Disclosure Control of the data format programmed into an interface means by a computer means is provided in response to the data format required by an I/O device. A register in the interface means is programmed to respond to only a first digital address from the computer means. A switching means having first and second positions is utilized to create "don't care" positions in a digital address from the computer means to the interface means. Because of the "don't care" positions in the digital address the register in the interface means will respond to a second digital address when the switching means is in the first position. The register will not respond to the second digital address when the switching means is in the second position. When the register responds to the second digital address then the computer programs the data format required by a first I/O means into the interface means. When the register does not respond to the second digital address then the computer programs the data format required by a second I/O means into the interface means. Thus, the position of the switching means determines the data format which will be programmed into the interface means.

Description

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26~260 :
I/O TERMINAL ID~ITIFIGATI0 This inventlon relates'to a method and apparatus for controlling an interface means 'between a computer means and an input/output (I/O) device. In a particular aspect this invention relates to a method and apparatus for providing inormation to a computer means concerning the'data format which must be pro~
grammed into the interEace mean~ to allow data transmission between ths computer means and the I/O device where diferent I/O devices which demand diEerent data formatting schemes may be utilized in~erchangeably. -' In present day computer technology it is oEten desirable to provide data from a computer ~eans to a variety of ItO devices'such as teletype machines ~TTY), cathode ray tubes (CRT2 or thermal printers~ It is also desirable to input data to the computer means from the I/O devices. In both cases the data ~ , must be ~ormatted so that it may be utilized by either the computer means or the I/O devices. Special circuits termed interface means have been developed in many cases to perform the required data ormatting function. '~ ' The computer must kno~ what type oE I/O device is in the system to ~ ' know what data format to program in-to the interface means. If only one type ~ ' of I/O device is utili~ed there is no problem. The problem occurs when different types of I/O devices may be used interchangeably in the same system because the computer means often has no way of knowing what type of I/O device is in the system at any one time. An example of this is when a TTY and a CRT terminal may be utilized interchangeably. A TTY requires 11 bits of serial data at 110 baud. Most other serial I/O devices such as a CRT requires 10 bits of serial data at rates above 300 baucl. Dif~erent data formats are thus required for a TTY and a CRT or for any other types o I/O devices which use different data rates or di~erent serial bit lengths.
This problem is especially evident in the field of microprocessors.
The entire computer system is often on chips and there is simply no way to provide an outside address to the microprocessor to tell it ~Jhat kind of I/O
device is in the system at any one time~ This would preven-t the use of micro-processors in applications where different types of I/O devices requiring -1- ,~
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dlfferent data formats may be used interchangeably in the same system unless a method is provlded whereby the microprocessor can know what type o~ I/O device is in the system at any one time.
Accordingly it is an o~ject o~ this invention to provide a method and apparatus for controlling an -interface méans be~ween a comp~uter means and an I/O device. It is a particular object of this invention to provide a method and appara-tus for providing information to a computer means concerning the data format which must be programmed into the interface means to allow data transmission between the computer means and the I/O devices which demand lQ different data formatting schemes may be utilized interchangeably.
In accordance with the present invention a method and apparatus is provided whereby image locations created by "don't cares" are utilized to pro-vide the computer means with information as to what type of I/O device is in the system. This is done by using binary images. An example of this is where there is a register in an interface maans which has been programmed to send data to the computer means when the address from the computer means to the interface means is equal to 0100. If a switching means is utilized so that the second leas-t significant bit is in a "don't care" position then the address 0100 will be identical to the address 0110 when i-t is received by the interface means. The register will thus respond to an address of 0110 even though it is programmed to resyond only to an address of 0100. T~e computer pro~rams the interEace means with one data format corre~ponding l:o one type of I/O device if the register responds to an address of 0110 and with another data format corresponding to a second type of I/O device if the register does not respond to an address oE 0110. The switching means position may be set by an operator or may be set automatically to correspond to a certain type of I/O device and in this manner the computer means is provided with information as to the type of I/O device in the system.
Other objects and advanta~es o~ the inven~ion will be apparent from the description of the invention and the appended claims thereto as well as from the detailed description of the drawing which is a block diagram of the -required interfacing for a typical microprocessor to I/O terminal ~link.

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For the sake o~ convenlence and ease of illustratlon ~he invention ;~ ~
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will be described in terms of a preferred embodiment utilizing the Motorola ~' 6800 microprocessor family. Although the invention ls described in terms o a specific computer system, the invention is also applicable to other computer systems where information must be provided to a computer as ~o what type of I¦O device is in the system at any particular time.
A specific address and programming scheme is set forth in the descrlp~
tion of the preferred embodiment of the invention as an example only. As is ~ell Icnown in the art many dif~erent program~ing schemes cduld be utilized depending on the computer sys-tem invGlved. The inventiGn is applicable to any programming scheme which is part of a method and apparatus such as those described in the preferred embodiment of t~is invention and which performs the functions of the programmlng scheme set forth as an example in the preferred embodiment of the învention.
Referrîng now to t'he drawing the microprocessor (MPU) 11 is, in this preferred embodiment, a Motorola 6800 microprocessor. The Asynchronou~ Communi-cation Interface Adapter (ACIA~ 13 is a Motorola 6850. Both the Motorola 6800 and 6850 are well known systems. Operational and functional characterlstics are set forth in detail in'Microprocessors'And Microcomputers by Branko Soucek, published by John Wiley and Sons, 1976, at pages 299-340 and in Microcomputer-Based Design by John B~ Peatman, published by McGraw-Hill Inc., 1977, at pages ~81-494~ ~ ~
The interface means 15 converts the 0-5 volt transistor-transl~tor logic (l'TL) levels from the ACIA to ~he current or voltage levels required by the I/O terminals. In thia preferred embodiment the I/O terminal i8 a teletype terminal 17 or a terminal 18 which i8 compatl'ble with ~IA RS232. The inter~ace converts the TTL levels from the ~CIA to a 20 ma loop for the ~eletype tPrminal 17 or to + 12 volts for a terminal 18 which requires an RS232 input.

The baud rate control means 19 contr~ls the baud rate of the data flo~ from the NPU 11 to the I/O ~erminals 17 and 18 and from the~I/O terminals 17 and 18 to the ~PU ll.

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, Both the baud rate control 19 and the interface means 15 are well known in communications art. A Programmable Bit Rate Generator, 34702, manufac-tured by Fairchild Semiconductor may be used as a 'baud rate control means.
One method of implementing the 34702 as a baud rate control-means is shown on page 292 of Microcom~uter-Based ~ by John B. Peatman, McGraw-Hill, 1977.
The 9616, Triple EIA RS-232-C/Mil-Std-188C Line Driver and the 9617, Triple ~ ' -EIA RS-232-C Line Receiver manufactured by Fairchild Semiconductor may be used as a ~TL to RS-232 and RS-232 to TT1 interface. The'4371 Optical Isolator manufactured by Hewlett Packard may be used in conjunction with a current limiter as an interface for a TTY terminal requiring a 2Q ma loop.
The MPU 11 is connected to the ACIA 13 through the two-way signal ~`
lines 21-29. Signal lines 21-25 are representative of the six~een signal lines available for addressing. Signal line 26 carries the valid memory address (V~) signal. Signal 27 is an enabling signal. Signal 28 is a read/write signal. Signal 29 is representative of the eigh~ signal lines available for data. The terminology ls consistent with the re~erences cited above. These references give a further description o~ the generation and function of these signals.
Signal 21 is supplied to the ACIA 13 as signal 30 when the switching means 32 is in the position sho~n in FIGURE 1 which will be referred to as the first or AO position. Signal 22 is supplied to the ACIA 13 as signal 30 when the switching means is in the second or alternative position from that shown in FIGURE 1. This second or alternative position will be referxed to as the Al position. The switching means 32 is, in a preferred embodiment, a 53137-l manu~actured by AMP, Inc.
The interface means 15 is connected to the ACIA 13 through signal lines 41-45. These signal lines carry asynchronous serial data and con*rol signals. The interEace means 15 is also connected to the I/O terminal 17 through signal line 47 and to I/O terminal 18 t'hrough signal line 48. Signal line 47 carries as~lchronous serial data from the inter~ace means 15 to the I/O terminal 17 and from the I/O terminal 17 to the interface means 15.

Signal line 48 carries asynchronous serial data from the interface means 15 to the I/0 terminal 18 and ~rom the I/0 terminal 18 to the in~erface means 15.
The baud rate control 19 -ls connected to the ACIA 13 through s:ignal line 4~
The ACI~ 13 con~a-lns four registers.. These are a status register 51~ a control register 52, a transmit data register 53,'and a recei~e data register -~
54. These registers may be programmed in such a manner that a speci-~ic digital address from the ~PU 11 will enable a pair of -the'registers to perform their function. ~ `
As has ~een stated'i.n the preceding paragraphs, many times it is desirable to use the MPU 11 and the'ACIA 13 'in a system in which the I/0 terminals 17 and 18 may be used'interchangeably. An e*ample of this is where a TTY ~erminal 17 and a CRT terminal 18 are used interchangeably -~n a system. ;' The TTY terminal 17 requires eleven bits o~ serial data at 110 baud. The CRT
terminal 18 requires ten bits of serial data at rates above 300 baud. The ACIA 13 must provide the data ~rom the MPU 11 to the I/0 terminals 17 and 18 and rom the I/0 terminals 17 and'l8 to the MPU 11 at the required data rate 20 and required data format.
The baud rate control 19 may be readily used to vary the baud rate.
This may be done manually or automatically as ma~ be desired. The problem occurs with the data format. The data format must be programmed into the ACIA
13 by the MæU 11. In order to do this the 'MPU 11 must know what type of I/0 terminals 17 and 18 is in the system. This inEormation is provided to the MPU
by utili~ing swltching means 32 to create a "don't care" posltion in a binary address from the ~PU 11 to the AClA 13.
An example o~ this tech~ique is as follows. Assume that a TTY
terminal 17 and a CRT terminal 18 may be used interchangeably. Switching 30 means 32 is placed in the A0 position when the TT~ terminal 17 is in the system and is placed in the Al position ~hen the G~T tenninal 18 is in the system. In this example~ the ~CIA registers are programmed in such a manner that a hexadecimal address 8004 enables the stat~s register 51 and the control : :

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:, register 52, and 8007 enables the receive data register 54 and the transmi~
data register 53. The hexadecimal address is provided'rom the`MP'U ll to the ACIA 13 through signal lines 21-25 which car~y the address ~its AO~A15.
Table I shows the four least sign-i-Elcant bits A0-A3 of the address in binary form.
TABL~ I
A3 A2'Al A0 Address o 1 o o saQ4 0 l 1 0 8006 0 1 l 1 8007 If the switchlng means 32 is în the A0 position then the ACIA receives'only data ~its AO, A2, A3, and A4-Al5. Data bit Al is not received: thus the Al column o Table I is a "don't care" column. An examination of Table I shows that when data bit Al i9 a "don~t care" then the address 8004 i9 ident-lcal to 8006 and the address 8~n5 i9 ldentical to 8007.
When thP MPU 11 addresses the ACIA 13 with a binary address ~006 the ACIA 13 will receive an address identical to the address that would have been received i~ the MPU 11 had addressed the ACIA 13 with a binary address 8004.
The status register 51 ~ill send data to ~he computer means in response to the 8006 address even though it is programmed to answer only to an 8004 address.
The MPU 11 is programmed in such a manner, that when the status register 51 `~
responds to an address oE 8006, the MæU will 'know that a TTY terminal 17 is in the system and ~ill program the ACI~ accordingly.
Table II shows a routine which may be used to perEorm the function descr-lbed in the preceding paragraphs. A complete Eunctional listing of ~he Motorola 6800 microprocessor instructio~ set, from whic'h the routine shown in Table II was developed, 19 g~ven in Table 8.2 at page 312 of`_lcroprocessors `and ~icrocomputers by Branko Soucek.`

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TABL~ II
_ __ 'ACIA'INITIALIZATIO~ ROUTINE
__ Address in Machine Assembler Memor~ Language n~O CE8004 'LDX #$8004 Set Inde~Register on ~CIA
n~3 8603 ~DA A #$03 ~aster Reset AGIA
n~5 A70Q STA A O,X ~ ~-n~7 44 LSR A Program AGX~ With Ol,TT~ Control Word n~8 AlOO STA A O,X
n~A A600 LDA A O,X Check ~or Data at ' 8004 to equal 8006 n~C ~102 CMP A 2,~
n~E 27Q4 BEQ EXIT If equal exit ~-n~10 860~ LDA A #$Q9 Else Program ACIA
with O9,RS232 Con-trol Nord n~l2 A700 STA A O,X
n~l4 EXIT
The purpose of the routine shown in Ta~e lI would be apparent to one skilled in the art of programming microprocessors. Essentially the MPU 11 ~
initially programs the ACIA 13 Eor ~the 11 bit format requlred by TTY t&rminal ~' 17. The MPU 17 then addresses the status and contxol registers 51, 52 of the ACIA 13 with an address oE 8004. The &tatus register 51 will transmit the data it holds to the NPU in response to this address. In this preferred embodiment the data held by the status register 51 will be 02. The MPU stores the data from the status register 51 and addresses the ACIA 13 aith an address of 8006. I~ the switching means 32 is in the AO position, then the status register will again respond. The MPU compares the data received Erom the two addre~ses 8004 and 8006. I~ the data i8 equal, then the MPU leaves the ACIA

programmecl Eor the 11 bit format requlred Eor a T~Y terminal~l7. I~ the data is not equal, then the MPU 11 will kno~ that the switching means 32 is in the Al position corresponding to a CRT terminal 18 and the~MPU 11 will reprogram the ACIA 13 for 10 bit format.
The'invention has been described in terms of the pres~ently preferred embodiment. Reasonable variations and modifications are possible9 by those skilled in the'art, within the"scope of described invention and the appended claims~ Such variations as utili~ing addressing schemes'and ~Ising different ... ~ :

~B3~2 computer systems, interfaces, and I/O terminals are within the scope o~ the inv~ntion .

Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE
IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Apparatus comprising:
a computer means;
a first input/output (I/O) terminal means which requires a first data format;
a first interface means which interfaces said computer means to said first I/O terminal means;
a register means which is an integral part of said first interface means;
means for supplying digital addresses from said computer means to said register means;
means for supplying digital data from said register means to said computer means, said register means being enabled to supply the digital data stored in said register means to said computer means when a first digital address is supplied from said computer means to said register means;
and a switching means, having first and second positions, adapted to receive at least a part of each digital address from said computer means and transfer to said register means a smaller part of the digital address from said computer means than that received by said switching means, in such a manner that at least one digit of the digital address supplied by said com-puter means to said register means is not received by said register means, so that a second digital address supplied by said computer means to said register means, as received by said register means, will be equivalent to said first digital address as received by said register means if said switching means is in said first position and will not be equivalent to said first digital address as received by said register means if said switching means is in said second position; said computer means having means for introducing said first data format into said first interface means when said register means is enabled to supply the digital data stored in said register means to said computer means by said second digital address.

2. Apparatus in accordance with claim l additionally comprising a second I/O terminal means which requires a second data format and which is interfaced to said computer means by said first interface means; said com-puter means having means for introducing said second data format into said first interface means when said switching means is in said second position and said register means is not enabled, to supply the digital data stored in said register means to said computer means by said second digital address.

3. Apparatus in accordance with claim 2 additionally comprising a baud rate control means for controlling the baud rate of said first inter-face means where said first I/O terminal means and said second I/O terminal means require different baud rates.

4. Apparatus in accordance with claim 3 additionally comprising a second interface means for converting the transistor-transistor logic levels of said first interface means to the current or voltage levels required by said first and second I/O terminals.

5. Apparatus in accordance with claim 4 wherein said computer means comprises a microprocessor.

6. A method for providing the proper data format to an interface means which interfaces a computer means to a first I/O terminal means, said interface means having a register means that is enabled to supply the digital data stored in said register means to said computer means when said register means is addressed by a first digital address from said computer means, comprising the steps of:
addressing said register means with a second digital address from said computer means in such a manner that said register means is enabled to supply the digital data stored in said register means to said computer means by said second digital address in the same manner that said register means is enabled to supply the digital data stored in said register means to said computer means by said first digital address when it is desired to introduce the data format required by said first I/O terminal means into said inter-face means and is not enabled to supply the digital data stored in said register means to said computer means by said second digital address when it is not desired to introduce the data format required by said first I/O
terminal means into said interface means; and actuating said computer means to introduce the data format required by said first I/O terminal means into said interface means if said register means is enabled to supply the digital data stored in said register means to said computer means when said second digital address is received by said register means.

7. A method in accordance with claim 6 comprising the additional step of actuating said computer means to introduce the data format required by a second I/O terminal means into said first interface means if said register means is not enabled to supply the digital data stored in said register means to said computer means when said second digital address is received by said register means.

8. A method in accordance with claim 7 comprising the additional step of controlling the baud rate of said first interface means where said first I/O terminal means and said second I/O terminal means require differ-ent baud rates.

9. A method in accordance with claim 8 comprising the additional step of converting the transistor-transistor logic levels of said interface means to the current or voltage levels required by said first and second I/O
terminal means.