CA1105139A

CA1105139A - Charge transfer device having linear differential charge-splitting input

Info

Publication number: CA1105139A
Application number: CA290,564A
Authority: CA
Inventors: Ronald E. Crochiere; Carlo H. Sequin; Michael F. Tompsett
Original assignee: Western Electric Co Inc
Current assignee: AT&T Corp
Priority date: 1976-12-08
Filing date: 1977-11-09
Publication date: 1981-07-14
Also published as: ES464864A1; FR2373856B1; GB1592480A; JPS5371578A; DE2753677A1; FR2373856A1; NL7713544A; BE861538A

Abstract

CHARGE TRANSFER DEVICE HAVING
LINEAR DIFFERENTIAL CHARGE-SPLITTING INPUT

Abstract of the Disclosure A charge transfer device includes two channels and a common input structure. The input structure is operated in a manner to divide a charge packet of signal-independent size into two complementary packets for movement along the two channels. A single-channel embodiment employs a similar input structure.

Description

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_eld of the Invention_ _ _ This invention relates to semiconductor apparatus, and more particularly to charc~e-coupled devices or, generically, charge transfer devices.
Background of the Invention Charge transfer devices (CTD's) are well known in the art. Such a device comprises a semiconductor subs-trate, typically wi-th a single surface channel, -to which an arrangement of electrodes is coupled for defininy a path.
The electrodes are electrically isola-ted from one another and adapted to move charge packets along a sequence of potential wells formed in response -to phase-related signals applied to -the electrodes in sets in a now well-understood manner.
A variety of input structures are known for introducing charge into such devices. Each of these input structures responds to an input signal voltage which is determined with respect to some reference potential. As a consequence, the charge which is developed in the input structure is a func-tion of the applied signal.
A prior art improvement over a single-channel device uses two channels where the output signal is taken as the difference between the outputs of the two channels. By using such a differential mode, the effects of dark current, temperature dependent drift, clock pickup, and even harmonic ~ .
distortions detrimental in single-channel devices, are significantly reduced since they appear as common mode noise signals and are thus cancelled by a difference amplifier employed at the output.
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To reali~e the full benefit of the two-channel ; spprosch,~the charge has to be introduced ln an exactly ~ ~ complementary form 1nto the two transfer channels. In prior ~. ~ ., ~ . : . , 3~
art clevices using two chanllels, -two separate inputs were provided to generate two charge packets independently where -the charges had no fixed relationship with one another.
Further, -the generation of the -two charge packets reyuired amplifier circuits wl-th attending losses in linearity and symmetry as is well known.
Brief Description of -the Invention In accordance wi-th an aspect of the invention there is provided a charge transfer device comprising a layer of semiconductor material in which first charge packe-ts can be moved along a first path from an input portion in response to a succession of localized electric fields, and electrical conductor means including a first set of electrodes coupled to said layer for generating said fields in a manner to move said first charge packets along said first path, wherein ; said input portion includes means for genera-ting signal independent charge packets and means responsive to firs-t and second signals for dividing each of said signal independent charge packets into first and second charge packets, each of ~0 said first packets being llnearly related to the difference between said first and second signals, said first charge packet being positioned for movement along said first path.
The present invention is based on the recognition that the generatlon of a charge packet of signal-independent size at the input of a CTD provides a number of advantages.
~; The advantayes are partlcularly cIear for a two-channel device where a charge packet of signal-independent or fixed si~e is separated into two packets which have a fixed relationship to one another. Since the sum of the charge ~;30 ~packets (QA + QB = QO) is a fixed q~lantity, the common mode signal is suppressed. For a twa-channel device speci:Eically, :
an input structure, in accordance with an embodiment of this ~ - 2 -, 3~
invention, inc~udes a charcJe injection circuit and two input gates to each of which a vo:Ltac3e is applied. The charge packet QO is formecl by conventiorlal techniques in the charge injection circuit precediny the ya-tes. The ya-tes are then operatecl, responsive -to inpu-t siynals, in a manner to develop two charye packets (QA, QB) oE
complementary sizes, the difference between which is determined by -the difference between signal-dependen-t vol-tages applied to the gates. This is to be contrasted with prior art s-tructures where the size of each of the signal charge packets is separately determined a-t the point of injection from a separate source as indicated hereinbefore.
In one specific embodimen-t of such a two-channel device, an input diode, a me-tering elec-trode, and a pair of gates is employed a-t the inpu-t. The metering elec-trode can be operated in the "voltage input" or in -the "charge preset"
mode (see Charge Transfer Devices, by C.H. Sequin and . .
M.F. Tompsett, page 48, Academic Press, 1975) to produce a single charge packet of a fixed si~e in each clock cycle of operation. Each charge packet so generated in subsequently transferred to the signal input region defined by the two gates where the charge packet is spli-t into two packets which depend on the momentary signal voltages applied to the two gates.
In those embodiments of this invention where -the symmetry of the input gates is sufficiently precise, the charge packets which are divided into complementary portions need not be signal independent but can fluctuate from packet to packet as long as common mode noise supression is not important.

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srief Descr.ipt:Lon of tle Dr~lwing FIG. 1 is a c:ross-section diagram of a three-phase semiconductor charge transfer clevice with a generalized input arrangement in accordance with prior art teachinys;
FlG. 2 is a schematic -top view of a two-channel CTD
arrangement wi-th an inpu-t s-truc-ture in accordance wi-th -this invention;
FIGS. 3A, 3B, 3C, and 3D are a cross-sectional view of a portion of the lnput structure of FIG. 2 showing alternative charge division -therein in accordance with this invention;
FIGS. 4~, 4B, and ~C are schematic top views of alternative two-channel CTD arrangements with inputs in accordance with this invention; and, FIG. 5 is a schema-tic -top view of a single-channel arrangement with an input structure in accordance wi-th -this invention.
Detailed Description FIG. 1 shows a generalized prior art CTD
arrangement 10 including a semiconductor layer 11, an insulating coating 12, and an arrangement of electrodes ~1' ~2' ~3 organized in a three-phase arrangement to form a charge packet transfer path i.n the semiconductor layer. The semiconductor layer includes an input porti.on or region 1~
characterized by an input diode ID and an input gate IG for defining a charge pac~e-t in a metering poten-tial well formed under a metering electrode ME. The charge accumulates in the well in response to a signal supplied by an input signal j.
source designated 16 in -the figure. The charge accumulated in response to the signal in each clock cycle is advanced, in a well-known manner, by the provision of "charge transfer" pulses applied to the electrodes in a multiphase ~ ~.
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manner by charge trans:~er pulse cont:rol circuit 17. The charge so transferred passes at 1east one sense output tap indica-ted by arrow 18 and thus appli,es signals to utilization circuit 19. Layer 11 may comprise a surface channel, or a bulk channe:L. In either case, a charge transfer channel is defined in a well-understood manner and layer 11 is taken to include such a channel.
The various sources and circuits may be any such elemen-ts capable of operating in accordance wi-th this invention.
FIG. 1 also shows, speci:Eically, -the semiconduc-tor layer 11 as having superimposed thereon a contoured broken line 20 which depicts, in a well-understood manner, the surface potential in the layer at different positions along the transfer channel. The contour of line 20 is determined by the potential applied to the electrodes of FIG. 1 during one phase of a clock cycle. In the typical situa-tion, like-designated electrodes are interconnec-ted electrically in sets (or series) and circuit 17 applies clock pulses (~1 2n ~2~ and ~3 to the sets in sequence. The pulse pattern on the electrodes determines the peaks and wells of -the contour as shown for one phase and wherein successive pulses cause the contours to move. The (potential) wells store charge packets which are thus moved along the layer 11 in response to the succession of (three-phase) pulses in a well ~, understood manner.
Of course, the amount of charge or -the presence or "absence" of a (p:rescribed) charge in the input portion 14 is determined by a signal applied to an input gate IG during : 30 a given clock cycle as is also well understood. The amount of charge in a potential well during one phase is represented by cross-hatched areas designated 21A, ~ ```' '`' .

3~3 21B,...21s. Area 21A is representecl at the inpu-t to layer 11 and cons~itutes the metering well uncler metering electrode ME. Area 21s is a represen-tative sense outpu-t -tap.
FIG. 2 ls a -top view of a CTD device which also may be represented by the generalized CTD representa-tion o~
FIG. 1 bu-t inclucling an additlonal charge divider inpu-t implementation as will become apparent hereinaf-ter. The figure shows a two-channel arrangement where the channels are designa-ted channel A and channel B for movement of charge packets to the right as viewed. The channels are separated by a channel "divider" (or "stop") area 23 and are preceded by an input portion designated 2~ in the figure.
The input portion is common to -the two channels and is separated therefrom by input gate electrodes GA and GB
associated with channels A and B, respectively.
The input portion of the device includes an input diode ID, an input gate IG and a metering electrode ME. The metering electrode is followed by first and second phase elec-trodes (Pl and ~2 operative in synchronization with the first two phases of the three-phase charge packe-t advance electrodes ~ 2 and (~3 shown for the channels. A channel divider electrode SG separating gate electrodes GA and GB is shown in this particular embodiment.
The me-tering electrode can be operated either in the familiar vol-tage input or in the charge prese-t mode to produce charge packets of a fixed size QO in each clock ; cycle. These chalge packets are subsequently transferred to the complementary signal input consisting of the two gates 30 GA and GB, where each arriving charge pac]cet QO is split into two packets oE slzes QA and QB' respectively, which depend upon the momentary signal voltages VGA and VGB 1, : ~- ;'"'`i : :

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applied to the two g.ltes.
The device is operated such tl~at the two charge packets can equilibrate in the splitting process so that they achieve equal in-ter:Eace potentials before they are separa-ted and -transferred in-to the -two individual channels.
More charge carriers will thus collect ur-der the ga-te which has the higher poten-tial (for an N-channel device) applied to it and which therefore generates a deeper po-tential well underneath. ~s shown below, the charge QA (collected under the gate electrode GA) jS related to the charge QB (collected under GB) by the relationship QA - QB = a (VGA - VGB) provlded that the areas of -the gate electrodes are equal, where "a"
is a signal-independent parameter. This process can be understood more fully by looking at the cross-sectional view taken along line 2-2' of FIG. 2 through the two input gates as depic-ted in FIGS. 3A, 3B, 3C, and 3D. FIG. 3A
shows the structure with no voltages applied. FIG. 3B
shows the potential profiles and charge distributions for the balanced case (VGA = VGBj where the packet QO is split 20 into two equal parts, each representing the zero signal or ~`
reference level.~ FIG. 3C depicts the general unbalanced case where a difference QA-QB is produced by a voltage difference between the two input gates GA and G~ due to different voltages VGA and VGB applied as shown in FIG. 2.
FIG. 3D, finally, illustrates one extreme case of saturation : : (largest useab1e input signal VGA ~ VGB) where the whole charge packet QO is moved to one side and thus to one channel. In order to give a clean saturation behavior, the charge input 19 designed so that the full charge packet 30: QO can be handled by each one of the two individual output .
channels.
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process we refer acJain to FIGS. 2, 3A, 3B, 3C, and 3D. For generality, we drop the requirernent that the -two input gates GA and GB be of equal size. This will allow us to estimate -the effec-t of misalignment errors of the elec-trodes wi-th respect to the channel geome-try.
AE-ter equilibration of -the -two fractional charge packets, the interface potential uncler both input ya-tes will be the same:

~)S = VA+Vo - (VAvo+vo ) = VB-~Vo -- (VE~Vo+vo) where VA = (VGA-VFB) ~ qA/COX
and correspondingly for VB. The structural parame-ter VO = qNAEOs/C x is the same for bo-th gates, where q is electron charge, Eo iS the permittivity of vacuum, ES iS the relative permit-tivity of silicon, NA is the number of acceptors per cubic centimeters, and COX is -the oxide capaci-tance per unit area. It thus follows that VA = VB
and thus CoxVGA + qA CoxVGB + qB' in order that the original equality be satisfied. In the above equation, qA and qB represent charge densities under the respective electrodes GA and GB. The size of the actual charge packets is then obtained by multiplying with the respective gate electrode areas AA and AB. The sum of the two charge packets is given by QO, and it then holds that A A B B A B O
and it follows that for < QA ~ QO
AAQO-AAABCOX(VGA VGB) QA = AqA = AA+A~
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Since the zero reEerellce siynal is represente(l by Qo/2~ the actual signal in one of -the two indiv:idual output channels is QA QO/ 2 AA~AB AA-~AB ox( G~ GB) -Similarly, Q ~ Q / = 2 AtAB ~ AA~B C (VGA-VGB) .

Thus:

QA QB Q AA+AB AA+AB ox ( GA GB) with QA ~ QB

For the case of precise symmetry of alignmen-ts, where the -two yate elec-trocle areas are equal (AA=AB=AG), the above results reduce to:

QA = Qo/2 ~ 2 AGCox(VGA GB)' QB = Qo/2 + 2 AGCox(VGA VGB)' QA ~ QB = -AGCox(vGA VGB)' or QA ~ QB a(VGA GB
Again, with QA~QB = QO~ where a =AGCoX, a signal-independent structural parameter. In the case of precise symmetry of alignments, the~ foregoing equations show -that the charge 20 packets QA and QB are precisely complementary and that ~ the charge packet difference (QA-QB) is linearly ;~ porportional -to the input signal difference voltage (VGA-VGB) as desired. Moreover, even in the case of nonalignment (AA and AB no-t equal). The equations show that the charge~packet. difference~ (QA-QB) wlll still be llnearly related to the input signal voltage dif~erence (VGA-VGB) with an (additive) offset that is signal independent, and this offset will be the same for all subsequent packets so ---- 9 ~ :, : ~Y

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lony as QO i.s kept Lhe same fc)r all these packets. 'I.'hus, it is important that QO be the same flxed value for all packets in -the case o:E nonalignment (AA and AB no-t equa]).
For the perfectly symmetrical case, the difference mode signal charge QAQO/2 does not depend on QO.
Therefore, if this input is used wi-th a differential charge-coupled delay line wi-th two separa-te channels carrying complementary signals and wi-th a difference '~
amplifier at the output, fluctuations in the size of QO will cancel.
The above analysis relies on the fact that -the -two partial charge packets QA and QB reach a common interface potential just before they are completely separated.
FIGS. 4A, 4B, and 4C illustrate several structures in which a common interface potential can be reached prior to separation. The dotted lines in the figures indicate the locations of two relatively narrow charge transfer channels separated by channel stop diffusion (implant or thick oxide regions as is well known) growing out of a single, xelatively wide input channel.. The implementation shown in FIG. 4A, is operated in a three-phase manner, with two input gates, GA and GB, serving the function of dc electrodes held in the voltage range between the low signal pulse potential and half the peak signal pulse potential. The electrodes are made at least twice the lenyth (taken along :.
direction of charge movement) of a regular transfer electrode r so that they can accommodate a full charge packet QO within that limited potential range. Equilibration takes place when phase ~2 turns off and the charge packet QO is pushed 30 under the input gates. Charge continues to equilibrate around ,.
the channel divider area through the region under electrode ~2 adjacent gates GA and GB until the interface potential under i`
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phase ~P2 Ealls below the common interEace potential produced by -the split charge packe-t under the input ya-tes.
Near turnoff (when the in-terface potential under the phase two elec-trode ~2 is almost equal to -the potential under gates GA and GB), the equilibration path between the g -two wells defined by gates GA and GB is of low conductivity and, in addition,may be poorly defined due to spatial variations of the interface potential. Furthermore, since the discharge of the large area under phase two electrode ~2 10 occurs simultaneously with the equilibra-tion process, this elec-trode is not turned off too quickly lest proper equilibration be forestalled by -the dynamics of the discharge under -the influence of -the electrical fringe fields at the edges of the ~2 electrode.
Alternatively, the beginning of the channel divider is placed further to the right under -the input gates themselves, and the remaining uncovered gap between the gates is bridged by a self-aligned diode as shown in p FIG. 4B. The self-aligned diode is formed during the normal 20 processing sequence by a diffusion step which employs the gates as a mask. In this arrangement, charge can equilibrate during the whole time that it resides under the ~ input gates,~ and -the dynamics of the discharge now are ; helpful since they -tend to separate the two partial charge ; ~ packets with -time constants much shorter than the equilibration~ time constants between the two wells. For a fixed operating rate, the channel width, the electrode length, and the dimensions of the passage through the self-aligned diode can be properly chosen to obtain the right ; :
30 time constants in accordance wlth well-understood ~-considerations.
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Alterll~tively, a special. separation gate SG is i.ntroduced, between two chanllel stop recJiOns 23' and 23", to replace the self-alicJned diode as il~dicated in E'IG. ~C.
During the first part of phase ~3, this gate is pulsed to allow equilibration of the interface po-tentials under the two input ~ates. Then, before the char~e star-ts to transfer to phase electrode ~1' the gate is turned off resul-ting in a complete separation of the two charge packets.
The noise introduced by this charye-spli-tting input scheme does not depend on -the noise associated with the genera-tion of the charge packet QO as long as -this input is used in conjunction with differen-tial charge detection. The noise produced in the splitting process can be estima-ted by assuming tha-t the variance of the interface po-ten-tial difference under the two input gates is given by nkT/C where the parameter, which depends on the mechanism of equilibration, lies .in the interval Q.5 < ~ < 1Ø The value for C to be used in the above expression is the capaci-tance resulting from the series connection of the two metering well capacitances, k is Boltzmann's constant and T
is absolute temperature. If the capacitance under each of the input gates is CG, the rms noise charge observed differentially between the two channels will be 2~kT/CG.
This value is thus, in principle, the same as that calculated Eor a differential CCD of the same i.nput dimensions with two separate charge inputs which equillbrate independentl~ with a voltage source. Thls means that the obtainable signal-to-noise charge ratios with this new differential input scheme are baslcally the same as for a .. ::
30 single-channel approach using the same total channel width. .~:
The input arrangement of FIG. 2 is particularly suited for differential char~e-coupled delay lines, - 12 ~

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especia~ i.f balanced input signa:Ls are avai:lable, say, frorn a two-wire l.irle or from a coup:LincJ transformer. In such a case, t:he input circuit becornes cornpletely symmetrical. I.E only a single-ended input signal, wh:ich is referenced to systems ground, is available, the second inpu-t gate is held at a suitable dc reference potential which should be abou-t one-fourth of the peak signal pulse potential for the -three-phase implementations of FIG. 2.
The differential nature oE this input scheme then eliminates the need to generate a special complementary input signal for -the second channel.
The charge-splitting input in accordance with -this invention is useful also as an input for a single-channel device when -the input signals are available in a balanced format. The partial charge packet QB injected into one channel can simply be discarded into a reverse-biased drain diode. However, for a single-channel approach, the layout can readily be rearranged as shown in E'IG. 5 so that equilibration between the two inpu-t gates (GA and GB) can take place across the whole channel width, thus permitting high speed operation. In this form, the charge-splitting input ~using the separation gate SG of FIG. 5) combines the advantages of the voltage lnput and oE the charge preset input arrangements while avoiding some of their problems.
: Of the former, it has retained the speed and the well-~: : defined sampling point given by the turnoff of the separatlon gate without the nonlinearities arising from the ~ :
~; varying depletion capacitance. It thus avoids the well-understood problems connected with the undesirably changing sampIing point. which is especially troublesome for signal frequencies near the Nyquist rate which result from the ~ - 13 -::

unidirectional equilibrclt:iorl process in the charye p~ese-t method. The linearity of the new input exceeds the performance of -the charge preset method at high fre~uencies, and the sensitivlty to threshold voltage difEerences is strongly reduced since the -two inpu-t gates are formed in the same electrode level.
Considering the splitting noise ahove, which is fully correlated in both channels, the signal-to-noise ra-tio would not change by taking the outpu-t signal from only one of the two channels. However, in the single-channel approach, the noise associated with QO does not cancel and the variances of the two noise sources have to be added. It turns out that the overall signal-to-noise ratio is ayain comparable to the one obtainable in a single-channel device of equal channel width using one of the conventional inputs.
Whether the charge--splitting input is used with a single or with differential channels and wi-th single-sided or with balanced input signals, the transfer channels are never completely flooded with charge, even with extreme voltages applied to the inpu-t ga-tes, since the charge input limits the amount of charge available in any one clock cycle to QO. On the o-ther hand, the common mode signal range has its limits. When both input gates are biased below the low resting potential of the pulsed transfer electrodes, no charge is injected into any of the channels. The charge that cannot be inserted into the transfer channels can be made to flow bach to the metering well under metering electrode ME rather than being injected into the substrate, if the ~1 transfer electrode following the metering well is 30 held at a potentlal somewhat above -the resting potential. 1-:

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At the other extreme, very high potellt:Lals on the inpu-t gates can gellerate deep potential wells which are unable to empty their carriers into the transfer channels. When the potential is subsequently reduced, -these carriers can add up to a charge packet larger than ~O and, depending on the charge-handling capabili-ty of the -transfer channel, some of this charge may be in~ected into -the substra-te. To avoid overfilled or completely empty charge packets, either of which would impair the charge transfer in the signal channels, the inpu-t signals should be limited accordingly.
This corresponds to -the precau-tions -that have to be taken in prior art devices.
Although several possible implementations of the differential input scheme have been discussed in the context oE three-phase devices, it should be clear tha-t the technique applies equally well to four-phase devices and, with some precautions, to two-phase devices with directional electrodes. For example, if -the input gates themselves are , directional electrodes, then the arrangement represen-ted in FIG. ~A does not work since charge cannot equilibrate across the barrier part of the input gates. The arrangement . . .
illustrated ln FIGS. 4B and ~C, however, work, provided that the equilibration path connects the storage parts of the input gates. L
Implementations using more than one electrode level (i.e., polysilicon I or polysilicon II) are most suitable for the realization of the input structure with the extra separation gate. The gate, in this instance, is placed in ~i ; the second electrode level to minimize the active area of this gate and to provide easy accessibility. A symmetrical differential~input using the separation gate approach has : , E ~ 3~

been implemented with two levels of polysilicon in the context of a chip containing several clifferen-tial charge-coupled delay lines.
A device with a charge-splitting inpu-t was macle with the electrode layout indicated in FIG. ~C and included an on-chip differential amplifier (not shown) with polysilicon I and polysilicon II capaci-tors to con-trol the overall gain of the device and for frequency compensation of the amplifier. A four-phase transfer electrode structure with two levels oE polysilicon was used to provide the delay elements normal to CTDs. Transfer pulses and pulses required for the input and output circuits were provided by ~ a line of logic cells (not shown) also provided on the chip.
; The chip operated with two voltages, +12 V and -5 V; all intermediate voltages required were generated by on-chip voltage dividers.
The chips were fabricated using an n-channel process with self-aligned thick field oxide over an ion implanted channel-stopping region, two levels of 20 polysilicon, an ion implant to tailor the -threshold under one of the polysilicon levels, and a self-aligned diffusion to form the sources and drains all in accordance with well-understood techniques.
In operation, charge packets of a fixed size were b generated in each clock cycle in a metering well using the normal "fill and spill" (- charge preset) method. These packets were then moved subsequently to the actual signal input, i.e., into two potential wells generated under a split electrode which were connected via a conductlng 30 channel. These t~wo poten-tial wells are created by ~ -electrodes in polysilicon level I to which the input ::
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vo:Ltages were applied. 'l'he conduc-tincJ channel was created by an electrode in polysilicon level II which allows, at first, the charge packets under -the -two electrodes to equilibrate so that the charge difEerence between them was a linear functioll of -the voltage difference on -the electrodes.
Subsequently, this electrode was -turned off to separate the two partial charge packets.
In -this embodimen-t, the dimension of the gates GA, GB and SG were 40 ~m ~ lO0 ~m and 7 x 7 ~m. The dimensions of the transfer electrodes were 9 and 6 by lO0 ~m.
Al-though the invention has been described in terms of an input region adapted to divide a given charge into two packets, it is specifically contemplated herein to encompass input regions adapted to divide charge into -three or more packets, or in-to delibrately unequal packe-ts. In this last instance, equal or unequal signal voltages are contemplated.
What has been described is considered merely illustrative of the principles of this invention.
Therefore, various modifications can be devised by those skilled in the art within the spirit and scope of the invention as encompassed by the following claims.

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A charge transfer device comprising a layer of semiconductor material in which first charge packets can be moved along a first path from an input portion in response to a succession of localized electric fields, and electrical conductor means including a first set of electrodes coupled to said layer for generating said fields in a manner to move said first charge packets along said first path, wherein said input portion includes means for generating signal independent charge packets and means responsive to first and second signals for dividing each of said signal independent charge packets into first and second charge packets, each of said first packets being linearly related to the difference between said first and second signals, said first charge packet being positioned for movement along said first path.

2. A charge transfer device in accordance with claim 1 wherein said electrical conductor means also includes a second set of electrodes coupled to said layer for generating said fields in a manner to move said second charge packets along a second path and each of said second charge packets is positioned for movement along said second path.

3. A charge transfer device in accordance with claim 2 wherein said means for generating said first charge packet includes an input diode and a metering electrode for defining a metering well in said layer.

4. A charge transfer device in accordance with claim 3 wherein said means for dividing includes first and second input gates proximate said layer and responsive to first and second signals, respectively, for separating said signal independent charge packet into first and second charge packets.

5. A charge transfer device in accordance with claim 4 wherein said means for dividing also includes a gate electrode.

6. A charge transfer device in accordance with claim 4 wherein said means for dividing also includes a diode.

7. A charge transfer device including a layer of semiconductor material in which first and second charge packets can be moved from an input region along first and second paths in response to successions of localized electric fields, electrical conductor means including first and second sets of electrodes coupled to said layer for providing said localized electric fields for moving said first and second charge packets along said first and second paths, respectively, means for generating a charge in said input region and means responsive to an input gate signal for dividing said charge into said first and second charge packets in accordance with said input gate signal.

8. A charge transfer device in accordance with claim 7 wherein said last-mentioned means comprises electrodes of substantially identical geometries.

9. A charge transfer device in accordance with claim 7 wherein said charge in said input region is independent of said signals.