CA1102926A - Semiconductor device having improved schottky-barrier junction - Google Patents
Semiconductor device having improved schottky-barrier junctionInfo
- Publication number
- CA1102926A CA1102926A CA309,646A CA309646A CA1102926A CA 1102926 A CA1102926 A CA 1102926A CA 309646 A CA309646 A CA 309646A CA 1102926 A CA1102926 A CA 1102926A
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- Prior art keywords
- layer
- metal
- semiconductor material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 98
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 40
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052737 gold Inorganic materials 0.000 claims abstract description 36
- 239000010931 gold Substances 0.000 claims abstract description 36
- 239000010936 titanium Substances 0.000 claims abstract description 33
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 27
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 19
- 239000000956 alloy Substances 0.000 claims abstract description 19
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 16
- 239000003870 refractory metal Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000000374 eutectic mixture Substances 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 43
- 229910052697 platinum Inorganic materials 0.000 abstract description 22
- 238000005275 alloying Methods 0.000 abstract description 6
- 238000001465 metallisation Methods 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 11
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 7
- 239000002800 charge carrier Substances 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910000927 Ge alloy Inorganic materials 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 241000234282 Allium Species 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
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- 230000009850 completed effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- VKYKSIONXSXAKP-UHFFFAOYSA-N hexamethylenetetramine Chemical compound C1N(C2)CN3CN1CN2C3 VKYKSIONXSXAKP-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28581—Deposition of Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/864—Transit-time diodes, e.g. IMPATT, TRAPATT diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Abstract A semiconductor device having an improved non-diffusive Schottky-barrier junction and metallization layers and method for producing the same. A thin layer of a Schottky-barrier forming metal such as platinum is sputter deposited upon a hot gallium arsenide substrate impact alloying a portion of the Schottky-barrier forming metal with the gallium arsenide material. A refractive metal such as titanium is then sputtered above the Schottky-barrier forming layer at a power level sufficient to alloy the remaining Schottky-barrier forming metal with the refractive metal. A highly conductive layer such as gold is then sputter deposited over the refractive layer to provide ohmic contact. The invention may be used to particular advantage in microwave diode and field effect transistor devices.
Description
s~
Background of the Invention 1. Field of the Invention.
The invention pertains to semiconductor devices having a Schottky-barrier contact and in particular to such devices constructed for operation in the mlcrowave frequency ranges in which a stable contact is desired.
Background of the Invention 1. Field of the Invention.
The invention pertains to semiconductor devices having a Schottky-barrier contact and in particular to such devices constructed for operation in the mlcrowave frequency ranges in which a stable contact is desired.
2. Description of the Prior Art.
In prior art microwave diodes and field effect transistors employing Schottky-barrier contacts, the contact was ordinarily formed by a layer of platinum or other Schottky-barrier forming metal deposited upon a semiconductor surface in a desired pattern with a layer of highly conductive metal such as gold deposited over the platinum layer to provide external contact. The platinum layer ~as made thick enough to prevent atoms of the gold layer from migrating through pinholes or grain boundaries in the platinum layer into the semiconductor material and, by their presence in the semiconductor material~ degrading the performance of the device. Unfortunately, the excess platinum over that hich was required to form the Schottky-barrier junction allowed for continuing alloying between the platinum and semiconductor material during high temperature conditioning and operation - o the device. The position of the Schottky barrier effectively moved further into the semiconductor material as the alloying process continued. With many devices such as Read-type Il~lPATT
diodes, such movement is quite undesirable as the position of the Schottky-barrier junction determines one boundary of the avalanche or charge carrier creation region. In some configurations of such devices, the frequency of operation of the device was changed as the junction moved.
~ 2 ~
Summ~r~ of the Invention . .
~ ccordingly, it is an object of the present invention to provide a semiconductor device having a position-stable Schott~y barrier junction.
r~lso, it is an object of the present invention to provide such a semiconductor device in whic~ atoms of the contact layer are prevented from migrating into the semiconductor material.
Furthermore, it is an object of the present invention to provide such a device in which only a minimal thic~ness of Schottky-barrier forming metal is required.
These, as well as other objects of the invention, may be met by providing the combination of a body of semiconductor material, a layer comprising an alloy of the semiconductor material and a first metal upon at least portions of a surface of the body of semiconductor material, and a layer of a second metal disposed upon the alloy layer. The first metal is of a type which will form a Schottky-barrier junction wi~h the semiconductor material. A third metal layer may be disposed upon the second metal layer. Preferably, the metal of the second layer is a refractive metal such as titanium, tungsten or hafnium, while that of the third is highly conductive. The body of semlconductor material has a plurality of layers of the - same type of semiconductor material with at least some of the layers being of different conductivity.
Objects of the invention may also be met by providing the combination of semiconductor material, a layer of al~oy of the same semiconductor material and a first metal disposed upon at least portions of a surface of the body of semiconductor material, a layer comprising an alloy of the first metal and a second metal disposed upon the la/er of semiconductor material on the first ~z~
metal, and a layer of the second metal disposed upon the layer comprising an alloy of the first metal and second metal. ~he first metal is again preferably of t~e type ~hich forms a Schottky-barrier junction ~ith the chosen semiconductor material.
~ layer of third metal disposed upon the second metal layer mav also be provided. As before, the second metal is preferably refractive, t~hile the third metal is highly conductive.
Still fuTther, objects of the invention may be met by a semiconductor diode comprising the combination of a body of gallium arsenide semiconductor material, a layer consis~ing of an alloy of platinum and gallium arsenide disposed upon at least a portion of the surface of the body of gallium arsenide se~niconductor material, a layer consisting of an alloy of platinum and titanium, and a layer of gold disposed upon the layer of titanium. The body of gallium arsenide semiconductor material may have a doping profile for an IMPATT diode, or, more specifically, for a Read-type I~IPATT diode. The preferred thick-ness of the platinum layer is in the range of 100 to 300 A ~-hile the preferred thickness of the titanlum layer is in the range of 1000 to 2000 A.
A field effect transistor device may be constructed in accordance uith the teachlngs ~of the invention by providing a body of gallium arsenide semiconductor material having a first contact upon the body of gallium arsenide material comprising a layer consisting of an alloy of platinum and gallium arsenide disposed upon predetermined portions of the surface of the body of gallium arsenide semiconductor mateTial, a layer consisting of platinum and titanium disposed upon the layer of alloy of platinum and gallium arsenide, a layer of titanium disposed upon the alloy layer of platinum and titanium and a layer of gold
In prior art microwave diodes and field effect transistors employing Schottky-barrier contacts, the contact was ordinarily formed by a layer of platinum or other Schottky-barrier forming metal deposited upon a semiconductor surface in a desired pattern with a layer of highly conductive metal such as gold deposited over the platinum layer to provide external contact. The platinum layer ~as made thick enough to prevent atoms of the gold layer from migrating through pinholes or grain boundaries in the platinum layer into the semiconductor material and, by their presence in the semiconductor material~ degrading the performance of the device. Unfortunately, the excess platinum over that hich was required to form the Schottky-barrier junction allowed for continuing alloying between the platinum and semiconductor material during high temperature conditioning and operation - o the device. The position of the Schottky barrier effectively moved further into the semiconductor material as the alloying process continued. With many devices such as Read-type Il~lPATT
diodes, such movement is quite undesirable as the position of the Schottky-barrier junction determines one boundary of the avalanche or charge carrier creation region. In some configurations of such devices, the frequency of operation of the device was changed as the junction moved.
~ 2 ~
Summ~r~ of the Invention . .
~ ccordingly, it is an object of the present invention to provide a semiconductor device having a position-stable Schott~y barrier junction.
r~lso, it is an object of the present invention to provide such a semiconductor device in whic~ atoms of the contact layer are prevented from migrating into the semiconductor material.
Furthermore, it is an object of the present invention to provide such a device in which only a minimal thic~ness of Schottky-barrier forming metal is required.
These, as well as other objects of the invention, may be met by providing the combination of a body of semiconductor material, a layer comprising an alloy of the semiconductor material and a first metal upon at least portions of a surface of the body of semiconductor material, and a layer of a second metal disposed upon the alloy layer. The first metal is of a type which will form a Schottky-barrier junction wi~h the semiconductor material. A third metal layer may be disposed upon the second metal layer. Preferably, the metal of the second layer is a refractive metal such as titanium, tungsten or hafnium, while that of the third is highly conductive. The body of semlconductor material has a plurality of layers of the - same type of semiconductor material with at least some of the layers being of different conductivity.
Objects of the invention may also be met by providing the combination of semiconductor material, a layer of al~oy of the same semiconductor material and a first metal disposed upon at least portions of a surface of the body of semiconductor material, a layer comprising an alloy of the first metal and a second metal disposed upon the la/er of semiconductor material on the first ~z~
metal, and a layer of the second metal disposed upon the layer comprising an alloy of the first metal and second metal. ~he first metal is again preferably of t~e type ~hich forms a Schottky-barrier junction ~ith the chosen semiconductor material.
~ layer of third metal disposed upon the second metal layer mav also be provided. As before, the second metal is preferably refractive, t~hile the third metal is highly conductive.
Still fuTther, objects of the invention may be met by a semiconductor diode comprising the combination of a body of gallium arsenide semiconductor material, a layer consis~ing of an alloy of platinum and gallium arsenide disposed upon at least a portion of the surface of the body of gallium arsenide se~niconductor material, a layer consisting of an alloy of platinum and titanium, and a layer of gold disposed upon the layer of titanium. The body of gallium arsenide semiconductor material may have a doping profile for an IMPATT diode, or, more specifically, for a Read-type I~IPATT diode. The preferred thick-ness of the platinum layer is in the range of 100 to 300 A ~-hile the preferred thickness of the titanlum layer is in the range of 1000 to 2000 A.
A field effect transistor device may be constructed in accordance uith the teachlngs ~of the invention by providing a body of gallium arsenide semiconductor material having a first contact upon the body of gallium arsenide material comprising a layer consisting of an alloy of platinum and gallium arsenide disposed upon predetermined portions of the surface of the body of gallium arsenide semiconductor mateTial, a layer consisting of platinum and titanium disposed upon the layer of alloy of platinum and gallium arsenide, a layer of titanium disposed upon the alloy layer of platinum and titanium and a layer of gold
-3-disposed upon the layer of titanium and further having second and third contacts upon the body o~ gallium arsenide semi-conductor materlal, each of which comprises a layer of non-Schottky barrier-forming material. The layer of non-Schottky barrier-forming metal may be selected from the group consisting of a eutectic mi~ture of gold and germanium and a eutectic mi~ture of gold and nickel. The first contact is preferably located between the second and third contacts. A plurality of each of the first, second and third contacts may be provided in 1~ a multi-transistor composite device.
The invention may also be practiced by the method comprising the steps of providing a body of semiconductor material, sputter-ing a Schottky-barrier forming metal upon at least a portion of the surface of the body of semiconductor material at a sputtering power level sufficient to cause alloying between a portion of the semiconductor material and at least a portion of the sputtered Schottky-barrier forming metal, sputtering a layer of a refractory metal over the sputtered Schottky-barrier forming metal, and sputtering a layer of highly conductive metal over the layer of refractory metal. The body of the semiconductor material should be heated~to a temperature in the range of 300C
to 350~C prior to sputtering the Schottky-barrier forming metal.
The refractory metal should be sputtered at a level sufficient to cause alloying between at least portions of the Schottky-barrier forming metal not alloyed with the semiconductor material and a portion of the layer of re-fractory material. The semi-conductor material in preferred embodiments comprises gallium arsenide, while the Schottky-barrier -forming metal comprises platinum. The refractory metal may be titanium while the highly conductive metal may be gold.
,. : :
The invention may further be practiced by the method comprising the steps of providing a body of gallium arsenide semiconductor material, heating the body of semiconductor ma-terial to a temperature ~ithin the range of 300C to 350C, sputtering a layer of platinum upon a first surface of said body in predetermined locations at a sputtering po~er level in 0.5 to 2.7 watts/cm2 with a preferred operating point of 0.~ watts/cm2 to a thickness in the range of 100 to 300 A, cooling the body .o a temperature below 40C, sputtering a layer of titanium over the layer of platinum at a sputtering power level in the range of 1.4 to 4.4 watts/cm2 with a preferred operating point of 2.7 watts/cm2 to a thickness in the range of 1000 to 2000 A, cooling the body to a temperature of approximately 30C, and sputtering a layer of gold over the layer of titanium. A layer of gold-germanium alloy may be then sputtered upon a second section or upon a second portion of the first surface or upon predetermined portions of a second surface of the semiconductor material body with a layer of gold deposited over the gold-germanium alloy layer. Portions of the layer of gold-germanium alloy and underlying portions of the semiconductor material may then be etched away leaving thè remaining portion of the layer of gold-germanium alloy and of the body of semlconductor material in the form of mesas underlying the discs formed from the gold layer.
A heat sink may then be coupled both thermally and electrically to the gold discs.
In accordance with the present invention there is pro-vided a semiconductor device comprising in combination a body of semiconductor material; a first layer comprising an alloy of said semiconductor material and a first metal upon at least por-tions of a surface of said body of semiconductor material; and a second layer comprising an alloy of the first metal and a re-fractory metal disposed upon said first alloy layer.
In accordance with the present invention there is also provided a semiconductor d.iode device comprising in combination a ~ody of gallium arsenide semiconductor material; a layer con-sisting of an alloy of platinum and gallium arsenide disposed upon at least a portion of a surface of said body of gallium arsenide semiconductor material; a layer consisting of an alloy of platinum and titanium; a layer consisting of titanium dis-posed on the layer consisting of an alloy of platinum and titan-ium; and a layer of gold disposed upon said layer of titanium.
In accordance with the present invention there is also provided a device comprising in combination a body of gallium arsenide semiconductor material; a first contact upon said body of gallium arsenide semiconductor material comprising: a layer consisting of an alloy of platinum and gallium arsenide disposed upon a sur~ace of said body of gallium arsenide semiconductor material; a layer consis:ting of an alloy of pla~inum and titanium disposed upon said layer consisting of an alloy of platinumand gal-lium arsenide; a layer of titanium disposed upon said layer con sisting of an alloy of platinum and titanium; and a layer of gold disposed upon said layer of titanium; and second and third con-tacts upon said body of ~allium arsenide semiconductor material, each of said second and third contacts comprising: a layer of 3a non-Schottky barrier formin~ conducti~e material; and a layer of gold disposed upon said layer of non-Schottky barrier forming metal.
- 5a -~' z~
Brief Description of the Drawings Figures 1-4 are a series of cross-sectional views showing steps in the construction of a semiconductor device in accordance with the invention;
Figure 5 is a top view of the device as shown in Figure 1~;
Figure 6 is a cross-sectional view from a comple-ted packaged de-vice in accordance with the invention;
Figure 7 is a cross-sectional view showing steps in a dicing opera-tion in accordance with the invention;
Figure 8 shows a cross-sectional view of a spray-etching operation as used in the dicing operation of the invention;
Figure 9 is a graph showing a preferred doping density profile for the semiconductor material used with the invention; and Figure 10 is a graph showing an alternative preferred doping den-sity profile for the semiconductor material used with the invention.
Description of the Preferred Embodimen-ts Construction of semiconductor devices in accordance with the teach-ings of the present invention will be initially described in conjunction with the cross-sectional views of Figures 1-~. Referring first to Figure 1, there is shown in cross-section a layer of substrate of gallium arsenide semiconduc-tor diode material 10. Diode material 10 may have one of many different dop-ing density profiles depending -upon the particular application at hand. For example, diode material 10 may have the doping profile of a single-drift ; region IMPATT avalanche diode. A double-drift region IMPATT avalanche diode doping profile may also be used to particular advantage with the invention.
Referring momentarily to the graph of Figure 9, the preferred dop-ing profile of the double-drift IMPATT avalanche diode is illustrated. The material is formed in four regions, two of them being doped with an ~- or negative-type dopant while the other two are doped with a P- or positive-type dopant. A diode junction is formed substantially at the center of the mate-rial between the P and ~ moderately doped layers. Avalanching of charge .' .
~z~
carriers takes pla~e on either side of the diode junction within a portion both the P and N layers. The positive and negative charge carriers gener-ated by avalanching are pulled by an electric field outward -toward the P++
and N++ heavily doped region producing a time delay between tne time of gen-eration of the carriers near the diode junction and the time they reach the heavily-doped region. This time delay corresponds to an 180 phase shift between input and output signals and a diode circuit. The charge carriers in both the P and N regions, upon reaching the P+-~ and N++ regions respec-tively, recombine producing a conduction current in the output circuitry. A
particular diode device used with the invention which has been found to func-tion well with an N doping density of approximately 1.5 x 10 6/cm , a doping density in the N++ region of 2 x 10 /cm3, a density of 1.3 x 10 /cm3 in the P region and a doping density of approximately 10 ~/cm3 in the P++ region.
The ~ layer may have a width in the range of 3.5 to 4.5 microns depending upon the frequency of operation desired. For the same range of frequencies, the P region may have a width in the range of 3.0 to 3.5 microns. Wid-ths of 5.0 to 8.o microns for the N++ layer and approximately 1.0 micron for the P++ layer have been found to function adequately.
Most of the heat generated within the material having the doping density profile shown in Figure 9 is produced in the avalanche regions adja-cent the diode junction in the center of the device. The maximum amount of power which can be handled with such a device is, of course, dependent upon the junction temperature. The junction temperature is in turn dependent upon the rate at which heat may be extracted from the device. Since with the double-drift structure it is not possible to place a heat sink lmmediately adjacent the junction because of the presence of active material extending for appreciable distances on both sides of the junction, heat removal has been a serious problem severely limiting the maximum power at which such devices may be employed.
Referring now to Figure 10, there is shown a graph of a single-.
, '. ''' ., ... ',, ,, ', .' : .
drift Read-type IMPATT diode with which the invention may also be used to advantage. An avalanche region is formed with an l\l-type semiconductor rnate-rial adjacent a rnetal layer suitable for forming a Schottky-barrier junction.
A layer of pla-tinum may be used with gallium arsenide semiconductor material to form such a junction. A thin doping spike of heavily doped semiconductor material terminates the avalanche region and confines the avalanche of charge carriers strictly between the layer of Schottky-barrier forming metal and the doping spike. The charge carriers produced within the avalanche region are pulled through the drift region of moderately-doped material by the ex-ternally applied electric field. Upon reaching the termination region, the cha-rge car-riers recombine forming a conduction current which flows in the external cir-cuitry. A two-layered heavily-doped termination region may be used with the layer immediately adjacen-t the drift region being less heavily doped to pre-vent carrier injection from defects at the interface between the drift region and termination region and the consequent generation of an unwanted reverse current. As in the previously described double-drift avalanche diode, heat removal is also a severe problem with this type of device.
Referring again to Figure 1, -the steps in the construction of a de-vice in accordance with the teachings of the present invention will be dis-cussed in further detail. For use with diode material having a doping densityin accordance with that specified in Figure 10, a three-layer metallization pattern is deposited over one surface of diode material 10 with a layer of Schottky-barrier forming metal in contact with the surface of diode material 10. For the case of the double-drift structure shown in Figure 10, the high-ly doped P++ layer may be omitted as the three-layer metallization described will form a good ohmic contac-t with R-type gallium arsenide material. Also, with the double-drift IMPATT avalanche diode specified in Figure 9, the three-layer metallization may be replaced, for example, by some other metal-lization system. With the embodiment shown in Figure 1, first a layer of platinum 11 is sputtered upon the surface of gallium-arsenide diode material ~ .~,., .. ', , ' 2~
Upon platinum layer 1] is then sputtered layer 12. Titaniwn is the preferred material although tungsten, hafnium, or other refractory metals may be used as well for layer 12. Next, gold layer 13 is sputtered over titanium layer 12. Highly conductive gold layer 13 is sputter deposited upon titanium layer 12 and forms the lower contact to the diode.
In accordance with one aspect of the invention, a particularly ad-vantageous sputtering process is used which results in a device in which the gold layer is prevented from diffusing through the platinum layer into diode material 10 and adversely affecting some of the electrical properties of the material. In accordance with the invention, diode material 10 is first heat-ed to a temperature in -the range of 300 to 350 C with 330 C being a preferred operating point. Platinum lay-er 11 is then sputtered upon the surface of diode material 10 with a sputtering power in the range of 0.5 to 2.7 watts/
cm with a preferred operating point of o.8 watts/cm to a preferred thick-ness in the range of 100 to 300A. A thickness of 200A has been found to function well. During this initial sputtering operation, a portion of plat-inum layer 11 reacts with the gallium arsenide material forming an alloy therewith. Diode material 10 is then cooled to a temperature in the range of 20 to 40C with 30C being a preferred operating point, and a layer 12 of titanium having a thickness in the range of 1000~ to 2000~ is sputtered over -platinum layer 11 at a relatively high sputtering power level in the pre-ferred range of 1.4 to 4.4 watts/cm with a preferred operating point of 2.7 watts/cm . The relatively high -titanium power level causes impact alloying between the remaining platinum and the titanium material forming a compound which reacts chemically much more slowly with gallium arsenide than does pure platinum. Moreover, atoms of gold layer 13 are not able to migrate through the barrier thus formed. Still further, it has unexpectedly been found that diode deuices constructed in accordance with the above-described sputtering process exhibit substantially lower noise measures than for diodes having an ordinary Schottky-barrier contact with the gold layer immediately adjacent . . , the Schottky-~arrier forming me-tal.
Referring nex-t to Figure 2, a layer of gold-germanium eutectic alloy is evaporated upon the surface of gallium arsenide diode material 10 opposite that upon which the p]atinum-titanium-gold layers were deposited.
This surface corresponds to the outer side of -the termination region of a device having a profile shown in Figure 10. Atop gold-germanium layer 14 is pla,ted gold contact layer 15. Similarly, gold contact layer 16 is plated above previously deposited gold layer 13.
Next, as shown in the view of Figure 3 gold-contact layer 15 is masked and chemically e-tched away in predetermined locations using well-known photoresist techniques -to leave a plurality of circular gold contacts 17 atop positions at which diode mesas are to be formed. Ordinarily, many more con-tacts could be formed upon a single semiconductor wafer than are herein shown. For large-scale production, many hundreds of such contacts could be formed upon one wafer then the diode mesa devices diced apart singly or in groups as desired.
Next, as illustrated in the view of Figure 4, gold-germanium layer 14 and portions of diode material 10 are chemically etched away between gold contacts 17 to form individual diode mesas 18. A top view of the device at this stage of fabrication is shown in the view of Figure 5.
Referring next to the cross-sectional view of Figure 6, there is shown the four-mesa device of Figures 4 and 5 assembled in a double-heat sink microwave diode package in accordance with the invention. Gold-contac-t la,yer 16 is soldered to the upper surface of metallic diode base 28 with solder joint 27. Diode base 28 is prefera'bly a highly thermally and electrically conductive metal such as copper which may have a coating of gold on its outer surface. The lower portion of base 28 is threaded and provided with a screw slot 29 for package mounting.
Base 28 forms a heat sink for the hea-t produced within diode mesas 18 and transmitted through gold-contact layer 16. Base flange 31 is provided , ' , . : , ~z~
around the upper portions of diode base 28 to form support for cylinarically-shaped ceramic spacer 26. Ceramic spacer 26 is both thermally and electrical-ly insulating. Annularly-shaped flange 25 is secured atop ceramic spacer 26.
In accordance with the invention, upper heat sink 32 is provided within the interior space of ceramic spacer 26 in electrical and thermal con--tact with gold contacts 17 of diode mesas 18. Upper heat sink 32 is formed of a highly thermally and elec-trically conductive metal such as gold-plated copper as used for base 28. The volume of upper heat sink 32 should be much larger than that of diode mesas 18 to provide a low thermal resistance for 10 heat flowing out of the upper ends of diode mesas 18. A flexible foil-flanged plug 24, in thermal and electrical contact with -the upper surface of upper hea-t sink 32, is secured to the upper surface of flange 25. A metal lid 23 covers and is also an electrical and thermal contact with foil-flanged plug `; 24. In actual device operation, such as in an amplifier or oscillator cir-cui-t, a contact rod abuts the surface of lid 23 providing continuation of the upper heat path.
The device shown in Figure 6 has numerous advantages over the de-vices of prior art in its heat-flow characteristics allowing it to be emplov-ed at higher power levels than were heretobefore possible with diode devices of similar dimensions. First, by providing multiple diode measas, rather than a single mesa of the same total junction area, the -thermal resistance between the junction or any point within any one of the diode mesas is sub-stantially lower than for a larger single mesa device. An arrangement of three mesas or other devices in a substantially equilateral triangular ar-rancgement, or four devices in a rectangular arrangement is preferred. Sec-ondly, because heat sinks are provided upon both sides of the diode mesas, heat may flow outwardly from two directions from the heat generating areas within the diode material. In this manner, a second large reduction in over-all thermal resistance and hence junction tempera-ture is achieved.
Referring next to Figure 7, there is shown a cross-sectional view .
~Z~2~i use~ul in exp'aining a dicing procedure in accordance with the invention. A
device in the same state of construction as illustrated in Figures 4 and 5 is mounted upon transparent glass plate 40 with a non-reactive wax 48 filling the space between and around diode mesas 18 and gold contact 17. The wax protected device is pressed against the upper surface of glass plate 40 with gold contacts abut-ting the surface. From the lower surface o~ glass plate li0 it is -then possible to visually distinguish between gold contacts 17 and wax 48 lying therebetween hence making it possible to determine where the dicing cuts are to be made.
The lower surface of glass plate 40 is then covered with a trans-parent layer of photoresist material which is masked with a photographic mask having lines corresponding to the positions of the dicing cuts and exposed to form lower alignment mask 42 having lines corresponding to those along which -the dicing cuts are to be made through gold contact layer 16. Other such lines are provided for alignment purposes in a grid pat-tern beyond the periphery of wax 48.
Next, a second layer of photoresist material is deposited upon -the upper surface of glass plate 40 and the upper surface of gold-contact layer 16. The same mask which was used to expose lower alignment mask 42 is aligned visually with the portions of the grid pattern extending beyond the periphery of wax 48. The photoresist layer is then exposed and chemically etched to remove the photoresist material in the lines along which dicing is to be made.
The device at the stage of construction as sho~m in Figure 7 is then placed within e spray-etching system illustrated in Flgure 8. The de-vice is placed upon perforated stand 52 positioned above a tank of collected etchant 51. Pump 54 circulates the collected etchant 51 through atomizing nozzle 53 spraying it toward the exposed dicing~lines. The etching process continues until the desired portions of gold-contact layer 16 have been com-pletely etched through. Wax 48 is then removed allowing the devices to be ', separated.
Of course, as before, many more than three diode mesas would ordin-arily be provided on a wafer that is being diced, three only being sho~,m for clarity of illustration. The same technique may be employed for etching apart single diode mesas or groups of d:iode mesas. It may also be readily appreciated tha-t any shape hea-t sink may be produced with the -technique of the inven-tion. For example, a circular heat sink may be produced ~or a de-vice having three mesas positioned in an equilateral triangular arrangement so that each mesa has the same effective t-hermal resistance. This could not have been done with the rectilinear techniques of the prior art.
This completes the description of the preferred embodimen-ts of the invention. Although pre-ferred embodiments have been described, it is be-lieved that numerous modifications and alterations thereto would be apparent to one having ordinary skill in the art without departing from the~spirit and scope of the in~ention.
.
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The invention may also be practiced by the method comprising the steps of providing a body of semiconductor material, sputter-ing a Schottky-barrier forming metal upon at least a portion of the surface of the body of semiconductor material at a sputtering power level sufficient to cause alloying between a portion of the semiconductor material and at least a portion of the sputtered Schottky-barrier forming metal, sputtering a layer of a refractory metal over the sputtered Schottky-barrier forming metal, and sputtering a layer of highly conductive metal over the layer of refractory metal. The body of the semiconductor material should be heated~to a temperature in the range of 300C
to 350~C prior to sputtering the Schottky-barrier forming metal.
The refractory metal should be sputtered at a level sufficient to cause alloying between at least portions of the Schottky-barrier forming metal not alloyed with the semiconductor material and a portion of the layer of re-fractory material. The semi-conductor material in preferred embodiments comprises gallium arsenide, while the Schottky-barrier -forming metal comprises platinum. The refractory metal may be titanium while the highly conductive metal may be gold.
,. : :
The invention may further be practiced by the method comprising the steps of providing a body of gallium arsenide semiconductor material, heating the body of semiconductor ma-terial to a temperature ~ithin the range of 300C to 350C, sputtering a layer of platinum upon a first surface of said body in predetermined locations at a sputtering po~er level in 0.5 to 2.7 watts/cm2 with a preferred operating point of 0.~ watts/cm2 to a thickness in the range of 100 to 300 A, cooling the body .o a temperature below 40C, sputtering a layer of titanium over the layer of platinum at a sputtering power level in the range of 1.4 to 4.4 watts/cm2 with a preferred operating point of 2.7 watts/cm2 to a thickness in the range of 1000 to 2000 A, cooling the body to a temperature of approximately 30C, and sputtering a layer of gold over the layer of titanium. A layer of gold-germanium alloy may be then sputtered upon a second section or upon a second portion of the first surface or upon predetermined portions of a second surface of the semiconductor material body with a layer of gold deposited over the gold-germanium alloy layer. Portions of the layer of gold-germanium alloy and underlying portions of the semiconductor material may then be etched away leaving thè remaining portion of the layer of gold-germanium alloy and of the body of semlconductor material in the form of mesas underlying the discs formed from the gold layer.
A heat sink may then be coupled both thermally and electrically to the gold discs.
In accordance with the present invention there is pro-vided a semiconductor device comprising in combination a body of semiconductor material; a first layer comprising an alloy of said semiconductor material and a first metal upon at least por-tions of a surface of said body of semiconductor material; and a second layer comprising an alloy of the first metal and a re-fractory metal disposed upon said first alloy layer.
In accordance with the present invention there is also provided a semiconductor d.iode device comprising in combination a ~ody of gallium arsenide semiconductor material; a layer con-sisting of an alloy of platinum and gallium arsenide disposed upon at least a portion of a surface of said body of gallium arsenide semiconductor material; a layer consisting of an alloy of platinum and titanium; a layer consisting of titanium dis-posed on the layer consisting of an alloy of platinum and titan-ium; and a layer of gold disposed upon said layer of titanium.
In accordance with the present invention there is also provided a device comprising in combination a body of gallium arsenide semiconductor material; a first contact upon said body of gallium arsenide semiconductor material comprising: a layer consisting of an alloy of platinum and gallium arsenide disposed upon a sur~ace of said body of gallium arsenide semiconductor material; a layer consis:ting of an alloy of pla~inum and titanium disposed upon said layer consisting of an alloy of platinumand gal-lium arsenide; a layer of titanium disposed upon said layer con sisting of an alloy of platinum and titanium; and a layer of gold disposed upon said layer of titanium; and second and third con-tacts upon said body of ~allium arsenide semiconductor material, each of said second and third contacts comprising: a layer of 3a non-Schottky barrier formin~ conducti~e material; and a layer of gold disposed upon said layer of non-Schottky barrier forming metal.
- 5a -~' z~
Brief Description of the Drawings Figures 1-4 are a series of cross-sectional views showing steps in the construction of a semiconductor device in accordance with the invention;
Figure 5 is a top view of the device as shown in Figure 1~;
Figure 6 is a cross-sectional view from a comple-ted packaged de-vice in accordance with the invention;
Figure 7 is a cross-sectional view showing steps in a dicing opera-tion in accordance with the invention;
Figure 8 shows a cross-sectional view of a spray-etching operation as used in the dicing operation of the invention;
Figure 9 is a graph showing a preferred doping density profile for the semiconductor material used with the invention; and Figure 10 is a graph showing an alternative preferred doping den-sity profile for the semiconductor material used with the invention.
Description of the Preferred Embodimen-ts Construction of semiconductor devices in accordance with the teach-ings of the present invention will be initially described in conjunction with the cross-sectional views of Figures 1-~. Referring first to Figure 1, there is shown in cross-section a layer of substrate of gallium arsenide semiconduc-tor diode material 10. Diode material 10 may have one of many different dop-ing density profiles depending -upon the particular application at hand. For example, diode material 10 may have the doping profile of a single-drift ; region IMPATT avalanche diode. A double-drift region IMPATT avalanche diode doping profile may also be used to particular advantage with the invention.
Referring momentarily to the graph of Figure 9, the preferred dop-ing profile of the double-drift IMPATT avalanche diode is illustrated. The material is formed in four regions, two of them being doped with an ~- or negative-type dopant while the other two are doped with a P- or positive-type dopant. A diode junction is formed substantially at the center of the mate-rial between the P and ~ moderately doped layers. Avalanching of charge .' .
~z~
carriers takes pla~e on either side of the diode junction within a portion both the P and N layers. The positive and negative charge carriers gener-ated by avalanching are pulled by an electric field outward -toward the P++
and N++ heavily doped region producing a time delay between tne time of gen-eration of the carriers near the diode junction and the time they reach the heavily-doped region. This time delay corresponds to an 180 phase shift between input and output signals and a diode circuit. The charge carriers in both the P and N regions, upon reaching the P+-~ and N++ regions respec-tively, recombine producing a conduction current in the output circuitry. A
particular diode device used with the invention which has been found to func-tion well with an N doping density of approximately 1.5 x 10 6/cm , a doping density in the N++ region of 2 x 10 /cm3, a density of 1.3 x 10 /cm3 in the P region and a doping density of approximately 10 ~/cm3 in the P++ region.
The ~ layer may have a width in the range of 3.5 to 4.5 microns depending upon the frequency of operation desired. For the same range of frequencies, the P region may have a width in the range of 3.0 to 3.5 microns. Wid-ths of 5.0 to 8.o microns for the N++ layer and approximately 1.0 micron for the P++ layer have been found to function adequately.
Most of the heat generated within the material having the doping density profile shown in Figure 9 is produced in the avalanche regions adja-cent the diode junction in the center of the device. The maximum amount of power which can be handled with such a device is, of course, dependent upon the junction temperature. The junction temperature is in turn dependent upon the rate at which heat may be extracted from the device. Since with the double-drift structure it is not possible to place a heat sink lmmediately adjacent the junction because of the presence of active material extending for appreciable distances on both sides of the junction, heat removal has been a serious problem severely limiting the maximum power at which such devices may be employed.
Referring now to Figure 10, there is shown a graph of a single-.
, '. ''' ., ... ',, ,, ', .' : .
drift Read-type IMPATT diode with which the invention may also be used to advantage. An avalanche region is formed with an l\l-type semiconductor rnate-rial adjacent a rnetal layer suitable for forming a Schottky-barrier junction.
A layer of pla-tinum may be used with gallium arsenide semiconductor material to form such a junction. A thin doping spike of heavily doped semiconductor material terminates the avalanche region and confines the avalanche of charge carriers strictly between the layer of Schottky-barrier forming metal and the doping spike. The charge carriers produced within the avalanche region are pulled through the drift region of moderately-doped material by the ex-ternally applied electric field. Upon reaching the termination region, the cha-rge car-riers recombine forming a conduction current which flows in the external cir-cuitry. A two-layered heavily-doped termination region may be used with the layer immediately adjacen-t the drift region being less heavily doped to pre-vent carrier injection from defects at the interface between the drift region and termination region and the consequent generation of an unwanted reverse current. As in the previously described double-drift avalanche diode, heat removal is also a severe problem with this type of device.
Referring again to Figure 1, -the steps in the construction of a de-vice in accordance with the teachings of the present invention will be dis-cussed in further detail. For use with diode material having a doping densityin accordance with that specified in Figure 10, a three-layer metallization pattern is deposited over one surface of diode material 10 with a layer of Schottky-barrier forming metal in contact with the surface of diode material 10. For the case of the double-drift structure shown in Figure 10, the high-ly doped P++ layer may be omitted as the three-layer metallization described will form a good ohmic contac-t with R-type gallium arsenide material. Also, with the double-drift IMPATT avalanche diode specified in Figure 9, the three-layer metallization may be replaced, for example, by some other metal-lization system. With the embodiment shown in Figure 1, first a layer of platinum 11 is sputtered upon the surface of gallium-arsenide diode material ~ .~,., .. ', , ' 2~
Upon platinum layer 1] is then sputtered layer 12. Titaniwn is the preferred material although tungsten, hafnium, or other refractory metals may be used as well for layer 12. Next, gold layer 13 is sputtered over titanium layer 12. Highly conductive gold layer 13 is sputter deposited upon titanium layer 12 and forms the lower contact to the diode.
In accordance with one aspect of the invention, a particularly ad-vantageous sputtering process is used which results in a device in which the gold layer is prevented from diffusing through the platinum layer into diode material 10 and adversely affecting some of the electrical properties of the material. In accordance with the invention, diode material 10 is first heat-ed to a temperature in -the range of 300 to 350 C with 330 C being a preferred operating point. Platinum lay-er 11 is then sputtered upon the surface of diode material 10 with a sputtering power in the range of 0.5 to 2.7 watts/
cm with a preferred operating point of o.8 watts/cm to a preferred thick-ness in the range of 100 to 300A. A thickness of 200A has been found to function well. During this initial sputtering operation, a portion of plat-inum layer 11 reacts with the gallium arsenide material forming an alloy therewith. Diode material 10 is then cooled to a temperature in the range of 20 to 40C with 30C being a preferred operating point, and a layer 12 of titanium having a thickness in the range of 1000~ to 2000~ is sputtered over -platinum layer 11 at a relatively high sputtering power level in the pre-ferred range of 1.4 to 4.4 watts/cm with a preferred operating point of 2.7 watts/cm . The relatively high -titanium power level causes impact alloying between the remaining platinum and the titanium material forming a compound which reacts chemically much more slowly with gallium arsenide than does pure platinum. Moreover, atoms of gold layer 13 are not able to migrate through the barrier thus formed. Still further, it has unexpectedly been found that diode deuices constructed in accordance with the above-described sputtering process exhibit substantially lower noise measures than for diodes having an ordinary Schottky-barrier contact with the gold layer immediately adjacent . . , the Schottky-~arrier forming me-tal.
Referring nex-t to Figure 2, a layer of gold-germanium eutectic alloy is evaporated upon the surface of gallium arsenide diode material 10 opposite that upon which the p]atinum-titanium-gold layers were deposited.
This surface corresponds to the outer side of -the termination region of a device having a profile shown in Figure 10. Atop gold-germanium layer 14 is pla,ted gold contact layer 15. Similarly, gold contact layer 16 is plated above previously deposited gold layer 13.
Next, as shown in the view of Figure 3 gold-contact layer 15 is masked and chemically e-tched away in predetermined locations using well-known photoresist techniques -to leave a plurality of circular gold contacts 17 atop positions at which diode mesas are to be formed. Ordinarily, many more con-tacts could be formed upon a single semiconductor wafer than are herein shown. For large-scale production, many hundreds of such contacts could be formed upon one wafer then the diode mesa devices diced apart singly or in groups as desired.
Next, as illustrated in the view of Figure 4, gold-germanium layer 14 and portions of diode material 10 are chemically etched away between gold contacts 17 to form individual diode mesas 18. A top view of the device at this stage of fabrication is shown in the view of Figure 5.
Referring next to the cross-sectional view of Figure 6, there is shown the four-mesa device of Figures 4 and 5 assembled in a double-heat sink microwave diode package in accordance with the invention. Gold-contac-t la,yer 16 is soldered to the upper surface of metallic diode base 28 with solder joint 27. Diode base 28 is prefera'bly a highly thermally and electrically conductive metal such as copper which may have a coating of gold on its outer surface. The lower portion of base 28 is threaded and provided with a screw slot 29 for package mounting.
Base 28 forms a heat sink for the hea-t produced within diode mesas 18 and transmitted through gold-contact layer 16. Base flange 31 is provided , ' , . : , ~z~
around the upper portions of diode base 28 to form support for cylinarically-shaped ceramic spacer 26. Ceramic spacer 26 is both thermally and electrical-ly insulating. Annularly-shaped flange 25 is secured atop ceramic spacer 26.
In accordance with the invention, upper heat sink 32 is provided within the interior space of ceramic spacer 26 in electrical and thermal con--tact with gold contacts 17 of diode mesas 18. Upper heat sink 32 is formed of a highly thermally and elec-trically conductive metal such as gold-plated copper as used for base 28. The volume of upper heat sink 32 should be much larger than that of diode mesas 18 to provide a low thermal resistance for 10 heat flowing out of the upper ends of diode mesas 18. A flexible foil-flanged plug 24, in thermal and electrical contact with -the upper surface of upper hea-t sink 32, is secured to the upper surface of flange 25. A metal lid 23 covers and is also an electrical and thermal contact with foil-flanged plug `; 24. In actual device operation, such as in an amplifier or oscillator cir-cui-t, a contact rod abuts the surface of lid 23 providing continuation of the upper heat path.
The device shown in Figure 6 has numerous advantages over the de-vices of prior art in its heat-flow characteristics allowing it to be emplov-ed at higher power levels than were heretobefore possible with diode devices of similar dimensions. First, by providing multiple diode measas, rather than a single mesa of the same total junction area, the -thermal resistance between the junction or any point within any one of the diode mesas is sub-stantially lower than for a larger single mesa device. An arrangement of three mesas or other devices in a substantially equilateral triangular ar-rancgement, or four devices in a rectangular arrangement is preferred. Sec-ondly, because heat sinks are provided upon both sides of the diode mesas, heat may flow outwardly from two directions from the heat generating areas within the diode material. In this manner, a second large reduction in over-all thermal resistance and hence junction tempera-ture is achieved.
Referring next to Figure 7, there is shown a cross-sectional view .
~Z~2~i use~ul in exp'aining a dicing procedure in accordance with the invention. A
device in the same state of construction as illustrated in Figures 4 and 5 is mounted upon transparent glass plate 40 with a non-reactive wax 48 filling the space between and around diode mesas 18 and gold contact 17. The wax protected device is pressed against the upper surface of glass plate 40 with gold contacts abut-ting the surface. From the lower surface o~ glass plate li0 it is -then possible to visually distinguish between gold contacts 17 and wax 48 lying therebetween hence making it possible to determine where the dicing cuts are to be made.
The lower surface of glass plate 40 is then covered with a trans-parent layer of photoresist material which is masked with a photographic mask having lines corresponding to the positions of the dicing cuts and exposed to form lower alignment mask 42 having lines corresponding to those along which -the dicing cuts are to be made through gold contact layer 16. Other such lines are provided for alignment purposes in a grid pat-tern beyond the periphery of wax 48.
Next, a second layer of photoresist material is deposited upon -the upper surface of glass plate 40 and the upper surface of gold-contact layer 16. The same mask which was used to expose lower alignment mask 42 is aligned visually with the portions of the grid pattern extending beyond the periphery of wax 48. The photoresist layer is then exposed and chemically etched to remove the photoresist material in the lines along which dicing is to be made.
The device at the stage of construction as sho~m in Figure 7 is then placed within e spray-etching system illustrated in Flgure 8. The de-vice is placed upon perforated stand 52 positioned above a tank of collected etchant 51. Pump 54 circulates the collected etchant 51 through atomizing nozzle 53 spraying it toward the exposed dicing~lines. The etching process continues until the desired portions of gold-contact layer 16 have been com-pletely etched through. Wax 48 is then removed allowing the devices to be ', separated.
Of course, as before, many more than three diode mesas would ordin-arily be provided on a wafer that is being diced, three only being sho~,m for clarity of illustration. The same technique may be employed for etching apart single diode mesas or groups of d:iode mesas. It may also be readily appreciated tha-t any shape hea-t sink may be produced with the -technique of the inven-tion. For example, a circular heat sink may be produced ~or a de-vice having three mesas positioned in an equilateral triangular arrangement so that each mesa has the same effective t-hermal resistance. This could not have been done with the rectilinear techniques of the prior art.
This completes the description of the preferred embodimen-ts of the invention. Although pre-ferred embodiments have been described, it is be-lieved that numerous modifications and alterations thereto would be apparent to one having ordinary skill in the art without departing from the~spirit and scope of the in~ention.
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Claims (19)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor device comprising in combination:
(a) a body of semiconductor material;
(b) a first layer comprising an alloy of said semi-conductor material and a first metal upon at least portions of a surface of said body of semiconductor material; and (c) a second layer comprising an alloy of the first metal and a refractory metal disposed upon said first alloy layer.
(a) a body of semiconductor material;
(b) a first layer comprising an alloy of said semi-conductor material and a first metal upon at least portions of a surface of said body of semiconductor material; and (c) a second layer comprising an alloy of the first metal and a refractory metal disposed upon said first alloy layer.
2. The combination of claim 1 wherein: said first metal is of a type which forms a Schottky-barrier junction with said semiconductor material.
3. The combination of claim 1 further comprising: a layer of a third metal disposed upon said layer of a refractory metal.
4. The combination of claim 3 wherein: said third metal is highly conductive.
5. The combination of claim 2 wherein said body of semi-conductor material comprises: a plurality of layers of said semiconductor material, at least some of said layers of said semiconductor material being of different conductivity.
6. A semiconductor device comprising in combination: a body of semiconductor material; a layer comprising an alloy of said semiconductor material and a first metal disposed upon at least portions of a surface of said body of said semiconductor mate-rial; a layer comprising an alloy of said first metal and a re-fractory metal disposed upon said layer comprising semiconductor material and said first metal; and a layer of said refractory metal disposed upon said layer comprising an alloy of said first metal and said refractory metal.
7. The combination of claim 6 wherein: said first metal is of a type which forms a Schottky-barrier junction with said semi-conductor material.
8. The comhination of claim 6 further comprising: a layer of a third metal disposed upon said layer of a refractory metal.
9. The combination of claim 8 wherein: said third metal is highly conductive.
10. The combination of claim 7 wherein said body of semi-conductor material comprises: a plurality of layers of said semiconductor material, at least some of said layers of said semiconductor material being of different conductivity.
11. A semiconductor diode device comprising in combination:
a body of gallium arsenide semiconductor material; a layer con-sisting of an alloy of platinum and gallium arsenide disposed upon at least a portion of a surface of said body of gallium arsenide semiconductor material; a layer consisting of an alloy of platinum and titanium; a layer consisting of titanium disposed on the layer consisting of an alloy of platinum and titanium;
and a layer of gold disposed upon said layer of titanium.
a body of gallium arsenide semiconductor material; a layer con-sisting of an alloy of platinum and gallium arsenide disposed upon at least a portion of a surface of said body of gallium arsenide semiconductor material; a layer consisting of an alloy of platinum and titanium; a layer consisting of titanium disposed on the layer consisting of an alloy of platinum and titanium;
and a layer of gold disposed upon said layer of titanium.
12. The combination of claim 11 wherein: said body of gallium arsenide semiconductor material has a doping profile for an IMPATT diode.
13. The combination of claim 11 wherein: said body of gall-ium arsenide semiconductor material has a doping profile for a Read-type diode.
14. The combination of claim 11 wherein: the thickness of said alloy layers is in the range of 100 .ANG. to 300 .ANG..
15. The combination of claim 14 wherein: the thickness of said titanium layer is in the range of 1000 to 2000 .ANG..
16. A device comprising in combination: a body of gallium arsenide semiconductor material; a first contact upon said body of gallium arsenide semiconductor material comprising: a layer consisting of an alloy of platinum and gallium arsenide disposed upon a surface of said body of gallium arsenide semiconductor material; a layer consisting of an alloy of platinum and tita-nium disposed upon said layer consisting of an alloy of platinum and gallium arsenide; a layer of titanium disposed upon said layer consisting of an alloy of platinum and titanium; and a layer of gold disposed upon said layer of titanium; and second and third contacts upon said body of gallium arsenide semi-conductor material, each of said second and third contacts comprising: a layer of non-Schottky barrier forming conductive material; and a layer of gold disposed upon said layer of non-Schottky barrier forming metal.
17. The combination of claim 16 wherein said layer of non-Schottky barrier forming material is selected from the group consisting of a eutectic mixture of gold and germanium and a eutectic mixture of gold and nickel.
18. The combination of claim 16 wherein: said first contact is located between said second and third contact.
19. The combination of claim 18 wherein: a plurality of each of said first, second and third contacts are provided.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US833,317 | 1977-09-14 | ||
| US05/833,317 US4197551A (en) | 1977-09-14 | 1977-09-14 | Semiconductor device having improved Schottky-barrier junction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1102926A true CA1102926A (en) | 1981-06-09 |
Family
ID=25264075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA309,646A Expired CA1102926A (en) | 1977-09-14 | 1978-08-18 | Semiconductor device having improved schottky-barrier junction |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4197551A (en) |
| JP (1) | JPS5453861A (en) |
| CA (1) | CA1102926A (en) |
| CH (1) | CH633654A5 (en) |
| DE (1) | DE2839044C2 (en) |
| GB (1) | GB2004416B (en) |
| NL (1) | NL7809331A (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0029334B1 (en) * | 1979-11-15 | 1984-04-04 | The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and | Series-connected combination of two-terminal semiconductor devices and their fabrication |
| US4316201A (en) * | 1980-05-08 | 1982-02-16 | The United States Of America As Represented By The Secretary Of The Navy | Low-barrier-height epitaxial Ge-GaAs mixer diode |
| US5144413A (en) * | 1981-11-23 | 1992-09-01 | Raytheon Company | Semiconductor structures and manufacturing methods |
| US4439912A (en) * | 1982-04-19 | 1984-04-03 | The United States Of America As Represented By The Secretary Of The Army | Infrared detector and method of making same |
| US4518255A (en) * | 1982-08-20 | 1985-05-21 | Mcdonnell Douglas Corporation | Temperature tracking range finder |
| US4499659A (en) * | 1982-10-18 | 1985-02-19 | Raytheon Company | Semiconductor structures and manufacturing methods |
| US4596070A (en) * | 1984-07-13 | 1986-06-24 | Texas Instruments Incorporated | Interdigitated IMPATT devices |
| GB2182200B (en) * | 1985-08-31 | 1989-04-26 | Plessey Co Plc | Mesa semiconductor device |
| US4784967A (en) * | 1986-12-19 | 1988-11-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method for fabricating a field-effect transistor with a self-aligned gate |
| FR2623941A1 (en) * | 1987-11-27 | 1989-06-02 | Thomson Csf | Schottky contact on an indium phosphide substrate |
| US5260603A (en) * | 1990-01-25 | 1993-11-09 | Kabushiki Kaisha Toshiba | Electrode structure of semiconductor device for use in GaAs compound substrate |
| US5106771A (en) * | 1991-06-05 | 1992-04-21 | At&T Bell Laboratories | GaAs MESFETs with enhanced Schottky barrier |
| JP2796919B2 (en) * | 1992-05-11 | 1998-09-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Metallization composites and semiconductor devices |
| US5336631A (en) * | 1993-05-26 | 1994-08-09 | Westinghouse Electric Corporation | Method of making and trimming ballast resistors and barrier metal in microwave power transistors |
| JP2006332230A (en) * | 2005-05-25 | 2006-12-07 | Ecotron:Kk | Schottky barrier diode and method of manufacturing the same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3551842A (en) * | 1968-03-27 | 1970-12-29 | Rca Corp | Semiconductor laser having high power output and reduced threshold |
| US3755752A (en) * | 1971-04-26 | 1973-08-28 | Raytheon Co | Back-to-back semiconductor high frequency device |
| US3935586A (en) * | 1972-06-29 | 1976-01-27 | U.S. Philips Corporation | Semiconductor device having a Schottky junction and method of manufacturing same |
| US3938243A (en) * | 1973-02-20 | 1976-02-17 | Signetics Corporation | Schottky barrier diode semiconductor structure and method |
| US3995301A (en) * | 1973-03-23 | 1976-11-30 | Ibm Corporation | Novel integratable Schottky Barrier structure and a method for the fabrication thereof |
| US3896473A (en) * | 1973-12-04 | 1975-07-22 | Bell Telephone Labor Inc | Gallium arsenide schottky barrier avalance diode array |
| JPS50108878A (en) * | 1974-02-01 | 1975-08-27 | ||
| US3906541A (en) * | 1974-03-29 | 1975-09-16 | Gen Electric | Field effect transistor devices and methods of making same |
| JPS50131764A (en) * | 1974-04-05 | 1975-10-18 | ||
| JPS5136878A (en) * | 1974-09-14 | 1976-03-27 | Tokyo Shibaura Electric Co | Handotaisochi no seizohoho |
| US4016643A (en) * | 1974-10-29 | 1977-04-12 | Raytheon Company | Overlay metallization field effect transistor |
| JPS5850428B2 (en) * | 1975-04-16 | 1983-11-10 | 株式会社東芝 | Mesa semiconductor device |
| JPS5845832B2 (en) * | 1975-08-26 | 1983-10-12 | 日本電気株式会社 | Kinzoku-Handoutai Seiriyuseisetsugouno Seihou |
| US4110488A (en) * | 1976-04-09 | 1978-08-29 | Rca Corporation | Method for making schottky barrier diodes |
-
1977
- 1977-09-14 US US05/833,317 patent/US4197551A/en not_active Expired - Lifetime
-
1978
- 1978-08-18 CA CA309,646A patent/CA1102926A/en not_active Expired
- 1978-09-07 DE DE2839044A patent/DE2839044C2/en not_active Expired
- 1978-09-12 GB GB7836559A patent/GB2004416B/en not_active Expired
- 1978-09-13 JP JP11288778A patent/JPS5453861A/en active Granted
- 1978-09-13 NL NL7809331A patent/NL7809331A/en not_active Application Discontinuation
- 1978-09-14 CH CH961778A patent/CH633654A5/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB2004416B (en) | 1982-03-31 |
| CH633654A5 (en) | 1982-12-15 |
| JPS5453861A (en) | 1979-04-27 |
| US4197551A (en) | 1980-04-08 |
| GB2004416A (en) | 1979-03-28 |
| JPS6222271B2 (en) | 1987-05-16 |
| DE2839044C2 (en) | 1986-06-12 |
| DE2839044A1 (en) | 1979-03-22 |
| NL7809331A (en) | 1979-03-16 |
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