CA1081855A - Initializing means for a bus-oriented data processing system employing firmware-configured modules - Google Patents
Initializing means for a bus-oriented data processing system employing firmware-configured modulesInfo
- Publication number
- CA1081855A CA1081855A CA271,931A CA271931A CA1081855A CA 1081855 A CA1081855 A CA 1081855A CA 271931 A CA271931 A CA 271931A CA 1081855 A CA1081855 A CA 1081855A
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- Prior art keywords
- data processing
- firmware
- storage means
- processing system
- memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
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- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Hardware Redundancy (AREA)
Abstract
Title of the Invention INITIALIZING MEANS FOR A BUS-ORIENTED
DATA PROCESSING SYSTEM EMPLOYING FIRMWARE-CONFIGURED
MODULES
Abstract of the Disclosure In order to initialize firmware-configured modules, such as the system processor and input/output controllers, in a data processing system, a service processor is employed. The service processor, which itself normally functions as a power-ful input/output controller, includes an instruction memory comprised, at least partially, of non-volatile memory means such as a read-only memory. Upon utilization during actual start-up or when changing the configuration of the data pro-cessing system under program control, an instruction counter in the service processor is forced to a predetermined address in the non-volatile section of the instruction memory. The predetermined location contains the first instruction in a boot-strap routine by which a loader and the necessary firmware may be obtained from a diskette coupled to the service processor The firmware is then distributed among the firmware-configured modules throughout the system. When the system is configured, the service processor itself is reconfigured to function as an input/output controller for peripherals coupled to it.
DATA PROCESSING SYSTEM EMPLOYING FIRMWARE-CONFIGURED
MODULES
Abstract of the Disclosure In order to initialize firmware-configured modules, such as the system processor and input/output controllers, in a data processing system, a service processor is employed. The service processor, which itself normally functions as a power-ful input/output controller, includes an instruction memory comprised, at least partially, of non-volatile memory means such as a read-only memory. Upon utilization during actual start-up or when changing the configuration of the data pro-cessing system under program control, an instruction counter in the service processor is forced to a predetermined address in the non-volatile section of the instruction memory. The predetermined location contains the first instruction in a boot-strap routine by which a loader and the necessary firmware may be obtained from a diskette coupled to the service processor The firmware is then distributed among the firmware-configured modules throughout the system. When the system is configured, the service processor itself is reconfigured to function as an input/output controller for peripherals coupled to it.
Description
-- 108~855 Field of the Invention This invention relates to the data processing arts and, more particularly, to the art of initializing firmware-configured modules in a data processing system.
Related Patents This invention may be employed in a data proces-sing system such as that disclosed in U. S. Patent No.
; 4,041,472 entitled "Data Processing Internal Communications System Having Plural Time-Shared Intercommunication Buses and Inter-Bus Communication Means", and assigned to the same assignee as the present application.
Background of the Invention One of the most substantial, and perhaps the dom-inant, cost in an operative data processing system is to be ¦ found in the software. As new generations of hardware have become available, it has become apparent that there is too much time and money invested in current software and user programs to simply disregard in favor of new-generation hardware. Moreover, a user faced with a massive effort to upgrade to a new system is vulnerable to the suggestion that he can just as easily switch to a new computer sup-plier with possible cost/performance gains if the already-developed software must be discarded. Thus, it will be apparent that a prime requirement for new generations of computer hardware is true compatability with already-I developed software.
¦ This compatability may be achieved by providing the new hardware with the capability for emulating the predecessor hardware. While such emulation may be carried out under the control of a suitable emulator program oper-ating in the new hardware, the performance obtained is, of necessity, limited. Therefore, some new generation computer .~:
systems include modules which are firmware-configured in order that they may assume the "personality" of an older computer system for which highly developed software has already been developed to handle the task which the new system is to perform. Thus, a "virtual" machine is created by the firmware, which virtual machine can execute the al-ready-developed software with enhanced performance char-acteristics. Further, a firmware-configured data pro-cessing system has the facility for being reconfigured at anytime, even dynamically, to become another, completely different, virtual machine to execute previously-developed software for such other prior art computers for which soft-ware suitable to the task at hand may have been developed.
Thus, those skilled in the art will understand that very substantial benefits are realized from the utili-zation of modules in a computer system which are firmware-¦ configured. However, attendent idiosyncracies of such `I firmware-configured modules must be dealt with. Chief a-mong these is the necessity for configuring the apparatus upon initilization inasmuch as the firmware must be stored ! in volatile memory if the ability to assume the personali-ties of different virtual machines is to be realized. It is to this problem of configuring such a data processing system, either upon initilization or dynamically, to which our lnvention is addressed.
Thus, it is a broad object of our invention to provide improved means for configuring a firmware-configur-ed data processing system.
It is another object of our invention to provide such means which is simple, fast, and reliable in operation.
It is a more specific object of our invention to provide such means which includes a temporarily dedicated ,, ~ .
.... , , ; ,, . ,. . , .... . ~ :
108~85S
special-purpose processor having non-volatile memory which may be initially addressed to institute a sequence of events resulting in the firmware configuration of the system.
Brief Description of the Invention Briefly, these and other objects of the inven-tion are achieved in a data processing system which has at least one firmware-configured module. The data processing system includes a first interchangeable storage device which permanently stores the system firmware, and a second storage device which permanently stores a program for ac-cessing the system firmware stored in the first inter-changeable storage device. Also included in the data pro-cessing system is a processor which is responsive to the program stored in the second storage device for reading the system firmware from the first interchangeable storage de-vice and configuring or reconfiguring the firmware-con-figured module. More specifically, all the firmware neces-sary to configure a predetermined system is stored on a diskette which is in communication with a service proces-sor. The service processor, which is itself firmware-configured and normally operates as a powerful input/
output controller, includes non-volatile memory which con-tains a bootstrap routing. Upon initilization by an oper`ator or from an appropriate signal in the system as it is operating, an instruction counter of the service processor is forced to the beginning address of the boot-strap routine in the non-, ~ "-' ~ .
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~r , volatile memoryO The service processor responds by calling in a loader program from the diskette and configures itself to function as a firmware loader for the entire data processing system. Under control of the loader, the service processor extracts the firmware from the diskette and configures the system. Finally, the service processor is itself reconfigured as an input/output controller or such other functional con- -figuration as may be useful in a particular system.
The sub~ect matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specificationO The invention, however, both as to or-~ganization and method of operation, may best be understood by reference to the following description taken in connection with the sub~oined claims and the accompanying drawing of which:
Figure 1 is a ma~or block diagram of a bus-oriented, multi-bus data processing system comprising an exemplary en-vironment in which our invention find~ use; and Figure 2 is a block diagram of the service subsystem, including the service processor, illustrating its relationship to the entire data processing system during the firmware con-figuration process.
Attention is now directed to Figure 1 which illus-trates, in a block diagram, an exemplary data processing system ln which the present invention finds use. The data processing system of Figure 1 is bus-oriented in that all the immediate subsystems, including the processor subsystem 1, are coupled to one another by means of at least one internal transfer bus 2.
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The internal transfer bus is incorporated into an internal transfer bus subsystem 3 which also includes a plurality of local bus adapters 4, an inter-bus communication adapter 5, bus control logic 6, and timing logic 7. In the internal trans-fer bus subsystem, up to sixteen local bus adapters may be coupled to the internal transfer bus 2. Undesignated subsystems 8 may constitute any of the typical subsystems usually found in a bus-oriented data processing system; e.g.: core memory, tape units, disc units, printers, video displays, etc. The service 10 subsystem 9 may include a system console to effect two-way com- , munication between an operator and the data processing system.
The function of the internal transfer bus 2 is to transmit information from one local bus adapter to another local bus adapter. It defines the paths and procedures to be used by the local bus adapters to communicate with each other. All in-I formation is passed over the internal transfer bus sequentially
Related Patents This invention may be employed in a data proces-sing system such as that disclosed in U. S. Patent No.
; 4,041,472 entitled "Data Processing Internal Communications System Having Plural Time-Shared Intercommunication Buses and Inter-Bus Communication Means", and assigned to the same assignee as the present application.
Background of the Invention One of the most substantial, and perhaps the dom-inant, cost in an operative data processing system is to be ¦ found in the software. As new generations of hardware have become available, it has become apparent that there is too much time and money invested in current software and user programs to simply disregard in favor of new-generation hardware. Moreover, a user faced with a massive effort to upgrade to a new system is vulnerable to the suggestion that he can just as easily switch to a new computer sup-plier with possible cost/performance gains if the already-developed software must be discarded. Thus, it will be apparent that a prime requirement for new generations of computer hardware is true compatability with already-I developed software.
¦ This compatability may be achieved by providing the new hardware with the capability for emulating the predecessor hardware. While such emulation may be carried out under the control of a suitable emulator program oper-ating in the new hardware, the performance obtained is, of necessity, limited. Therefore, some new generation computer .~:
systems include modules which are firmware-configured in order that they may assume the "personality" of an older computer system for which highly developed software has already been developed to handle the task which the new system is to perform. Thus, a "virtual" machine is created by the firmware, which virtual machine can execute the al-ready-developed software with enhanced performance char-acteristics. Further, a firmware-configured data pro-cessing system has the facility for being reconfigured at anytime, even dynamically, to become another, completely different, virtual machine to execute previously-developed software for such other prior art computers for which soft-ware suitable to the task at hand may have been developed.
Thus, those skilled in the art will understand that very substantial benefits are realized from the utili-zation of modules in a computer system which are firmware-¦ configured. However, attendent idiosyncracies of such `I firmware-configured modules must be dealt with. Chief a-mong these is the necessity for configuring the apparatus upon initilization inasmuch as the firmware must be stored ! in volatile memory if the ability to assume the personali-ties of different virtual machines is to be realized. It is to this problem of configuring such a data processing system, either upon initilization or dynamically, to which our lnvention is addressed.
Thus, it is a broad object of our invention to provide improved means for configuring a firmware-configur-ed data processing system.
It is another object of our invention to provide such means which is simple, fast, and reliable in operation.
It is a more specific object of our invention to provide such means which includes a temporarily dedicated ,, ~ .
.... , , ; ,, . ,. . , .... . ~ :
108~85S
special-purpose processor having non-volatile memory which may be initially addressed to institute a sequence of events resulting in the firmware configuration of the system.
Brief Description of the Invention Briefly, these and other objects of the inven-tion are achieved in a data processing system which has at least one firmware-configured module. The data processing system includes a first interchangeable storage device which permanently stores the system firmware, and a second storage device which permanently stores a program for ac-cessing the system firmware stored in the first inter-changeable storage device. Also included in the data pro-cessing system is a processor which is responsive to the program stored in the second storage device for reading the system firmware from the first interchangeable storage de-vice and configuring or reconfiguring the firmware-con-figured module. More specifically, all the firmware neces-sary to configure a predetermined system is stored on a diskette which is in communication with a service proces-sor. The service processor, which is itself firmware-configured and normally operates as a powerful input/
output controller, includes non-volatile memory which con-tains a bootstrap routing. Upon initilization by an oper`ator or from an appropriate signal in the system as it is operating, an instruction counter of the service processor is forced to the beginning address of the boot-strap routine in the non-, ~ "-' ~ .
I ~
- 4 - -~
' ! ~ : . : : : .. .. . . : ... : .
' . . : : .' . .
~r , volatile memoryO The service processor responds by calling in a loader program from the diskette and configures itself to function as a firmware loader for the entire data processing system. Under control of the loader, the service processor extracts the firmware from the diskette and configures the system. Finally, the service processor is itself reconfigured as an input/output controller or such other functional con- -figuration as may be useful in a particular system.
The sub~ect matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specificationO The invention, however, both as to or-~ganization and method of operation, may best be understood by reference to the following description taken in connection with the sub~oined claims and the accompanying drawing of which:
Figure 1 is a ma~or block diagram of a bus-oriented, multi-bus data processing system comprising an exemplary en-vironment in which our invention find~ use; and Figure 2 is a block diagram of the service subsystem, including the service processor, illustrating its relationship to the entire data processing system during the firmware con-figuration process.
Attention is now directed to Figure 1 which illus-trates, in a block diagram, an exemplary data processing system ln which the present invention finds use. The data processing system of Figure 1 is bus-oriented in that all the immediate subsystems, including the processor subsystem 1, are coupled to one another by means of at least one internal transfer bus 2.
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.. .. - , , . , :
: .
.- : - . , ,.: ' .: - . ',. . .
. . . . :
. . . . . ..
.
The internal transfer bus is incorporated into an internal transfer bus subsystem 3 which also includes a plurality of local bus adapters 4, an inter-bus communication adapter 5, bus control logic 6, and timing logic 7. In the internal trans-fer bus subsystem, up to sixteen local bus adapters may be coupled to the internal transfer bus 2. Undesignated subsystems 8 may constitute any of the typical subsystems usually found in a bus-oriented data processing system; e.g.: core memory, tape units, disc units, printers, video displays, etc. The service 10 subsystem 9 may include a system console to effect two-way com- , munication between an operator and the data processing system.
The function of the internal transfer bus 2 is to transmit information from one local bus adapter to another local bus adapter. It defines the paths and procedures to be used by the local bus adapters to communicate with each other. All in-I formation is passed over the internal transfer bus sequentially
2, following the common procedure defined by the internal transfer bus protocol. The identical local bus adapters 4 interface each subsystem to the internal transfer bus. Each local bus adapter performs all the logic operations necessary to insurethat the internal transfer bus discipline is maintained at all ' times.
The bus control logic 6 performs several functions.
It arbitrates all local bus adapter requests to use the internal 1, transfer bus on a fixed priority basis in the exemplary embodi-ment O The bus control logic also checks the parity of all messages sent over the internal transfer bus and reflects the 1 :~
. ~
,, . ., ~ ~ ' ~081855 result of the parity check onto the internal transfer bus for analysis by the communicating local bus adapters. The bus con-trol logic can communicate wlth the service subsystem 9 and the processor subsystem 1 by means of the serial service bus 10 in order to provide certain system condition history and status information and configuring signals. The internal transfer subsystems are synchronous logic machines in that all opera-tions in the internal transfer subsystems are synchronized with clock and phase signals emanating from the timing logic 7.
The inter-bus communications adapter S facilitates communications between the system components associated with the internal transfer bus subsystem 3 and the subsystems as-sociated with a second internal transfer bus subsystem 3' from ' which additional subsystems 11 depend.
~1~ Figure 2 is a block diagram of the service subsystem illustrating particularly the basic structure of the service ~ subsystem 9. The instruction counter 12 is a sixteen-bit ¦ counter which addresses the instruction memory 14 whereby the ,.. .
re6ultant memory data is made available to the service processor.
Two modes of operation are implemented for the instruction counter 12; viz.: increment and parallel load. Normally, the instructLon counter addresses consecutive memory locations in the instruction memory 14 by means of the increment mode. The parallel load mode is used to load and address into the in-struction counter during a branch operation to a non-consecu-tive memory location and also to effect system initiaIization as will be explained more fully below.
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108~855 The instruction memory 14 accepts a sixteen-bit memory address such that the maximum address allowable is 65,53510. The first 1024 memory addresses are allocated to a read-only memory section 16 of the instruction memory, and the remaining memory is contained in a random address section 18. The number of random access memory words actually implemented will depend on the characteristics of the given system in which the service subsystem 9 is resi-dent.
Instruction register 20 is an eighteen-bit regist-er which receives the sixteen-bit instruction being execut-ed as well as one parity bit on each of two instruction bytes. Instruction decoding logic 22 is employed to de-code the operation code portion of the instruction tem-porarily stored in the instruction register 20. The in-struction decoding logic 22 provides the control signals necessary to execute the specific instruction identified by the opcode. In a presently preferred embodiment of the service shbsystem 9, programmable read-only memory chips 20 are employed to effect the decoding in the instruction de- ;
coding logic 22.
The service subsystem 9 contains sixteen general I purpose registers contained in the register memory 24.
¦ These general purpose registers are allocated for use as ¦ accumulators, index registers, counters, etc. All arith-metic, shift, load and store operations involve one or ;
more of these registers. ~ ~;
'l The basic logic structure of the service proces-sor is oriented around a sixteen-bit arithmetic and logic unit 26. In the presently preferred embodiment of the service processor, the arithmetic and logic unit 26 com-prises a set of four, four-bit arithmetic logic unit/
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~, - , . . ,, : . :. . ~. :,. , :: , - . . ~ .
function generator integrated circuit chips wired in a carry-lookahead fashion. The arithmetic and logic unit 26 provides a carryout of the most significant bit and carryin to the least significant bit. The arithmetic and logic unit performs addition on two binary numbers in two's comple-. ment form, and subtraction of two binary numbers is ac-complished with two's complement addition as fo~lows:
A+(B+ carryin) where s is the one's complement of B, the complementing of B being performed internal to the arith-.¦ 10 metic and logic unit 26. Of course, those skilled in the art will appreciate that the specific manner by which arith-metic and logic unit 26 functions is not directly germane to the instant invention provided the capability is in-cluded in the service subsystem 9.
Data is transferred into and out of the service processor through the external register unit 28. The ad-dressing structure employed allows a possible 128 external registers in the external register unit 28. Communication to the internal transfer bus subsystem 2 (Figure 1) is ef-20 fected by a local bus adapter 30 which is contained within :~
i the service subsystem 9. Detailed logic structure for the ~ local bus adapter 30 is disclosed in the previously men-.~ tioned U. S. Patent No. 4,041,472 entitled "Data Processing :~ Internal Communications System Having Plural Time-Shared ! Intercommunication Buses and Inter-Bus Communication Means."
Additionally, the registers of the external register unit 1~ 28 may be employed to communicate with a plurality of peripheral subsystems represented by the logic block 32.
During normal data processing system operation, the service subsystem 9 is utilized as an input/output controller logically disposed between the peripherals represented by the block 32 and the internal transfer bus 2 and the ~.
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subsystems depending therefrom.
It will be observed that the service subsystem 9 can communicate with the system processor 1 through the ex-ternal register unit 28, the local bus adapter 30, and the internal transfer bus 2. In addition, however, more direct communication between the service subsystem 9 and the system processor 1 may be carried out over the serial ser-vice bus 10.
The external register unit 28 is also utilized ~,10 to couple an operator's console 34 to the service proces-sor. The primary switches and indicators for system start-up and control are located on the operator's console 34.
The operator's console 34 is also connected to the instruc-!tion counter 12 in order to force the instruction counter 12 to a predetermined memory location in the read-only memory sectlon 16 of the instruction memory 14 upon system initialization as will be discussed below. An interrupt logic block 38 also has the capability for forcing the in-struction counter 12 to predetermined locations in response to signals received external to the service subsystem 9.
Firmware for the entire system is permanently stored on a low speed magnetic medium known as a flexible disc or diskette which, with its associated electronics, ¦ is represented by the block 36 in Figure 2. The diskette may be manually removed and replaced by an operator.
~ When power to the system has been interrupted, ; whether deliberately or unexpectedly, the firmware within:
the firmware logic 44 of the system processor 1, the random access memory portion 18 of the instruction memory 14 (within the service processor), and other volatile firm-ware and controlware storage means in the diverse modules 40 contain random digital information. These firmware .
~- 10 --configured modules are thus completely inoperative at this time.
System startup is initiated by actuation of a power-on switch which is located on the console 34 or in any other convenient physical location according to the configuration of a specific system. In addition to the initiation of the usual powering-up activity such as pull-ing in power relays, starting the motors of rotating memor-ies, etc., actuation of the power-on switch issues a sig-nal to the instruction counter 12 within the service pro-cessor to force the instruction counter to a predetermined memory storage address (such as 00000) located within the read-only memory portion 16 of the instruction memory 14.
The predetermined memory storage location contains the first instruction of a simple bootstrap routing which func-tions, after determining that the diskette 36 has attained operating speed, to call in a loader routing from the diskette 36. This loader routine passes through the ex- . .
ternal register unit 28 into the random access memory por-.1 tion 18 of the instruction memory 14. When the entire loader routine has been obtained .
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~ 0 81 85 5 from the diskette 36, the bootstrap routlne branches to the first instruction of the loader routine which assumes control of the service processor. The loader routine is tailored to the individual system which it is prepared to conflgure: i.e., the loader routine contains, or has access to, information as to what specific firmware-configurable modules are coupled to the internal transfer bus 2 at specific ports of the bus.
The firmware logic 44 can be configured either through the serial service bus 10 or the internal transfer bus 2 where-as all other firmware-configurable modules ~ust be configured ` from the information contained on the diskette 36 through the internal transfer bus 2.
When all firmware or controlware configurable modules in the system, including the system processor, have been con-figured with the firmware information from the diskette 36, the ,, ~ service processor relinquishes system control to the system ~ ~
, .. .
processor 1. At this time, the service processor itself is re-configured to function as an input/output controller for the peripherals 32 by overlaying the loader routine in the random access memory portion 18 of the instruction memory 14 by the ; appropriate firmware from the diskette 36. Normal operation is then instituted.
It will be apparent that dynamic reconfiguration can be achieved by, for example, generating an interrupt signal from any appropriate location in the data processing system to the interrupt logic 38 of the service processor. If that specific interrupt forces the instruction counter 12 to the predeter-,i :
: mined memory storage location in the read-only memory 16 por-tion of the instruction memory 14 constituting the first in-struction in the bootstrap routine, the system will be recon-figured in the manner previously described with the firmware contained on the diskette 36 which, it will be understood, can be readily changed by simply substituting one diskette for a-nother prior to the occurrence of an interrupt or reinitiliza-tion.
Thu~, while the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifica-tions of structure, arrangement, proportions, elements, and components used in the practice of the invention which are partlcularly adapted for specific environments and operation requlremeDes wlthout deps-tlng from those prlnclples, j:~
.
The bus control logic 6 performs several functions.
It arbitrates all local bus adapter requests to use the internal 1, transfer bus on a fixed priority basis in the exemplary embodi-ment O The bus control logic also checks the parity of all messages sent over the internal transfer bus and reflects the 1 :~
. ~
,, . ., ~ ~ ' ~081855 result of the parity check onto the internal transfer bus for analysis by the communicating local bus adapters. The bus con-trol logic can communicate wlth the service subsystem 9 and the processor subsystem 1 by means of the serial service bus 10 in order to provide certain system condition history and status information and configuring signals. The internal transfer subsystems are synchronous logic machines in that all opera-tions in the internal transfer subsystems are synchronized with clock and phase signals emanating from the timing logic 7.
The inter-bus communications adapter S facilitates communications between the system components associated with the internal transfer bus subsystem 3 and the subsystems as-sociated with a second internal transfer bus subsystem 3' from ' which additional subsystems 11 depend.
~1~ Figure 2 is a block diagram of the service subsystem illustrating particularly the basic structure of the service ~ subsystem 9. The instruction counter 12 is a sixteen-bit ¦ counter which addresses the instruction memory 14 whereby the ,.. .
re6ultant memory data is made available to the service processor.
Two modes of operation are implemented for the instruction counter 12; viz.: increment and parallel load. Normally, the instructLon counter addresses consecutive memory locations in the instruction memory 14 by means of the increment mode. The parallel load mode is used to load and address into the in-struction counter during a branch operation to a non-consecu-tive memory location and also to effect system initiaIization as will be explained more fully below.
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,, : . ~ . ~. -: , ,. , ~ . . : .
108~855 The instruction memory 14 accepts a sixteen-bit memory address such that the maximum address allowable is 65,53510. The first 1024 memory addresses are allocated to a read-only memory section 16 of the instruction memory, and the remaining memory is contained in a random address section 18. The number of random access memory words actually implemented will depend on the characteristics of the given system in which the service subsystem 9 is resi-dent.
Instruction register 20 is an eighteen-bit regist-er which receives the sixteen-bit instruction being execut-ed as well as one parity bit on each of two instruction bytes. Instruction decoding logic 22 is employed to de-code the operation code portion of the instruction tem-porarily stored in the instruction register 20. The in-struction decoding logic 22 provides the control signals necessary to execute the specific instruction identified by the opcode. In a presently preferred embodiment of the service shbsystem 9, programmable read-only memory chips 20 are employed to effect the decoding in the instruction de- ;
coding logic 22.
The service subsystem 9 contains sixteen general I purpose registers contained in the register memory 24.
¦ These general purpose registers are allocated for use as ¦ accumulators, index registers, counters, etc. All arith-metic, shift, load and store operations involve one or ;
more of these registers. ~ ~;
'l The basic logic structure of the service proces-sor is oriented around a sixteen-bit arithmetic and logic unit 26. In the presently preferred embodiment of the service processor, the arithmetic and logic unit 26 com-prises a set of four, four-bit arithmetic logic unit/
1 ;
~, - , . . ,, : . :. . ~. :,. , :: , - . . ~ .
function generator integrated circuit chips wired in a carry-lookahead fashion. The arithmetic and logic unit 26 provides a carryout of the most significant bit and carryin to the least significant bit. The arithmetic and logic unit performs addition on two binary numbers in two's comple-. ment form, and subtraction of two binary numbers is ac-complished with two's complement addition as fo~lows:
A+(B+ carryin) where s is the one's complement of B, the complementing of B being performed internal to the arith-.¦ 10 metic and logic unit 26. Of course, those skilled in the art will appreciate that the specific manner by which arith-metic and logic unit 26 functions is not directly germane to the instant invention provided the capability is in-cluded in the service subsystem 9.
Data is transferred into and out of the service processor through the external register unit 28. The ad-dressing structure employed allows a possible 128 external registers in the external register unit 28. Communication to the internal transfer bus subsystem 2 (Figure 1) is ef-20 fected by a local bus adapter 30 which is contained within :~
i the service subsystem 9. Detailed logic structure for the ~ local bus adapter 30 is disclosed in the previously men-.~ tioned U. S. Patent No. 4,041,472 entitled "Data Processing :~ Internal Communications System Having Plural Time-Shared ! Intercommunication Buses and Inter-Bus Communication Means."
Additionally, the registers of the external register unit 1~ 28 may be employed to communicate with a plurality of peripheral subsystems represented by the logic block 32.
During normal data processing system operation, the service subsystem 9 is utilized as an input/output controller logically disposed between the peripherals represented by the block 32 and the internal transfer bus 2 and the ~.
.
~ , .
~ _ 9 _ .~ . . .
subsystems depending therefrom.
It will be observed that the service subsystem 9 can communicate with the system processor 1 through the ex-ternal register unit 28, the local bus adapter 30, and the internal transfer bus 2. In addition, however, more direct communication between the service subsystem 9 and the system processor 1 may be carried out over the serial ser-vice bus 10.
The external register unit 28 is also utilized ~,10 to couple an operator's console 34 to the service proces-sor. The primary switches and indicators for system start-up and control are located on the operator's console 34.
The operator's console 34 is also connected to the instruc-!tion counter 12 in order to force the instruction counter 12 to a predetermined memory location in the read-only memory sectlon 16 of the instruction memory 14 upon system initialization as will be discussed below. An interrupt logic block 38 also has the capability for forcing the in-struction counter 12 to predetermined locations in response to signals received external to the service subsystem 9.
Firmware for the entire system is permanently stored on a low speed magnetic medium known as a flexible disc or diskette which, with its associated electronics, ¦ is represented by the block 36 in Figure 2. The diskette may be manually removed and replaced by an operator.
~ When power to the system has been interrupted, ; whether deliberately or unexpectedly, the firmware within:
the firmware logic 44 of the system processor 1, the random access memory portion 18 of the instruction memory 14 (within the service processor), and other volatile firm-ware and controlware storage means in the diverse modules 40 contain random digital information. These firmware .
~- 10 --configured modules are thus completely inoperative at this time.
System startup is initiated by actuation of a power-on switch which is located on the console 34 or in any other convenient physical location according to the configuration of a specific system. In addition to the initiation of the usual powering-up activity such as pull-ing in power relays, starting the motors of rotating memor-ies, etc., actuation of the power-on switch issues a sig-nal to the instruction counter 12 within the service pro-cessor to force the instruction counter to a predetermined memory storage address (such as 00000) located within the read-only memory portion 16 of the instruction memory 14.
The predetermined memory storage location contains the first instruction of a simple bootstrap routing which func-tions, after determining that the diskette 36 has attained operating speed, to call in a loader routing from the diskette 36. This loader routine passes through the ex- . .
ternal register unit 28 into the random access memory por-.1 tion 18 of the instruction memory 14. When the entire loader routine has been obtained .
/
,` / ' '.
. / :
~ ~ .
.
~.
~ 0 81 85 5 from the diskette 36, the bootstrap routlne branches to the first instruction of the loader routine which assumes control of the service processor. The loader routine is tailored to the individual system which it is prepared to conflgure: i.e., the loader routine contains, or has access to, information as to what specific firmware-configurable modules are coupled to the internal transfer bus 2 at specific ports of the bus.
The firmware logic 44 can be configured either through the serial service bus 10 or the internal transfer bus 2 where-as all other firmware-configurable modules ~ust be configured ` from the information contained on the diskette 36 through the internal transfer bus 2.
When all firmware or controlware configurable modules in the system, including the system processor, have been con-figured with the firmware information from the diskette 36, the ,, ~ service processor relinquishes system control to the system ~ ~
, .. .
processor 1. At this time, the service processor itself is re-configured to function as an input/output controller for the peripherals 32 by overlaying the loader routine in the random access memory portion 18 of the instruction memory 14 by the ; appropriate firmware from the diskette 36. Normal operation is then instituted.
It will be apparent that dynamic reconfiguration can be achieved by, for example, generating an interrupt signal from any appropriate location in the data processing system to the interrupt logic 38 of the service processor. If that specific interrupt forces the instruction counter 12 to the predeter-,i :
: mined memory storage location in the read-only memory 16 por-tion of the instruction memory 14 constituting the first in-struction in the bootstrap routine, the system will be recon-figured in the manner previously described with the firmware contained on the diskette 36 which, it will be understood, can be readily changed by simply substituting one diskette for a-nother prior to the occurrence of an interrupt or reinitiliza-tion.
Thu~, while the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifica-tions of structure, arrangement, proportions, elements, and components used in the practice of the invention which are partlcularly adapted for specific environments and operation requlremeDes wlthout deps-tlng from those prlnclples, j:~
.
Claims (11)
1. A data processing system including: A) at least one firmware-configured module; B) first interchange-able storage means for permanently storing the system firm-ware; C) second storage means for permanently storing a program for accessing the system firmware stored in said first interchangeable storage means; and D) processing means responsive to the program stored in said second storage means for reading the system firmware from said first interchangeable storage means and configuring or reconfiguring said firmware-configured module.
2. The data processing system of Claim 1 in which said second storage means comprises non-volatile memory.
3. The data processing system of Claim 2 in which said processing means includes said second storage means.
4. The data processing system of Claim 2 in which said second storage means comprises a pre-programmed read-only memory.
5. The data processing system of Claim 4 which further includes third storage means, said third storage means comprising a read/write memory.
6. The data processing system of Claim 5 in which said third storage means comprises a firmware-con-figurable instruction memory.
7. The data processing system of Claim 6 in which a loader routine is stored in said first interchange-able storage means.
8. The data processing system of Claim 7 where-in said second storage means contains a bootstrap routine for reading said loader routine into said third storage means.
9. The data processing system of Claim 8 in which said processing means includes an instruction counter for addressing said third storage means and instruction de-coding means for generating control signals for executing instructions read from said third storage means.
10. The data processing system of Claim 9 in which said instruction decoding means comprises fourth storage means.
11. The data processing system of Claim 10 where-in said fourth storage means consists of a programmable read-only memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US68136476A | 1976-04-29 | 1976-04-29 | |
| US681,364 | 1976-04-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1081855A true CA1081855A (en) | 1980-07-15 |
Family
ID=24734974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA271,931A Expired CA1081855A (en) | 1976-04-29 | 1977-02-16 | Initializing means for a bus-oriented data processing system employing firmware-configured modules |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS52132646A (en) |
| CA (1) | CA1081855A (en) |
| DE (1) | DE2719199A1 (en) |
| FR (1) | FR2349880A1 (en) |
| GB (1) | GB1548497A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10339051B2 (en) | 2012-04-30 | 2019-07-02 | Hewlett Packard Enterprise Development Lp | Configurable computer memory |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4679166A (en) * | 1983-01-17 | 1987-07-07 | Tandy Corporation | Co-processor combination |
| US4590556A (en) * | 1983-01-17 | 1986-05-20 | Tandy Corporation | Co-processor combination |
| JPH06103460B2 (en) * | 1985-11-19 | 1994-12-14 | ソニー株式会社 | Program transfer method |
| FR2606566B1 (en) * | 1986-09-22 | 1993-04-30 | Nec Corp | INITIALIZATION METHOD FOR A CHANNEL CONTROLLER |
| US4803623A (en) * | 1986-10-31 | 1989-02-07 | Honeywell Bull Inc. | Universal peripheral controller self-configuring bootloadable ramware |
| JP3685931B2 (en) | 1998-07-31 | 2005-08-24 | 株式会社ソニー・コンピュータエンタテインメント | Information processing apparatus startup method, storage medium, and information processing apparatus |
-
1977
- 1977-02-16 CA CA271,931A patent/CA1081855A/en not_active Expired
- 1977-04-08 JP JP3958677A patent/JPS52132646A/en active Pending
- 1977-04-15 GB GB1576377A patent/GB1548497A/en not_active Expired
- 1977-04-29 DE DE19772719199 patent/DE2719199A1/en not_active Withdrawn
- 1977-04-29 FR FR7712929A patent/FR2349880A1/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10339051B2 (en) | 2012-04-30 | 2019-07-02 | Hewlett Packard Enterprise Development Lp | Configurable computer memory |
| US11615021B2 (en) | 2012-04-30 | 2023-03-28 | Hewlett Packard Enterprise Development Lp | Configurable computer memory |
| US11954029B2 (en) | 2012-04-30 | 2024-04-09 | Hewlett Packard Enterprise Development Lp | Configurable computer memory |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2719199A1 (en) | 1977-11-10 |
| JPS52132646A (en) | 1977-11-07 |
| GB1548497A (en) | 1979-07-18 |
| FR2349880B1 (en) | 1981-08-07 |
| FR2349880A1 (en) | 1977-11-25 |
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