CA1079793A - Single array ink jet printer - Google Patents
Single array ink jet printerInfo
- Publication number
- CA1079793A CA1079793A CA280,312A CA280312A CA1079793A CA 1079793 A CA1079793 A CA 1079793A CA 280312 A CA280312 A CA 280312A CA 1079793 A CA1079793 A CA 1079793A
- Authority
- CA
- Canada
- Prior art keywords
- media
- support
- ink jet
- drum
- nozzles
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J19/00—Character- or line-spacing mechanisms
- B41J19/16—Special spacing mechanisms for circular, spiral, or diagonal-printing apparatus
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/485—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by the process of building-up characters or image elements applicable to two or more kinds of printing or marking processes
- B41J2/505—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by the process of building-up characters or image elements applicable to two or more kinds of printing or marking processes from an assembly of identical printing elements
Landscapes
- Ink Jet (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Fax Reproducing Arrangements (AREA)
Abstract
SINGLE ARRAY INK JET PRINTER
ABSTRACT
An ink jet copier is provided with a document scanner which scans a document to be copied one line at a time producing non-coded binary data. The binary data is inserted in storage in a predetermined arrangement. Stored data is removed from selected predetermined locations in accordance with an algorithm and applied to a plurality of ink jet nozzles arranged in multiple linear arrays about the circumference of a rotating paper drum. The data signals selectively applied to the ink jet printers control the deposition of ink on the paper supported on the rotating drum to cause the reproduction of the original scanned image on a predetermined interlaced basis.
ABSTRACT
An ink jet copier is provided with a document scanner which scans a document to be copied one line at a time producing non-coded binary data. The binary data is inserted in storage in a predetermined arrangement. Stored data is removed from selected predetermined locations in accordance with an algorithm and applied to a plurality of ink jet nozzles arranged in multiple linear arrays about the circumference of a rotating paper drum. The data signals selectively applied to the ink jet printers control the deposition of ink on the paper supported on the rotating drum to cause the reproduction of the original scanned image on a predetermined interlaced basis.
Description
EIACKGROUND OF THE INVENTION
16 Field of the Invention 17 The invention relates to copiers in gen~ral and 18 more specifically to multiple nozzle ink jet copiers in ~ 19 which a plurality of ink jet nozzles are arranged ln a - , 20 plurality of linear arrays around the periphery of a rotating 21 medium ~upport drum and the scanned information from a ;
22 document i~ prearranged in memory and later tran3ferred.to 23 the linear arrays of nozzles at appropriate predetermined ~ 24 times to reproduce a copy of the ~canned document on a i 25 medium supported on the drum.
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~L0797~3 1 Description of the Prior Art -
16 Field of the Invention 17 The invention relates to copiers in gen~ral and 18 more specifically to multiple nozzle ink jet copiers in ~ 19 which a plurality of ink jet nozzles are arranged ln a - , 20 plurality of linear arrays around the periphery of a rotating 21 medium ~upport drum and the scanned information from a ;
22 document i~ prearranged in memory and later tran3ferred.to 23 the linear arrays of nozzles at appropriate predetermined ~ 24 times to reproduce a copy of the ~canned document on a i 25 medium supported on the drum.
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~L0797~3 1 Description of the Prior Art -
2 Ink jet copiers in general generate digital
3 information defining an image and applying the digital
4 information either directly to an ink jet printer or printers or indirectly applying the same via a memory storage device 6 which may or may not include rearrangement of the digital 7 information. In those instances where multiple ink jet 8 nozzles are employed, they may be arranged in a linear array 9 parallel to the axis of a drum which supports the paper or other medium on which the image is to be formed. As the 11 drum is rotated, the inX jet array is transported axially 12 and the digital information is used to selectively control 13 the ink jets to thus reproduce the image on the medium 14 supported on the drum.
In those instances where muLtiple nozzle arrays 16 are utilized, the images formed by each nozzle may follow 17 interlaced spiral patterns on the medium. A perfect inter-18 lacing pattern is necessary to assure complete coverage and 19 prevent double or multiple coverage of some areas on the medium. Several methods will provide such an interlace ~1 pattern of spirals.
22 The nozzle arrays may be fabrlcated such that the 23 center to center spacing of the nozzles is made equal to the 24 desired center to center spacing of the ink drops on the medium. This method provides automatic interlace, however, 26 the required nozzle spacing is impractical if high printing 27 resolution is required. Fabrication problems app~ar to .
28 render this solution unacceptable since the spacing, for any reasonable degree of resolution, is inadequate to accommodate 2 the structural elements required to implement the required 3 function.
4 Larger nozzle spacing in the array nnay be attained by angling the array with respect to the drum axis since the 6 angling provides a closer axial drop spacing at the same 7 time that it permits a larger nozzle spacing; however, this 8 solution in~roduces a new problem. When the nozzle array i~
g at an angle to the drum axis, the drops from the different nozzles in the array have different flight times due to the 11 different distances to the drum surface. This produces 12 varying degrees of drop misplacement depending on the number 13 of nozzles and their spacing in the array. The problem of 14 different flight tlmes can be avoided by arranging the nozzles on a curved support,plate which follows ~he drum 16 contour so that all of the nozzles are equidistant from the 17 drum surface. This solution is far from ideal since it 18 requires a structure which is difficult to manufacture and 19 align.
,The nozzles and arrays may be staggered to provide 21 additional space. However, this solution leads to additional 22 problems in the areas of, driver uniformity, deflection when ' ' 23 two or more rows are used, and guttering problems.
24 A more desirable solution would permit complete freedom on the center to center spacing of the nozzles which 26 would allow a center to center nozzle spacing larger BO976034 ~3~
~L0~9~79;3 1 than the center to center spacing of the drops on the paper in the axial direction with negligible sacrifice of either printing speed or resolution. Such a solution would ease the fabrication of the nozzles and permit a much wider choice of existing nozzle technologies, such as glass drawn nozzle arrays or etched amorphous material arrays, all of which require substantial spacing. In addition, freedom of spacing minimizes problems in charge electrode packaging, guttering deflection systems and other problems related to electrical crosstalk are more readily solved.
Summary of the Invention The invention contemplates a multiple nozzle ink jet copier in which digital information signals represen tative of an image to be reproduced are received from a line scanner or the like. The signals are stored one line at a time in one of two temporary memories on an alternating basis under control of clocking signals supplied by a clock generator. The signals stored in the temporary memories are, under control of an address generator, stored in pre-determined locations in a main memory. The address signalsused for selecting the information signals to be stored and the locations in main memory for storing the selected sig~
nals are generated from the clock signals and are represen-tative of line, nozzle and main memory word locations expressed as modular displacements from a reference. The information signals stored in the main memory are accessed under control of address signals generated by an output address generator means under control of the clock and a drum sync signal provided by the paper support drum system.
30 The drum sync ~0797~3 1 signal occurs NT times per drum revolution where NT is equal 2 to the total number of nozzles in the nozzle arrays. The 3 information signals read from the memory are stored in 4 selected regi~ters for controlling the associated ink jet nozzles. The nozzles are arranged in a plurality of linear 6 arrays about the periphery of the paper support drum and 7 provide an interlaced image on the paper when the drum is 8 rotated and the nozzle arrays are simultaneously transported 9 in an axial direction. The nozzles in the arrays are spaced k resolution elements apart and the array advances NT reso-11 lution elements in the axial direction in each drum revolu-12 tion.
1~ Brief Description of the Drawings 14 Figure 1 is a block diagram of a complete ink jet copier constructed according to the invention.
16 Figure 2 is a schematic diagram of the nozzle 17 array and drum illustrated in Figure 1;
18 Figure 3 is a perspective view of the drum shown 19 in Figure l;
Figure 4 is a schematic diagram illustrating the 21 segments and lines printed and identifies the various 22 nozzles and arrays which print the various segments;
23 Figure 5 is a schematic diagram of the clock shown 24 in Figure 1 and includes graphical representations of the outputs from the clock;
26 Figure 6 is a detailed block diagram of the Source 27 Organizer illustrated in Figure l;
28 Figure 7 is a detailed block diagram of the Signal 29 Value Generator shown in Figure l;
BO976034 ~5~
~L~'79793 1 Figure 8 is a block diagram of the array registers and switch shown in Figure l;
Figure 9 is a block diagram of the Address Gen-erator illustrated in Figure l; and Figure 10 is a graphical representa-tion of timing relatlonships utilized in the circuits illustrated.
~escription of the Preferred Embodiments Figure l is a block diagram of an ink jet copier and includes a document scanner ll arranged to scan a document which ic to be copied. The document scanner ll may take any form, preferably the document scanner should be arranged to scan serial horizontal lines in succession down the length of the document ancl provide a serial data stream indicative of the image content of the document on a line by line basis. Document scanner 11 is controlled by a line synchronizing clock signal generator 12. The line synchro--nizing signals cause the document scanner to scan one line at a time upon the occurrence of each of the line synchro-nizing signals. The data clocking signals provide the bit in~ormation. Typically, document scanner 11 will provide 40 lines in 257 mils of document length and the data clock willprovide 1400 information bits in each o~ the scanned lines.
The values set forth above are typical for an ink jet copier if constructed in accordance with the invention described in the specification. Obviously, these values may be varied over a wide range depending upon the resolution required in the copy.
The non-coded video data from the document scanner 11 is applied to the data input of a source organizer 14.
The source organizer 14 performs several functions which ~LC179793 1 will be descrlbed below. The details of source organ-izer 14 are illustrated in Figure 6 and the detailed description of how source organizer 14 performs its func-tion will be described in connection with the descrip-tion of Figure 6.
Source organizer 14 is provided internally with two memory areas. The successive lines of data from scanner 11 are stored in these two memory locations accord-ing to a predetermined scheme. The data on the first line, for example, is stored in the first storage location. After this data has been received, the data from the second line is stored in the second storage location. While the second line is being stored in the second location, the data pre-viously stored in the first location is selectively in- :
serted into the main memory 15. The source organizer 14 utilizes four control signals provided by clock generator 12 and three additional signals provided by a signal value generator circuit 16. In addition to the data clock and line sync signals applied to document scanner 11, source organizer 14 receives a cycle clock signal and an array clock signal A from the clock generator circuit 12. The three signals received from the input signal value generator circuit 16 are a line value labeled L, a nozzle value labeled N, and a word value labeled W. The .:
signal value generator 16 receives the line sync and data clock signals from clock generator 12 and preset vaIue signal stored in a register 17. Input signal value generator 16 is illustrated in detail in Figure 7, and a description of the operation of this circuit will be given in conjunction with the description of Figure 7.
The contents of register 17 represent misalignment of the paper or media 24 with respect BO9~76-034 -7-~79793 1 to a mounting drum or media support 22 on which and with respect to which the image is generated. If no misalign-ment is present, the value stored in re~ister 17 is zero.
The data stored in source organizer 1~ is presented to the main memory 15 based on the input: signals from clock generator 12 and signal value generator 16. The actual storage locations selected are determined by an address generator 18 which responds to the L, N and W signals from signal value generator 16 by generating the addresses with-in which the data presented by source organizer 14 will be located. Address generator 18 provides an output which is inserted in an address register 19 which actually controls the locations within main memory lS where the data from source organizer 1~ is inserted. Address generator 18 is shown in greater detail in Figure 10 and will be described in conjunction with the description of Figure 10.
The image data stored in main memory 15 is appliedone word at a time via a switch 20 under control of the nozzle value N from signal value generator 16, tQ the arrays 21A through E. The stored signals control the noz-zles associated with each of the five arrays, thus con-trolling the deposition of ink on the media mounted on the drum 22. The arrays are driven by an array drive 23 in an axial direction along the drum periphery. Thus, each nozzle describes a spiral about the drum selectively modulating the ink deposited by the nozzles as the nozzle array is driven axially and the drum is driven in a rotary direction which causes the image to appear on the media 24 mounted on the drum 22. The arrays 21A through 21E
are shown in greater detail in Figure 2A and Figure 2B
will be described in BO9-76-03~ -8-~L079~93 1 conjunction with the descriptions of these figures.
2 A read/write control signal from clock 12 is 3 applied to main memory 15; and as each memory address ls 4 generated ~y address generator 18, as described above, a
In those instances where muLtiple nozzle arrays 16 are utilized, the images formed by each nozzle may follow 17 interlaced spiral patterns on the medium. A perfect inter-18 lacing pattern is necessary to assure complete coverage and 19 prevent double or multiple coverage of some areas on the medium. Several methods will provide such an interlace ~1 pattern of spirals.
22 The nozzle arrays may be fabrlcated such that the 23 center to center spacing of the nozzles is made equal to the 24 desired center to center spacing of the ink drops on the medium. This method provides automatic interlace, however, 26 the required nozzle spacing is impractical if high printing 27 resolution is required. Fabrication problems app~ar to .
28 render this solution unacceptable since the spacing, for any reasonable degree of resolution, is inadequate to accommodate 2 the structural elements required to implement the required 3 function.
4 Larger nozzle spacing in the array nnay be attained by angling the array with respect to the drum axis since the 6 angling provides a closer axial drop spacing at the same 7 time that it permits a larger nozzle spacing; however, this 8 solution in~roduces a new problem. When the nozzle array i~
g at an angle to the drum axis, the drops from the different nozzles in the array have different flight times due to the 11 different distances to the drum surface. This produces 12 varying degrees of drop misplacement depending on the number 13 of nozzles and their spacing in the array. The problem of 14 different flight tlmes can be avoided by arranging the nozzles on a curved support,plate which follows ~he drum 16 contour so that all of the nozzles are equidistant from the 17 drum surface. This solution is far from ideal since it 18 requires a structure which is difficult to manufacture and 19 align.
,The nozzles and arrays may be staggered to provide 21 additional space. However, this solution leads to additional 22 problems in the areas of, driver uniformity, deflection when ' ' 23 two or more rows are used, and guttering problems.
24 A more desirable solution would permit complete freedom on the center to center spacing of the nozzles which 26 would allow a center to center nozzle spacing larger BO976034 ~3~
~L0~9~79;3 1 than the center to center spacing of the drops on the paper in the axial direction with negligible sacrifice of either printing speed or resolution. Such a solution would ease the fabrication of the nozzles and permit a much wider choice of existing nozzle technologies, such as glass drawn nozzle arrays or etched amorphous material arrays, all of which require substantial spacing. In addition, freedom of spacing minimizes problems in charge electrode packaging, guttering deflection systems and other problems related to electrical crosstalk are more readily solved.
Summary of the Invention The invention contemplates a multiple nozzle ink jet copier in which digital information signals represen tative of an image to be reproduced are received from a line scanner or the like. The signals are stored one line at a time in one of two temporary memories on an alternating basis under control of clocking signals supplied by a clock generator. The signals stored in the temporary memories are, under control of an address generator, stored in pre-determined locations in a main memory. The address signalsused for selecting the information signals to be stored and the locations in main memory for storing the selected sig~
nals are generated from the clock signals and are represen-tative of line, nozzle and main memory word locations expressed as modular displacements from a reference. The information signals stored in the main memory are accessed under control of address signals generated by an output address generator means under control of the clock and a drum sync signal provided by the paper support drum system.
30 The drum sync ~0797~3 1 signal occurs NT times per drum revolution where NT is equal 2 to the total number of nozzles in the nozzle arrays. The 3 information signals read from the memory are stored in 4 selected regi~ters for controlling the associated ink jet nozzles. The nozzles are arranged in a plurality of linear 6 arrays about the periphery of the paper support drum and 7 provide an interlaced image on the paper when the drum is 8 rotated and the nozzle arrays are simultaneously transported 9 in an axial direction. The nozzles in the arrays are spaced k resolution elements apart and the array advances NT reso-11 lution elements in the axial direction in each drum revolu-12 tion.
1~ Brief Description of the Drawings 14 Figure 1 is a block diagram of a complete ink jet copier constructed according to the invention.
16 Figure 2 is a schematic diagram of the nozzle 17 array and drum illustrated in Figure 1;
18 Figure 3 is a perspective view of the drum shown 19 in Figure l;
Figure 4 is a schematic diagram illustrating the 21 segments and lines printed and identifies the various 22 nozzles and arrays which print the various segments;
23 Figure 5 is a schematic diagram of the clock shown 24 in Figure 1 and includes graphical representations of the outputs from the clock;
26 Figure 6 is a detailed block diagram of the Source 27 Organizer illustrated in Figure l;
28 Figure 7 is a detailed block diagram of the Signal 29 Value Generator shown in Figure l;
BO976034 ~5~
~L~'79793 1 Figure 8 is a block diagram of the array registers and switch shown in Figure l;
Figure 9 is a block diagram of the Address Gen-erator illustrated in Figure l; and Figure 10 is a graphical representa-tion of timing relatlonships utilized in the circuits illustrated.
~escription of the Preferred Embodiments Figure l is a block diagram of an ink jet copier and includes a document scanner ll arranged to scan a document which ic to be copied. The document scanner ll may take any form, preferably the document scanner should be arranged to scan serial horizontal lines in succession down the length of the document ancl provide a serial data stream indicative of the image content of the document on a line by line basis. Document scanner 11 is controlled by a line synchronizing clock signal generator 12. The line synchro--nizing signals cause the document scanner to scan one line at a time upon the occurrence of each of the line synchro-nizing signals. The data clocking signals provide the bit in~ormation. Typically, document scanner 11 will provide 40 lines in 257 mils of document length and the data clock willprovide 1400 information bits in each o~ the scanned lines.
The values set forth above are typical for an ink jet copier if constructed in accordance with the invention described in the specification. Obviously, these values may be varied over a wide range depending upon the resolution required in the copy.
The non-coded video data from the document scanner 11 is applied to the data input of a source organizer 14.
The source organizer 14 performs several functions which ~LC179793 1 will be descrlbed below. The details of source organ-izer 14 are illustrated in Figure 6 and the detailed description of how source organizer 14 performs its func-tion will be described in connection with the descrip-tion of Figure 6.
Source organizer 14 is provided internally with two memory areas. The successive lines of data from scanner 11 are stored in these two memory locations accord-ing to a predetermined scheme. The data on the first line, for example, is stored in the first storage location. After this data has been received, the data from the second line is stored in the second storage location. While the second line is being stored in the second location, the data pre-viously stored in the first location is selectively in- :
serted into the main memory 15. The source organizer 14 utilizes four control signals provided by clock generator 12 and three additional signals provided by a signal value generator circuit 16. In addition to the data clock and line sync signals applied to document scanner 11, source organizer 14 receives a cycle clock signal and an array clock signal A from the clock generator circuit 12. The three signals received from the input signal value generator circuit 16 are a line value labeled L, a nozzle value labeled N, and a word value labeled W. The .:
signal value generator 16 receives the line sync and data clock signals from clock generator 12 and preset vaIue signal stored in a register 17. Input signal value generator 16 is illustrated in detail in Figure 7, and a description of the operation of this circuit will be given in conjunction with the description of Figure 7.
The contents of register 17 represent misalignment of the paper or media 24 with respect BO9~76-034 -7-~79793 1 to a mounting drum or media support 22 on which and with respect to which the image is generated. If no misalign-ment is present, the value stored in re~ister 17 is zero.
The data stored in source organizer 1~ is presented to the main memory 15 based on the input: signals from clock generator 12 and signal value generator 16. The actual storage locations selected are determined by an address generator 18 which responds to the L, N and W signals from signal value generator 16 by generating the addresses with-in which the data presented by source organizer 14 will be located. Address generator 18 provides an output which is inserted in an address register 19 which actually controls the locations within main memory lS where the data from source organizer 1~ is inserted. Address generator 18 is shown in greater detail in Figure 10 and will be described in conjunction with the description of Figure 10.
The image data stored in main memory 15 is appliedone word at a time via a switch 20 under control of the nozzle value N from signal value generator 16, tQ the arrays 21A through E. The stored signals control the noz-zles associated with each of the five arrays, thus con-trolling the deposition of ink on the media mounted on the drum 22. The arrays are driven by an array drive 23 in an axial direction along the drum periphery. Thus, each nozzle describes a spiral about the drum selectively modulating the ink deposited by the nozzles as the nozzle array is driven axially and the drum is driven in a rotary direction which causes the image to appear on the media 24 mounted on the drum 22. The arrays 21A through 21E
are shown in greater detail in Figure 2A and Figure 2B
will be described in BO9-76-03~ -8-~L079~93 1 conjunction with the descriptions of these figures.
2 A read/write control signal from clock 12 is 3 applied to main memory 15; and as each memory address ls 4 generated ~y address generator 18, as described above, a
5 - read cycle is executed causing the contents of the memory
6 location to be applied to the arrays as described above.
7 The read cycle is followed by a write cycle in which the new
8 image information is stored in the address indicated by
9' address generator 18. This information will be supplied to the nozzle arrays the next time this address in main memory 11 15 is accessed. A drum sync signal is applied to clock 12 generator 12 and causes the line sync signal issued there-13 ~rom to be synchronized to the drum sync signal, thus the 14 data from document scanner 11 cannot fall behind or get ahead of the printing which occurred on the media 24. This 16 prevents underruns and overruns of data in memory 15, thus 17 reducing the required amount of storage. The details of 18 output signal value generator 16 are illustrated in Figure 7 19 and will be described in conjunction with the description of that figure,. Switch 20 and the data registers associated 21 with arrays 21A through E are shown in greater detail in 22 Figure 8 and will be described in conjunction with the 23 description of that figure.
24 Figures 2 and 2A illustrate the drum, the array mountings and the array drive. The drum 22 is supported for 26 rotation by structures not shown. Adjacent to the periphery 27 of the drum is an array drive motor 28 which drives a lead 28 screw 29. The array support 30 is mounted on the lead screw 29 29 and travels in an axial direction along the drum surface 0 on the screw 29. Forty ink jet nozzles 31 illustrated BO976034 ~9~
~V797~3 1 schematically are supported on the array support 30. They are arranged in five linear groups of eight each. The details of the ink jet nozzles and the associated ink jet printer mechanisms have been intentionally deleted since conventional ink jet nozzles and ink jet printers may be utilized with this invention because the placement of the nozzles on the nozzle support 30 is substantially unrestrict-ed. The specific nozzle arrangement described above is exemplary only. A large number of nozzle arrangements may be selected when the rules set forth belo~ are followed.
According to the invention the center to center spac-ing of the nozzles in each of the arrays is virtually without restraint since adjacent nozzles are not required to cover adjacent segments o~ the circumference of the drum. Each of the circumferential :Lines around the drum is divided into equa~ length segments and the number of segments selected equals the total number of nozzles and the lines are spaced one resolution element apart. This criteria permits the spacing of the nozzles to be larger than the center to center spacing of the drops or the lines on the paper with a negligible sacrifice of either printing speed or resolution. In addition, it permits fabrication of nozzles using a much simpler process since spacing constraints may be eliminated. This consideration broadens the number of useful ink jet nozzle technologies available. For example, glass-drawn nozzle arrays or etched amorphous materials may be utilized since these are currently limited to larger spacings. In addition, the charge electrode packaging guttering deflection sys-tem and problems related to electrical cross tal}c be-come much easier to solve. The techniques described may be l utilized in eith~r single or multiple array cGpierS. Memory 2 requirements, such as are present in the main memory 15, are 3 mlnimized by using multiple arrays of nozzles positioned 4 around the circumference of the drum as illustrated in Figure 1, provided these are properly interlaced. This is 6 due to the fact that the memory storage required is directly 7 related to the axial length subtended by the arrays.
~ In considering the placement of nozzles in an 9 array, two cases must be looked at, the single array and plural arrays spaced around the drum periphery.
11 In a single array comprising N nozzles spaced k 12 resolution elements apart, the criteria for interlace is as 13 follows where N and k are both integers.
14 l) The nozzle array must advance in the axial direction N resolution element~ per single revolution of the 16 print drum.
17 2) For k factorable into prime factors such that 18 k = AxBx ..... x M, N must be an integer which has no prime 19 factors in common with k, i.e, the fraction k/N must be irreducible.
21 In accordance with the above, the first nozzle 22 prints, for exampler segment l for a given scan line, the 23 second nozzle segment l + k, the third l + 2k, etc. in order 2~ for all segments to be printed with no overprinting of any segment, the first segment must not be reached again in the 26 above sequence until 1 + Nk. Examples of k and N combination~
27 which will interlace are given below.
28 1) k=2, N includes the set of all odd integers.
29 2) k=3, N includes the set of all integers which are not multiples of 3.
1~79793 1 3) k=4, N includes the set of all odd integers.
2 4) k-S, N includes the set of all integers which 3 are not multiples of S.
4 5) k=30 [2x3x5], N includes the set of all odd integers which are not multiples of 3 or 5. If the fraction 6 k/N is reducible, the nozzle array will not interlace and 7 double printing or missed areas will result.
8 The second case considered and illustrated in 9~ Figure 1 and Figure 2 is that of multiple arrays of plural nozzles. A multiplicity of M identical nozzle arrays having 11 a total of NT nozzles are shown in ~igure 2. The nozzles 12 are spaced K resolution elements apart in the array. M, the 13 number of arrays, N, the number o nozzles per array, and k, 14 the multiple of the resolution elements are all integers.
The criteria for interla~e is as follows.
16 1) The nozzle transport must advance in the axial 17 direction NT resolution elements per revolution where NT is 18 the total number of nozzles.
19 2) The fraction Tk/M divided by TN must be irreduc-ible. The numerator and denominator must have no common 21 prime factors. T is the smallest integer between 1 and Mr 22 such that Tk/M is also an integer (it follows that M~T is 23 also an integer). The value of T required to satisfy the 24 above expressions indicates the necessity of pairing of nozzle arrays. If T equals 1, there is no constraint on the 26 arrays as to pairings. If T equals 2, the arrays must be 27 even in number and paired in two groups displaced fro~ each 28 other by 180~. If T equals 3, the number of arrays must be 29 a multiple of three and arranged in three groups spaced 120 apart. In a multiple array where T equals 2, the pairs of -~79793 1 array groups must be spaced 180 apart; however, the spaclng~
2 within each group will be dictated by other re~uirements, 3 namely, where on the drum the array segments are to begin.
4 This will be treated in greater detall when the specific embodiment disclosed is described.
6 An array arrangement may be selected according to 7 the steps set forth below.
8 1) The desired value for k is chosen to pro~ide g the desired resolution according to the expression l/reso-lution = nozzle spacing/k.
11 2) Select the number of arrays desired M.
12 3) Solve the fraction set Eorth above to determine 13 the value of T and khe allowable number of nozæles N. Find 14 the minimum T satisf~ing Tk/M eqllals an integer and determine that ~he equation set forth above is irreducible.
16 4) For a minimum print buf~er or main memory 17 requirement a~l arrays should be aligned in the axial direction 18 to a common circumferential line as illustrated in Figure 2.
19 The arrays need not necessarily be axially aligned to a common circumferential line. In this case the axial align-21 ment can be traded for spacing between arrays. ~owever, if 22 they are not aligned, interlacing will nevertheless occur 23 but increased main memory will be required in all instances 24 where information i5 being scanned and printed at the same time. The angular spacing for axially aligned arrays may be 26 any multiple of 360/NT which is not a multiple of 360 27 x K/NT from any other array where 360/NT corresponds to 28 one segment.
29 In the illustrated embodiment, five arrays, 21A
through 21E, are used. Each of these arrays include eight 31 nozzles 31. The nozzles in the arrays are spaced flLve ~Og7603~ -13-. . - ~
1 resolution elements apart, thus the values given above are M
2 = S, ~ = S, N = 8, NT = 40 When these va:Lues are substituted 3 in the equation given above, T has a value of 1, th~s the 4 arrays are not paired and may be angularly spaced according to the description above. An angular spacing between arrays 6 of 9~ was selected. 9~ of all the possible orientations was 7 selected since it permits an easier visualization o operation, 8 A selection of 54 is also an excellent choice since it 9 provides adequate space between arrays for the ink iet nozzles hardware yet has adequate space opposite the arxays 11 for installing papPr handling equipment to permit paper to ~ be automatically or manually added to the drum and removed.
13 Figure 3 illustrates the drum 22 with the paper 24 14 mounted on it and the drum sync generator 27. The drum sync generator includes the disc 32 having 40 scribed transparent 16 lines thqrein arranged around the periphery of the disc.
17 The disc 32 lS attached to the drum 22 and rotates therewith 18 between a light source 33 and a detector 34. When the light 19 from source 33 is detected by the detector 34, the drum sync 2n signal is provided by detector 34. This signal is applied 21 to the clock generator circuit 12 illustrated in Figure 1.
22 Figure 4 illustrates 40 scan lines as reproduced 23 on the drum. Each of the 40 scan lines includes 40 segments.
24 The drawing in Figure 4 is grossly distorted in order to present the information in a manner which is clearly under-26 stood. The 40 scan lines typically occupy 257 mils on the 27 drum or paper mounted thereon. The drawing contains a ~28 series of numbers. The first digit of each of the double 29 digit numbers represents the array number. The second digit of the double digit numbers represents the nozzle number 3LO'7~793 1 within the array which produced the image in that parti-cular seyment. Each of the double digit numbers is co-extensive with one of the segments. Thus, in the first scan line the first segment is produced by the first noz-zle of the first array and the number is 11. The second segment of the first line is produced by the first nozzle of the second array. The third segment is produced by the first nozzle of the third array, the fourth segment by the first nozzle of the fourth array, and the fifth segment by the first nozzle of the fifth array. The second noz-zle of the first array reproduces the sixth segment on the first scan line. The sequence continues throughout the scan line. The eighth nozzle of the fifth array repro-duces the first segment of the second scan line and all of the other nozzles in arrays are displaced one segment to the right. Subsequent lines are produced in the same manner with the segments produced by the nozzles precess-ing to the right and moving back to the left when the 40th segment was done on the preceding line. The entire pattern illustrated occupies a single revolution of the drum. On a subsequent revolution of the drum another 40 scan lines are produced. The 40 lines illustrated in Figure 4 are, as previously stated, distorted and on:Ly occupy approximately 257 mils of space in khe vertical direction on the paper on which the image is being pro-duced. The width, however, is substantially as illustrated in Figure 4. A complete page, of course, will require many reproductions one after the other of the 40 lines illustrated in Figure 4.
3n ' .: ' ` ' ' . ~ ' ~7~793 1 Figure 5 is primari'y intended to illustrate the outputs from clock generator 12 shown in Figure 1. The clock includes a master oscillator 35 and the necessary counting and logic circuits 36 for producing the four outputs illustrated in response to the drum sync signal supplied by the drum sync generator 27 of ~igure 1. The details of clock 12 are not illustrated here because con-ventional circuits may be utilized for providing the clock signals illustrated in Figure 5. These, typically, will include counting circuits, logic circuits, differentia-tors and integrators for operating on the pulses from the master oscillator 35 to provide the oùtputs illustrated in Figure 5.
The drum sync signal ~rom drum sync generator 27 is provided once per one-fortieth revolution of the drum 22.
This signal causes the issuance of the line sync signal from clock 12, thus the line sync signals are produced substantially coextensively with the drum sync signal.
1400 data clock signals are produced between each line sync signal to thus provide the 1400 bits per scan line pre-viously referred to. In addition, the period between line sync signals incl~des 56 cycle clocks. The cycle clock signals may or need not necessarily be symmetric. If the two processing times for the source organizer 14 are sym-metric, then the signal may be symmetric. However, if the reading operation requires more time than the writing operation, this may be accommodated by making the cycle clock signals asymmetric within each of the 56 cycles.
The array clock signal includes five pulses 1~7~793 1 during the positive cycle of each of the cycle clock cycles yielding 280 pulses between successive llne sync signals.
The source organizer 14 of Figure 1 is illustrated in greater detail in Figure 6. The data signals from the scanner 11 are applied to a shift register 37 and shifted in under control of the data clock signal from clock 12.
Shift register 37 stores five bits and is provided with five parallel outputs which are applied via a gate cir-cuit 38 and a switching circuit 39 to one or the other of two input data registers 40 and 41 associated with ran-dom access memory cells 42 and 43 respectively. The data signals are shifted into shift register 37 under control of the data clock signals from clock 12. In addition, the data clock signals are applied to a 1-5 counter 44.
At the count of five, counter 44 provides a signal which enables gate 38 and resets counter 44. When gate 38 is enabled, the contents of shift register 37 are applied in parallel to switch 39. Depending on the state of the control signal, the contents of shift register 37 are applied to either input data register 40 or input data register 41. The control signal applied to switch 39 is generated by a trigger circuit 45 which is toggled by the line sync signal from the clock 12. Thus, the control output from trigger 45 changes state with each line sync signal. During one line period the contents of shift register 37 are applied successively each five bit period to input data register 40 whereas during the ne~t line period the contents are applied serially five bits in parallel to input data register 41.
~09-76-034 -17-,. .
~079793 1 The contents of input data registers 40 or 41 are stored in memories 42 and 43 respectively at locations defined by the contents of address registers 46 and 47 respectively. The actual address inserted in either register 46 or 47 depending upon the state of ~rigger 45 is generated by a counter 48 which responds to the output of counter 44. Counter 48 counts from 1 to 280 since 280 is the maximum number of addresses required in memories 42 and 43. This quantity will accommodate 1400 bits in a single scan line since 280 addressable positions each containing five bits equals the 1400 bits per line stored. The output of counter 48 is applied via a switch 49 to either register 46 or 47 depending upon the state of the control signal from trigger 45. When the control signal occupies one state t~e contents o~ counter 48 will be inserted in register 46 and when the control signal occupies the opposite state the contents will be inserted in register 47. Registers 46 and 47 and 40 and 41 operate in synchronism under control of the control signal ~rom trigger 45 to cause the contents of the scanned ~ine to be inserted alternately in memories 42 and 43. A decod-ing circuit 50 responsive to the output of counter 48 decodes the count of 280 and resets counter 48 so that it is prepared to process the next scanned line. This completes the description of Figure 6 insofar as receiv-ing data from the scanner and inserting the received data into the memories 42 and 43 on an alternating line basis.
The remainder of the description which follows will be concerned with removing the contents from memories 42 and 43 and inserting those contents in the appropriate :
places in main memory 15.
BO9-76-034 ~ -18-1~797~3 The contents of memories 42 and 43 are made avail-able in output data registers 51 and 52 respectively.
Memories 42 and 43, depending upon the particular type BO9-76-034 -18a-1 selected, may be controlled by the output of trigger cir-cuit 45 as to which will be in a read and which will be in a write cycle since these cycles are opposite at any given time for the two memories, i.e., when the data from the line scanner is being stored in memory 42, the con-tents of memory 43 which represent the data from the pre vious scan line will be read out into output register 52 and inserted as will be described below in main memory 15.
Output registers 51 and 52 are connected by a switch 53 and five gates 54-1 through 54-5 to a data input register 55 associated with main memory 15. The operation and function of gates 54-1 through 54-5 will be described below.
The A clock signal from clock 12 is applied to a counter 56 w~ich counts 1 through 5 and is reset~ 'I'he outputs illustrated of counter 56 provide an indication of the count. These are labeled A and will be used elsewhere in this circuit and described later on. These outputs are also applied to a decoder circuit 57 which decodes the actual count A-l through A-5 and resets the counter 56 following the occurrence of the A-5 count.
The outputs of decoder 57, A-l through A-5, are applied to the gates 54-1 through 54-5, respectivel~v, thus the first five bits from memory 42 or memory 43 are applied via gate 54-1 to the first five positions of the input register 55. The second group of five bits are applied ~ia gate 54-2 to the second five bit positions in input data register 55, etc. until the last group of five bits are inserted in the last five positions of input register 55. Referring back to Figure 5, it should be notecl that the A clock or array clock contains five pulses in one-half of the cycle clock p,~riod. This is ~9793 1 necessary since five addresses in memories 42 or 43 must be processed during one clock cycle period because the word length in main memory 15 is 25 bits and that in memories 42 and 43 is five bits. Thus, the contents of five addresses in memories 42 or 43 are assembled in the input data register 55 during each cycle clock for later insertion into memory 15. These are assembled under con-trol of the counter 56 and decoder 57.
An address generator 58 receives the output from counter 56, the L, N, and W outputs from signal value generator 16 and computes the address as indicated in the expression in the drawing. The computed address is applied via a switch 59 under control oE the control out-put from trigger 45 to either register 46 or 47 depending upon the state of trigger 45. It should be noted that the address from counter 48 and the address from generator 58 will be applied to different registers 46 and 47 because the control signals from trigger 45 are of opposite s~ates and are applied to switches 49 and 59 respectively. Thus, data will be written into one memory while it is being removed from the other memory and the roles will reverse with each successive line sync signal. The implementa-tion of address generator 58 should be obvious to those skilled in this art. Typically, this address generator will be constructed from conventional solid state cir-cuits to specifically provide the output indicated from the inputs provided. A general purpose computer could be used. ~owever, the speed required and the limited function required would militate in most instances against such a choice.
Figure 7 is a detailed diagram of the signal 1 value generator 16 illustrated in Figure 1. The data clock signals are applied to an A counter 60 which is provided with five counting stages having paired outputs Al, A2, A4, A8 and A16. The outputs Al, A2, A4, A8 and A16 are applied via an AND gate 61 to the reset input of counter 60. Thus, counter 60 rese-ts aflter counting 25 data clock pulses. This corresponds to the number of bits in a word in main memory 15. The output of AND gate 61 is connected to a B counter 62 which has three stages to provide word count W which ranges from 1 through 7 or, stated differently, 0 through 6. The outputs Bl, B2 and B4 of B counter 62 are connected to an AND gate 63 which has its output connected to the reset input counter 62. The output of AND gate 63 is also connected to an E counter 6 which has four stages, the outputs of which are lab~lled El, E2, E4 and E8. These constitute the nozzle val~e N, the outputs El, E2, E4 and E8 are connected to an AND
gate 65 which has its output connected to the reset input of counter 64 which counts to 8, and resets, thus prov-iding an output indicative of the eight nozzle values.
The preset value stored in register 17 of Figure 1 is applied to preset an F counter 66. The line sync signals from the clock 12 of Figure 1 are applied to the step in-put of counter 66 which has six stages and provides the line count L. The Fl, F2, F4, F8, F16 and F32 outputs of counter 66 are applied via an AND gate 67 to the reset ~-input of counter 66. Thus, counter 66 counts from 1 through 40 to indicate which of the 40 scan lines are being pro-cessed. Obviously, many more than 40 lines are processed.
However, they are treated as groups of 40 by the circuits described above.
~0~97g3 1 Figure 8 illustrates some of the details of the arrays 21A through 21E and the relationship of switch 20 thereto. Switch 20 is connected to the output regis-ter associated with main memory 15 and receives 25 bits in parallel therefrom. In addition, it receives the N
signal from signal value generator 16. Each o~ the arrays 21 includes 8 nozzles N0 through N7. Associated with each of the nozzles is a register 77. There are in total 40 such registers. The 8 registers 77 associated with the first array are connected in parallel to the first five bit positions from the output register of main memory 15 via switch 20. They are selectively connected under control of the N signal from s~gnal value generator 16.
The 8 registers 77 associated with array 2 are connected to the 6th through 10th bit positions of the output regis-ter of memory 15 via switch 20 under control of the N sig-nal from value generator 16. In a similar manner the 8 registers associated with each of the third, fourth and fifth arrays are connected to the next succeeding groups of five bits from the output register of main memory lS
via switch 20 under control of the N signal from signal value generator 16. Registers 77 are loaded in parallel via switch 20 and the data contained therein is shifted out in serial fashion under control of the data clock sig-nal to the connected nozzles as indicated in the drawings.
Figure 9 illustrates in greater detail address genera-tor 18. The physical details of multiple output address generator 18 are not shown since they may be constructed from standard components to perform the functions outlines in algebraic form within the box.
~79~3 1 Three intarmediate computations are illustrated in 2 the box. In the first intermediate computation the line 3 value L is divided by k to provide a whole numher I and a 4 fraction F.
The whole number I converted to Mod N yields 6 a value I'. The value I' and the fractional part F from 7 above yield a value I'.~ which is multiplied by k to yield a 8 value A'. The value A' indicates the starting address for 9 each nozzle group. This value is, however, an intermediate value which is multiplied by a constant P (=7=number of 11 words/segment) summed with the word value W and a value ~N
12 to yield the actual address where data is retrieved or 13 placed depending on which portion of the cycle clock is 14 active (read or write).
The values R, Mod N and ~N are computed in advance 16 and stored in the multiple output address generator 18 for 17 each nozzle. The table below is predicated on a value o~
18 k=5 and RN indicates the number of storage locations in 19 memory 15 allocated for a nozzle.
Nozzle ~ Mod N RN x 7 QN
8 40 8 280 g80 BO976034 ~23-~7~7~3 1 The remaining values described above are provided by the circuits previously described. The values of Mod N and ~N may be stored in a read only memory at addresses corresponding to nozzle number values which are provided by the previously described circuits. While a programmed general purposed computational device may be used for mul-tiple address generator 18, a more desirable choice would be hard wired logical circuits for performing the described function since the speed of computation required would be more easily and economically achieved.
The graphs and table in Figure 10 illustrate the vari-ous timing relationships and the sequence of events in the circuits described ahove. Graph A illustrates se~eral cycles of the line and drum sync signals. Graphs B and C
illustrate read/write sequences for random access memories (RAM) 42 and 43. Graph D illustrates a single line sync period and graph E illustrates the fifty-six cycle clock periods occurring therein. The table immediately below graph E illustrates graphically the occurrence of various values during the different cycles of the cycle clock sequence. The indicated sequences are repeated. The word number goes from 0-6 and repeats. It ends on 6 at the 56th cycle of the cycle clock. The nozzle number stays at 0 for seven cycles and increments to 1 where it stays -for seven cycles. Thereafter it increments to 3 and incre-ments every seven cycles. The line number increments at line sync and remains at that value till the next line sync. Graph F shows a single cycle of the cycle clock and graph G shows the data clock during that cycle.
lO~g79~
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
24 Figures 2 and 2A illustrate the drum, the array mountings and the array drive. The drum 22 is supported for 26 rotation by structures not shown. Adjacent to the periphery 27 of the drum is an array drive motor 28 which drives a lead 28 screw 29. The array support 30 is mounted on the lead screw 29 29 and travels in an axial direction along the drum surface 0 on the screw 29. Forty ink jet nozzles 31 illustrated BO976034 ~9~
~V797~3 1 schematically are supported on the array support 30. They are arranged in five linear groups of eight each. The details of the ink jet nozzles and the associated ink jet printer mechanisms have been intentionally deleted since conventional ink jet nozzles and ink jet printers may be utilized with this invention because the placement of the nozzles on the nozzle support 30 is substantially unrestrict-ed. The specific nozzle arrangement described above is exemplary only. A large number of nozzle arrangements may be selected when the rules set forth belo~ are followed.
According to the invention the center to center spac-ing of the nozzles in each of the arrays is virtually without restraint since adjacent nozzles are not required to cover adjacent segments o~ the circumference of the drum. Each of the circumferential :Lines around the drum is divided into equa~ length segments and the number of segments selected equals the total number of nozzles and the lines are spaced one resolution element apart. This criteria permits the spacing of the nozzles to be larger than the center to center spacing of the drops or the lines on the paper with a negligible sacrifice of either printing speed or resolution. In addition, it permits fabrication of nozzles using a much simpler process since spacing constraints may be eliminated. This consideration broadens the number of useful ink jet nozzle technologies available. For example, glass-drawn nozzle arrays or etched amorphous materials may be utilized since these are currently limited to larger spacings. In addition, the charge electrode packaging guttering deflection sys-tem and problems related to electrical cross tal}c be-come much easier to solve. The techniques described may be l utilized in eith~r single or multiple array cGpierS. Memory 2 requirements, such as are present in the main memory 15, are 3 mlnimized by using multiple arrays of nozzles positioned 4 around the circumference of the drum as illustrated in Figure 1, provided these are properly interlaced. This is 6 due to the fact that the memory storage required is directly 7 related to the axial length subtended by the arrays.
~ In considering the placement of nozzles in an 9 array, two cases must be looked at, the single array and plural arrays spaced around the drum periphery.
11 In a single array comprising N nozzles spaced k 12 resolution elements apart, the criteria for interlace is as 13 follows where N and k are both integers.
14 l) The nozzle array must advance in the axial direction N resolution element~ per single revolution of the 16 print drum.
17 2) For k factorable into prime factors such that 18 k = AxBx ..... x M, N must be an integer which has no prime 19 factors in common with k, i.e, the fraction k/N must be irreducible.
21 In accordance with the above, the first nozzle 22 prints, for exampler segment l for a given scan line, the 23 second nozzle segment l + k, the third l + 2k, etc. in order 2~ for all segments to be printed with no overprinting of any segment, the first segment must not be reached again in the 26 above sequence until 1 + Nk. Examples of k and N combination~
27 which will interlace are given below.
28 1) k=2, N includes the set of all odd integers.
29 2) k=3, N includes the set of all integers which are not multiples of 3.
1~79793 1 3) k=4, N includes the set of all odd integers.
2 4) k-S, N includes the set of all integers which 3 are not multiples of S.
4 5) k=30 [2x3x5], N includes the set of all odd integers which are not multiples of 3 or 5. If the fraction 6 k/N is reducible, the nozzle array will not interlace and 7 double printing or missed areas will result.
8 The second case considered and illustrated in 9~ Figure 1 and Figure 2 is that of multiple arrays of plural nozzles. A multiplicity of M identical nozzle arrays having 11 a total of NT nozzles are shown in ~igure 2. The nozzles 12 are spaced K resolution elements apart in the array. M, the 13 number of arrays, N, the number o nozzles per array, and k, 14 the multiple of the resolution elements are all integers.
The criteria for interla~e is as follows.
16 1) The nozzle transport must advance in the axial 17 direction NT resolution elements per revolution where NT is 18 the total number of nozzles.
19 2) The fraction Tk/M divided by TN must be irreduc-ible. The numerator and denominator must have no common 21 prime factors. T is the smallest integer between 1 and Mr 22 such that Tk/M is also an integer (it follows that M~T is 23 also an integer). The value of T required to satisfy the 24 above expressions indicates the necessity of pairing of nozzle arrays. If T equals 1, there is no constraint on the 26 arrays as to pairings. If T equals 2, the arrays must be 27 even in number and paired in two groups displaced fro~ each 28 other by 180~. If T equals 3, the number of arrays must be 29 a multiple of three and arranged in three groups spaced 120 apart. In a multiple array where T equals 2, the pairs of -~79793 1 array groups must be spaced 180 apart; however, the spaclng~
2 within each group will be dictated by other re~uirements, 3 namely, where on the drum the array segments are to begin.
4 This will be treated in greater detall when the specific embodiment disclosed is described.
6 An array arrangement may be selected according to 7 the steps set forth below.
8 1) The desired value for k is chosen to pro~ide g the desired resolution according to the expression l/reso-lution = nozzle spacing/k.
11 2) Select the number of arrays desired M.
12 3) Solve the fraction set Eorth above to determine 13 the value of T and khe allowable number of nozæles N. Find 14 the minimum T satisf~ing Tk/M eqllals an integer and determine that ~he equation set forth above is irreducible.
16 4) For a minimum print buf~er or main memory 17 requirement a~l arrays should be aligned in the axial direction 18 to a common circumferential line as illustrated in Figure 2.
19 The arrays need not necessarily be axially aligned to a common circumferential line. In this case the axial align-21 ment can be traded for spacing between arrays. ~owever, if 22 they are not aligned, interlacing will nevertheless occur 23 but increased main memory will be required in all instances 24 where information i5 being scanned and printed at the same time. The angular spacing for axially aligned arrays may be 26 any multiple of 360/NT which is not a multiple of 360 27 x K/NT from any other array where 360/NT corresponds to 28 one segment.
29 In the illustrated embodiment, five arrays, 21A
through 21E, are used. Each of these arrays include eight 31 nozzles 31. The nozzles in the arrays are spaced flLve ~Og7603~ -13-. . - ~
1 resolution elements apart, thus the values given above are M
2 = S, ~ = S, N = 8, NT = 40 When these va:Lues are substituted 3 in the equation given above, T has a value of 1, th~s the 4 arrays are not paired and may be angularly spaced according to the description above. An angular spacing between arrays 6 of 9~ was selected. 9~ of all the possible orientations was 7 selected since it permits an easier visualization o operation, 8 A selection of 54 is also an excellent choice since it 9 provides adequate space between arrays for the ink iet nozzles hardware yet has adequate space opposite the arxays 11 for installing papPr handling equipment to permit paper to ~ be automatically or manually added to the drum and removed.
13 Figure 3 illustrates the drum 22 with the paper 24 14 mounted on it and the drum sync generator 27. The drum sync generator includes the disc 32 having 40 scribed transparent 16 lines thqrein arranged around the periphery of the disc.
17 The disc 32 lS attached to the drum 22 and rotates therewith 18 between a light source 33 and a detector 34. When the light 19 from source 33 is detected by the detector 34, the drum sync 2n signal is provided by detector 34. This signal is applied 21 to the clock generator circuit 12 illustrated in Figure 1.
22 Figure 4 illustrates 40 scan lines as reproduced 23 on the drum. Each of the 40 scan lines includes 40 segments.
24 The drawing in Figure 4 is grossly distorted in order to present the information in a manner which is clearly under-26 stood. The 40 scan lines typically occupy 257 mils on the 27 drum or paper mounted thereon. The drawing contains a ~28 series of numbers. The first digit of each of the double 29 digit numbers represents the array number. The second digit of the double digit numbers represents the nozzle number 3LO'7~793 1 within the array which produced the image in that parti-cular seyment. Each of the double digit numbers is co-extensive with one of the segments. Thus, in the first scan line the first segment is produced by the first noz-zle of the first array and the number is 11. The second segment of the first line is produced by the first nozzle of the second array. The third segment is produced by the first nozzle of the third array, the fourth segment by the first nozzle of the fourth array, and the fifth segment by the first nozzle of the fifth array. The second noz-zle of the first array reproduces the sixth segment on the first scan line. The sequence continues throughout the scan line. The eighth nozzle of the fifth array repro-duces the first segment of the second scan line and all of the other nozzles in arrays are displaced one segment to the right. Subsequent lines are produced in the same manner with the segments produced by the nozzles precess-ing to the right and moving back to the left when the 40th segment was done on the preceding line. The entire pattern illustrated occupies a single revolution of the drum. On a subsequent revolution of the drum another 40 scan lines are produced. The 40 lines illustrated in Figure 4 are, as previously stated, distorted and on:Ly occupy approximately 257 mils of space in khe vertical direction on the paper on which the image is being pro-duced. The width, however, is substantially as illustrated in Figure 4. A complete page, of course, will require many reproductions one after the other of the 40 lines illustrated in Figure 4.
3n ' .: ' ` ' ' . ~ ' ~7~793 1 Figure 5 is primari'y intended to illustrate the outputs from clock generator 12 shown in Figure 1. The clock includes a master oscillator 35 and the necessary counting and logic circuits 36 for producing the four outputs illustrated in response to the drum sync signal supplied by the drum sync generator 27 of ~igure 1. The details of clock 12 are not illustrated here because con-ventional circuits may be utilized for providing the clock signals illustrated in Figure 5. These, typically, will include counting circuits, logic circuits, differentia-tors and integrators for operating on the pulses from the master oscillator 35 to provide the oùtputs illustrated in Figure 5.
The drum sync signal ~rom drum sync generator 27 is provided once per one-fortieth revolution of the drum 22.
This signal causes the issuance of the line sync signal from clock 12, thus the line sync signals are produced substantially coextensively with the drum sync signal.
1400 data clock signals are produced between each line sync signal to thus provide the 1400 bits per scan line pre-viously referred to. In addition, the period between line sync signals incl~des 56 cycle clocks. The cycle clock signals may or need not necessarily be symmetric. If the two processing times for the source organizer 14 are sym-metric, then the signal may be symmetric. However, if the reading operation requires more time than the writing operation, this may be accommodated by making the cycle clock signals asymmetric within each of the 56 cycles.
The array clock signal includes five pulses 1~7~793 1 during the positive cycle of each of the cycle clock cycles yielding 280 pulses between successive llne sync signals.
The source organizer 14 of Figure 1 is illustrated in greater detail in Figure 6. The data signals from the scanner 11 are applied to a shift register 37 and shifted in under control of the data clock signal from clock 12.
Shift register 37 stores five bits and is provided with five parallel outputs which are applied via a gate cir-cuit 38 and a switching circuit 39 to one or the other of two input data registers 40 and 41 associated with ran-dom access memory cells 42 and 43 respectively. The data signals are shifted into shift register 37 under control of the data clock signals from clock 12. In addition, the data clock signals are applied to a 1-5 counter 44.
At the count of five, counter 44 provides a signal which enables gate 38 and resets counter 44. When gate 38 is enabled, the contents of shift register 37 are applied in parallel to switch 39. Depending on the state of the control signal, the contents of shift register 37 are applied to either input data register 40 or input data register 41. The control signal applied to switch 39 is generated by a trigger circuit 45 which is toggled by the line sync signal from the clock 12. Thus, the control output from trigger 45 changes state with each line sync signal. During one line period the contents of shift register 37 are applied successively each five bit period to input data register 40 whereas during the ne~t line period the contents are applied serially five bits in parallel to input data register 41.
~09-76-034 -17-,. .
~079793 1 The contents of input data registers 40 or 41 are stored in memories 42 and 43 respectively at locations defined by the contents of address registers 46 and 47 respectively. The actual address inserted in either register 46 or 47 depending upon the state of ~rigger 45 is generated by a counter 48 which responds to the output of counter 44. Counter 48 counts from 1 to 280 since 280 is the maximum number of addresses required in memories 42 and 43. This quantity will accommodate 1400 bits in a single scan line since 280 addressable positions each containing five bits equals the 1400 bits per line stored. The output of counter 48 is applied via a switch 49 to either register 46 or 47 depending upon the state of the control signal from trigger 45. When the control signal occupies one state t~e contents o~ counter 48 will be inserted in register 46 and when the control signal occupies the opposite state the contents will be inserted in register 47. Registers 46 and 47 and 40 and 41 operate in synchronism under control of the control signal ~rom trigger 45 to cause the contents of the scanned ~ine to be inserted alternately in memories 42 and 43. A decod-ing circuit 50 responsive to the output of counter 48 decodes the count of 280 and resets counter 48 so that it is prepared to process the next scanned line. This completes the description of Figure 6 insofar as receiv-ing data from the scanner and inserting the received data into the memories 42 and 43 on an alternating line basis.
The remainder of the description which follows will be concerned with removing the contents from memories 42 and 43 and inserting those contents in the appropriate :
places in main memory 15.
BO9-76-034 ~ -18-1~797~3 The contents of memories 42 and 43 are made avail-able in output data registers 51 and 52 respectively.
Memories 42 and 43, depending upon the particular type BO9-76-034 -18a-1 selected, may be controlled by the output of trigger cir-cuit 45 as to which will be in a read and which will be in a write cycle since these cycles are opposite at any given time for the two memories, i.e., when the data from the line scanner is being stored in memory 42, the con-tents of memory 43 which represent the data from the pre vious scan line will be read out into output register 52 and inserted as will be described below in main memory 15.
Output registers 51 and 52 are connected by a switch 53 and five gates 54-1 through 54-5 to a data input register 55 associated with main memory 15. The operation and function of gates 54-1 through 54-5 will be described below.
The A clock signal from clock 12 is applied to a counter 56 w~ich counts 1 through 5 and is reset~ 'I'he outputs illustrated of counter 56 provide an indication of the count. These are labeled A and will be used elsewhere in this circuit and described later on. These outputs are also applied to a decoder circuit 57 which decodes the actual count A-l through A-5 and resets the counter 56 following the occurrence of the A-5 count.
The outputs of decoder 57, A-l through A-5, are applied to the gates 54-1 through 54-5, respectivel~v, thus the first five bits from memory 42 or memory 43 are applied via gate 54-1 to the first five positions of the input register 55. The second group of five bits are applied ~ia gate 54-2 to the second five bit positions in input data register 55, etc. until the last group of five bits are inserted in the last five positions of input register 55. Referring back to Figure 5, it should be notecl that the A clock or array clock contains five pulses in one-half of the cycle clock p,~riod. This is ~9793 1 necessary since five addresses in memories 42 or 43 must be processed during one clock cycle period because the word length in main memory 15 is 25 bits and that in memories 42 and 43 is five bits. Thus, the contents of five addresses in memories 42 or 43 are assembled in the input data register 55 during each cycle clock for later insertion into memory 15. These are assembled under con-trol of the counter 56 and decoder 57.
An address generator 58 receives the output from counter 56, the L, N, and W outputs from signal value generator 16 and computes the address as indicated in the expression in the drawing. The computed address is applied via a switch 59 under control oE the control out-put from trigger 45 to either register 46 or 47 depending upon the state of trigger 45. It should be noted that the address from counter 48 and the address from generator 58 will be applied to different registers 46 and 47 because the control signals from trigger 45 are of opposite s~ates and are applied to switches 49 and 59 respectively. Thus, data will be written into one memory while it is being removed from the other memory and the roles will reverse with each successive line sync signal. The implementa-tion of address generator 58 should be obvious to those skilled in this art. Typically, this address generator will be constructed from conventional solid state cir-cuits to specifically provide the output indicated from the inputs provided. A general purpose computer could be used. ~owever, the speed required and the limited function required would militate in most instances against such a choice.
Figure 7 is a detailed diagram of the signal 1 value generator 16 illustrated in Figure 1. The data clock signals are applied to an A counter 60 which is provided with five counting stages having paired outputs Al, A2, A4, A8 and A16. The outputs Al, A2, A4, A8 and A16 are applied via an AND gate 61 to the reset input of counter 60. Thus, counter 60 rese-ts aflter counting 25 data clock pulses. This corresponds to the number of bits in a word in main memory 15. The output of AND gate 61 is connected to a B counter 62 which has three stages to provide word count W which ranges from 1 through 7 or, stated differently, 0 through 6. The outputs Bl, B2 and B4 of B counter 62 are connected to an AND gate 63 which has its output connected to the reset input counter 62. The output of AND gate 63 is also connected to an E counter 6 which has four stages, the outputs of which are lab~lled El, E2, E4 and E8. These constitute the nozzle val~e N, the outputs El, E2, E4 and E8 are connected to an AND
gate 65 which has its output connected to the reset input of counter 64 which counts to 8, and resets, thus prov-iding an output indicative of the eight nozzle values.
The preset value stored in register 17 of Figure 1 is applied to preset an F counter 66. The line sync signals from the clock 12 of Figure 1 are applied to the step in-put of counter 66 which has six stages and provides the line count L. The Fl, F2, F4, F8, F16 and F32 outputs of counter 66 are applied via an AND gate 67 to the reset ~-input of counter 66. Thus, counter 66 counts from 1 through 40 to indicate which of the 40 scan lines are being pro-cessed. Obviously, many more than 40 lines are processed.
However, they are treated as groups of 40 by the circuits described above.
~0~97g3 1 Figure 8 illustrates some of the details of the arrays 21A through 21E and the relationship of switch 20 thereto. Switch 20 is connected to the output regis-ter associated with main memory 15 and receives 25 bits in parallel therefrom. In addition, it receives the N
signal from signal value generator 16. Each o~ the arrays 21 includes 8 nozzles N0 through N7. Associated with each of the nozzles is a register 77. There are in total 40 such registers. The 8 registers 77 associated with the first array are connected in parallel to the first five bit positions from the output register of main memory 15 via switch 20. They are selectively connected under control of the N signal from s~gnal value generator 16.
The 8 registers 77 associated with array 2 are connected to the 6th through 10th bit positions of the output regis-ter of memory 15 via switch 20 under control of the N sig-nal from value generator 16. In a similar manner the 8 registers associated with each of the third, fourth and fifth arrays are connected to the next succeeding groups of five bits from the output register of main memory lS
via switch 20 under control of the N signal from signal value generator 16. Registers 77 are loaded in parallel via switch 20 and the data contained therein is shifted out in serial fashion under control of the data clock sig-nal to the connected nozzles as indicated in the drawings.
Figure 9 illustrates in greater detail address genera-tor 18. The physical details of multiple output address generator 18 are not shown since they may be constructed from standard components to perform the functions outlines in algebraic form within the box.
~79~3 1 Three intarmediate computations are illustrated in 2 the box. In the first intermediate computation the line 3 value L is divided by k to provide a whole numher I and a 4 fraction F.
The whole number I converted to Mod N yields 6 a value I'. The value I' and the fractional part F from 7 above yield a value I'.~ which is multiplied by k to yield a 8 value A'. The value A' indicates the starting address for 9 each nozzle group. This value is, however, an intermediate value which is multiplied by a constant P (=7=number of 11 words/segment) summed with the word value W and a value ~N
12 to yield the actual address where data is retrieved or 13 placed depending on which portion of the cycle clock is 14 active (read or write).
The values R, Mod N and ~N are computed in advance 16 and stored in the multiple output address generator 18 for 17 each nozzle. The table below is predicated on a value o~
18 k=5 and RN indicates the number of storage locations in 19 memory 15 allocated for a nozzle.
Nozzle ~ Mod N RN x 7 QN
8 40 8 280 g80 BO976034 ~23-~7~7~3 1 The remaining values described above are provided by the circuits previously described. The values of Mod N and ~N may be stored in a read only memory at addresses corresponding to nozzle number values which are provided by the previously described circuits. While a programmed general purposed computational device may be used for mul-tiple address generator 18, a more desirable choice would be hard wired logical circuits for performing the described function since the speed of computation required would be more easily and economically achieved.
The graphs and table in Figure 10 illustrate the vari-ous timing relationships and the sequence of events in the circuits described ahove. Graph A illustrates se~eral cycles of the line and drum sync signals. Graphs B and C
illustrate read/write sequences for random access memories (RAM) 42 and 43. Graph D illustrates a single line sync period and graph E illustrates the fifty-six cycle clock periods occurring therein. The table immediately below graph E illustrates graphically the occurrence of various values during the different cycles of the cycle clock sequence. The indicated sequences are repeated. The word number goes from 0-6 and repeats. It ends on 6 at the 56th cycle of the cycle clock. The nozzle number stays at 0 for seven cycles and increments to 1 where it stays -for seven cycles. Thereafter it increments to 3 and incre-ments every seven cycles. The line number increments at line sync and remains at that value till the next line sync. Graph F shows a single cycle of the cycle clock and graph G shows the data clock during that cycle.
lO~g79~
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
Claims (6)
- CLAIM 1
- 2. An interlaced multiple element printer as set forth in claim 1 in which said marking means are ink jet printer nozzles and selectively deposit ink on the media when operated.
- 3. An interlaced multiple element printer as set forth in claim 2 in which said member for supporting the media is a cylinder, the exterior cylindrical surface of which is adapted to support a media and is arranged for rotation about its axis to provide relative movement in one direction with respect to the said support and said support is mounted adjacent the exterior cylindrical surfaces and arranged to move in the axial direction of the cylinder to provide relative movement with respect to said cylindrical media support in the said orthogonal direction.
- 4. An interlaced multiple element printer as set forth in claim 3 in which said ink jet nozzle support moves in the axial direction N resolution elements during each complete rotation of the cylinder.
CLAIMS 2, 3 & 4 - 5. An interlaced multiple element printer mechanism suitable for use in a copier or the like comprising:
a substantially cylindrical member suitable for supporting a media and arranged for rotation about its cylindrical axis;
a support mounted adjacent the cylindrical surface of the member and arranged for relative axial movement there-with, whereby said support and cylindrical member move with respect to each other in two substantially orthogonal directions;
a plurality of selectively operable marking means arranged in a substantially straight line parallel to the cylindrical axis on the said support for selectively marking a media with indicia when operated, said selectively operable marking means being spaced from each other by a distance equal to (k) resolution elements where a resolution element is equal to the distance between successive marks formed on the media in the axial direction when all of the marking elements are operable and k is an integer which when divided by (N), the total number of selectively operable means, results in an irreducible fraction; and means for simultaneously rotating the cylindrical member and advancing the support means in the axial direction N resolution elements in each complete rotation of the cylinder. - 6. An interlaced multiple element printer mechanism as set forth in claim 5 in which said marking means are ink jet printer nozzles and selectively deposit ink on the media when operated.
CLAIMS 5 & 6
1. An interlaced multiple element printer mechanism suitable for use in a copier or the like comprising:
a member for supporting a media suitable for receiving indicia on at least one surface thereof;
a support mounted adjacent said at least one surface of said media support member and arranged for relative movement in two substantially orthogonal directions with respect to said media support member;
a plurality of selectively operable marking means mounted on the said support and arranged in a substantially straight line parallel to one of the directions of relative movement between the media support member and the adjacent support, and selectively operable marking means being spaced from each other by a distance equal to (k) resolution elements where a resolution element is equal to the distance between successive marks formed on the media in a direction parallel to the line of marking means when all of the marking elements are operable and k is an integer which when divided by (N), the total number of selectively operable means, results in an irreducible fraction; and means for simultaneously causing relative movement in the said two substantially orthogonal directions so that the marking means advance with respect to the media support in a direction parallel to the line of the marking means N
resolution elements while the line of nozzles move across the media in the said other direction in its entirety one time.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/700,423 US4069486A (en) | 1976-06-28 | 1976-06-28 | Single array ink jet printer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1079793A true CA1079793A (en) | 1980-06-17 |
Family
ID=24813445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA280,312A Expired CA1079793A (en) | 1976-06-28 | 1977-06-10 | Single array ink jet printer |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4069486A (en) |
| JP (1) | JPS532039A (en) |
| CA (1) | CA1079793A (en) |
| GB (1) | GB1566826A (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4112469A (en) * | 1977-04-21 | 1978-09-05 | The Mead Corporation | Jet drop copying apparatus |
| JPS54143012A (en) * | 1978-04-28 | 1979-11-07 | Canon Inc | Information reader |
| US4232324A (en) * | 1978-06-05 | 1980-11-04 | International Business Machines Corporation | Apparatus for arranging scanning heads for interlacing |
| JPS5611263A (en) * | 1979-07-11 | 1981-02-04 | Canon Inc | Recording device |
| JPS5621287A (en) | 1979-07-30 | 1981-02-27 | Xerox Corp | Fluid dripping device |
| US4347520A (en) * | 1979-09-12 | 1982-08-31 | The Mead Corporation | Ink jet printer |
| US4238805A (en) * | 1979-09-12 | 1980-12-09 | The Mead Corporation | Ink jet printer startup and shutdown procedure |
| US4321627A (en) * | 1979-09-20 | 1982-03-23 | International Business Machines Corporation | Optical scanner for ink jet printer |
| US4384295A (en) * | 1980-03-26 | 1983-05-17 | Cambridge Consultants Ltd. | Liquid jet printing apparatus using a raster of drops to effect printing |
| US4401991A (en) * | 1981-10-08 | 1983-08-30 | International Business Machines Corporation | Variable resolution, single array, interlace ink jet printer |
| US4596990A (en) * | 1982-01-27 | 1986-06-24 | Tmc Company | Multi-jet single head ink jet printer |
| US4445128A (en) * | 1982-04-02 | 1984-04-24 | Pitney Bowes Inc. | Method and apparatus for compensating for irregular motion |
| US4575082A (en) * | 1984-01-24 | 1986-03-11 | Diversified Products Corporation | Racquet with ratchet-connected throat and handle |
| US5070410A (en) * | 1989-03-21 | 1991-12-03 | Hewlett-Packard Company | Apparatus and method using a combined read/write head for processing and storing read signals and for providing firing signals to thermally actuated ink ejection elements |
| DE4019543A1 (en) * | 1989-06-20 | 1991-01-10 | Canon Kk | Ink jet printing-plotting appts. - has heated fixing unit following printing stage to improve throughput |
| EP0422925B1 (en) * | 1989-10-10 | 1996-09-11 | Tektronix Inc. | Method and apparatus for interlaced printing |
| JP2911652B2 (en) * | 1991-07-12 | 1999-06-23 | キヤノン株式会社 | Recording device |
| DE69417319T2 (en) * | 1993-08-30 | 1999-07-15 | Hewlett Packard Co | Image scanning head for a thermal inkjet printer |
| US5532825A (en) * | 1993-08-30 | 1996-07-02 | Hewlett-Packard Company | Add-on scanner for existing ink jet printer |
| US5808655A (en) * | 1995-05-12 | 1998-09-15 | Eastman Kodak Company | Interleaving thermal printing with discontiguous dye-transfer tracks on an individual multiple-source printhead pass |
| US5724086A (en) * | 1995-05-12 | 1998-03-03 | Eastman Kodak Company | Printhead having data channels with revisable addresses for interleaving scan lines |
| US5793392A (en) * | 1995-06-13 | 1998-08-11 | Tschida; Mark J. | Printing apparatus and method |
| US5988790A (en) * | 1996-04-11 | 1999-11-23 | Mitsubishi Denki Kabushiki Kaisha | Multiple element printer and method of adjusting thereof |
| JP3562308B2 (en) | 1997-05-14 | 2004-09-08 | セイコーエプソン株式会社 | Printing apparatus and printing method |
| US6089696A (en) * | 1998-11-09 | 2000-07-18 | Eastman Kodak Company | Ink jet printer capable of increasing spatial resolution of a plurality of marks to be printed thereby and method of assembling the printer |
| US6834586B1 (en) * | 1999-05-31 | 2004-12-28 | Fuji Photo Film Co., Ltd. | Lithographic method and lithographic device, plate making method and plate making device, and ink jet printing method and printing device |
| JP3353828B2 (en) | 1999-08-06 | 2002-12-03 | 富士ゼロックス株式会社 | Recording device and recording method |
| GB0816625D0 (en) * | 2008-09-11 | 2008-10-22 | Intense Ltd | Improvements in semiconductor lasers |
| IT1400421B1 (en) | 2010-06-05 | 2013-05-31 | Metoda S P A | WRITING MECHANISM WITH MULTIPLE HEADS FOR PRINTER |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3564120A (en) * | 1968-10-18 | 1971-02-16 | Mead Corp | Image construction system with arcuately scanning drop generators |
| US3588906A (en) * | 1968-10-18 | 1971-06-28 | Mead Corp | Image construction system with clocked information input |
| US3797022A (en) * | 1972-07-25 | 1974-03-12 | Mead Corp | Apparatus and method for reproduction of character matrices ink jet printer using read only memory |
| DE2246797C3 (en) * | 1972-09-23 | 1980-10-09 | Agfa-Gevaert Ag, 5090 Leverkusen | Continuous recording of images by means of a liquid jet |
| SE378212B (en) * | 1973-07-02 | 1975-08-25 | Hertz Carl H | |
| JPS5234328B2 (en) * | 1973-07-04 | 1977-09-02 | ||
| US3911818A (en) * | 1973-09-04 | 1975-10-14 | Moore Business Forms Inc | Computer controlled ink jet printing |
| US3975740A (en) * | 1973-10-02 | 1976-08-17 | Siemens Aktiengesellschaft | Liquid jet recorder |
-
1976
- 1976-06-28 US US05/700,423 patent/US4069486A/en not_active Expired - Lifetime
-
1977
- 1977-05-16 GB GB20496/77A patent/GB1566826A/en not_active Expired
- 1977-06-10 CA CA280,312A patent/CA1079793A/en not_active Expired
- 1977-06-16 JP JP7059577A patent/JPS532039A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| GB1566826A (en) | 1980-05-08 |
| US4069486A (en) | 1978-01-17 |
| JPS532039A (en) | 1978-01-10 |
| JPS5616467B2 (en) | 1981-04-16 |
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