CA1072685A - Analog to digital converters - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
In an analog to digital converter in which each sampled portion of an incoming video or other analog signal is converted to a digital character in a plurality of parallel conversions occurring serially; the range of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a relatively fine parallel conversion of a sampled analog signal is selected to be larger than, and offset in respect to the steps or increments of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a preceding relatively coarser parallel conversion, and the encoded outputs from the serially occurring parallel conversions are digitally added with the least significant bit of the encoded output from each preceding relatively coarser parallel conversion being accorded the same weight as the most significant bit of the encoded output from the next following relatively finer parallel conversion so as to eliminate from the result of the digital addition defects that would otherwise arose from inaccuracies in the voltage level reference signals and/or in the comparing operations of the comparators.

Description

~ f- S0777 ` ~76P48 ~ , Field of the Invention _ This invention relates generally to analog to digital converters, and more particularly is direeted to improved an~log to digital converters of the paralleL-serial type which are Pspecially suitable ~or use in video time base correctors.
Descri tion of the ~rior Art Time base corre tors.are known for processi~g video or ~ele~isio~ signals to remove time bas~ err:ors in~roduced d~r~ng signal recording, reproducing or transmissi~n. In such t~me base correctors, th~ incomin~ video signals are converted from analog to digital form and t~mporarily stored or written in a memory unit at a clocking rate which varies in a ma~ner generally proportional to the time base errors;
whereupo~g:the stored signals are fetched or read o~t o the memoxy:unit at a standard cloc.king rate so as to remove the time~base errors therefrom, and then t~e read-out sig~als are reconverted ~rom digitaL form back to analog form, Various type5 of analog to digital converters have be~n proposed, for :example, for use in t~;e base cor~ectors as described above. In so called parall el-type analoO to ::
digitæ.~ ~onverters9 a sampled:analog signal, such as tne in~mi~g video si~nal, i5 applied to a irst co~pare i~put o each of a plurali~y of dual~input comparators, while the seco~d compare inputs of the~ comparators receive respective '' ~ :
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voltage lev21 reference signals~ or exa~ple, from respective voltage sources or ~rom a voltage dividing network. The outputs of the comparators are coupled to an encoder which provides a binary or other encoded output or digital character comprised of a predetermined num~er of bits. Although analog to digital converters of the parallel type are capable of high speed operation, they have a nu~ber o~ inherent di3a~vantages First of aLl, such converters require large numbers of comparators and o associated voltage sources or resistors in ~he voltage dividing network for providing the respec~ive vol~a~e level reference signals. More particularly, in paral~e~-type analog to digital converters, the required nu~ber of comp ra~ors and of re~pecti~e voltage level reference signals : is 2k-1, with k being the number o~ bits of binar~ codes : desired in the output from the encoder. Thus, for exam21e, if the output of the ~ncoder is to contain~8-bits of binary codcs, the required ~umber of comparators i 28-1 or 255~
and a corresponding number of voltage sources are also required.
Furthermore, in the desc~bed parallel^type analog to digital converters, any inaccuracies in the co~parators and/or in the ~ respective ~oltage level reference signals can produce defects :~ in t~ signal that is obtained when the digi~izPd outpue of the analog to digital converter is subsequently reconver~ed to analog form.

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In other existing analog to digital converters of the so-called serial-type, a plurality of dual input comparators are arranged in a series of descending significance, wi~h a digital-analog converter and a subtractor being arranged between each comparator and the next adjacent co~parator of lower significance, and with the comparators receiving, at one of the inputs thereof, respective re~erence signals of descending voltage levels. The most signi~icant comparator compares the s~mpled analog signal, such as the incoming video signal, with the respective voltage level reference si~nal to provide the most significant bit o~ the desired digital charac~er or output. Each of the digital to analog convexters converts the :
output of the preceding comparator or comparators ~ a corresponding analog signal which is then subtracted, in the respective subtractor~ from the incoming video signal to attain a difference signal which ~ compared in the next comparator with the respective voltage level reference signal for pro~iding another re~pective bit of the dPsired digital output. Tha serial-type analog to digital converters, as briefly described above, require far fewer circuit elements than the parallel~type analog to digital converters. For e~ample, if the digital output is to be made up of ~ binary bits, the seriaL-type converter requires k comparators, k voltage sources or the like for providing the ~oltage level reference signals, k l digital-analog converters, and k-l subtrac~or~. However, the serial-type analog to digital conver~ers are not capabIe of high speed operation.

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In view of the above9 it has been proposed, for exampLe, as disclosed in U.S. ~atent No. 3,860,952, to provide a so-called parallel-serial analog to digital converter for use in a video time base corrector witn a view to attaining a high operating speed by ~eans o~ a relatively fewer number of circuit elements as compared with the existing parallel-type analog to digital conv~rters. In the known parallel-serial analog to digital converter, each sampled partion or an incoming video or other analo~ sig~ 1 is converted to a digital character in two 4-bit parallel co~versions which occur ~erially. The first parallel conversion is effected hy a number of coarse comparators having first inputs which receive the sampled i~coming analog signai and second inputs which receive voltage level reference sig~als of magnitudes descending in relatively large unit incr~ents~ and an encoder receives the outpu~s of the comparators for providing an encoded output specifying the fsur mos~ si~nificant bits of an 8-bit digital character representing the sa~pled incoming analog signal. Such output from the encoder of the first parallel conversion is converted to analog form and subtracted from the sampled incoming analog signal to provide an ana~og difference signal which is subjected to a second parallel conversion, The second parallel conve sion is effected by a number of fine comparat~rs havinO first inp~ts which receive ~he analog difference signal and second inputs which receive :.

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voltage level reerence signals of magni~udes descending in relatively small unit increments, with the max~mum voltage level re~erence signal applied to a fine comparator being smaller than the min~mum Yoltage level reference signal applied to a coarse comparator by one of said small unit increments. Finally, an encoder receives the outpu~ of the fine comparators for providing an encoded outpu~ specifying the four least si~nificant bits of the 8-bit digital character rep~esenting the sampled incoming analog signal.
It has been found that the existing analog to digital converters of the paraLlel-serial type, as described above, are also disadvantageous in that inaccuracies in the comparators 3 ~rticularly of the first parallel conversion, and/or of the re~pective voltage level reference signals can produce defects in the signal that is obtained when the digit~zed ou~put of the analog to digital converter is subsequently reconverted to analog ~orm.
OBJ~CTS AND SUk~RY OF THE INV~NTION
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Accordingly, an object o~ the present invention is to provide an improved analog to digital converter, ~or example7 for use in a time base corrector, and which is free of al} of the above described ~isadvantages of existing analog to di~;ital converters.
~ore specifically, it is an object of this inven~ on ~:
to provide an analog to digital converter which is composed o~.a relatively few circuit elements while being capable of -6- :~
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high speed operation, an~ which reliably provides a digitized output accurately representing a sa~pled analog input signal so that such digitized output, when reconverted to analog form, precisely corresponds to the original input signalO
A further object-is to provide an analog to digital convexter, as aforesaid9 which is o~ ~he so-called parallel~serial type.
I~ accordance with an aspect o this invention, in an analog to digital converter in which each sampled portion of an ;~ooming video or other analog signal is con~erted to a digitaL cnaracter in a plurality of paralLel ~onversions occurring serially, as aforesaid, the range of ~he voltage level reference sig~als o~ descending magnitude which are appLied to comparators for effecting a relatively ~ine parallel conversion of a sampled a~alog signal is selected to be larger than, and offset in respec~ to the steps or increments o the voltage ievel reference signals of descending magni~ude which are app~ied to comparators for effecting a preceding relati~ely coarser parallel conversion, and the encoded outputs from the serially occurring parallel conversions are digitally added with th~ least signiicant bit of the encoded :
-output from each preceding relatively:coarser parallel ~ :
conversion being accorded the same weight as the most signi~icant bit of the encoded output from the next followin~ :
relatively finer parallel con~ersion so as to eliminate ~rom the result o~ the digital addition defe~ts that wou1d otherwise ;---7- :

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ari5e rom inaccuracies in ehe voltage level reference signals and/or in the operations of the compar~tors.

More particularly, there is provided:
An analog to digital converter comprising a plural-ity of parallel conversion units in a serial arrangement com~ :
prising a preceding parallel conversion unit and a following : parallel conversion unit for specifying respective groups of decreasingly significant bits of a digital character, each of said parallel conversion units including a number of comparators 10 having first inputs for receiving an analog signal and second ; inputs for receiving respective voltage level re~erence signals and encoder means receiving the outputs of said comparators for providing an encoded output specifying the most significant group of bits of a digital character corresponding to the analog : signal received by said first inputs of the respective compara-tors; an input texminal for receiving a sampled analog input signal said input terminal being connected to said first inputs o~ the comparators in said preceding parallel conversion unit to supply said sampled analos signal thereto; means intexposed 20~in said serial arrangement of parallel conversion units for re-- converting the most significant group of bits to an analog signal and subtracting the reconverted analog signal from said sampled analog input signal to produce an analog difference signal and ~or applying the analog difference signal to said first inputs of the comparators in the following parallel conversion unit;
means for applying-to said second inputs of the comparators in each of said parallel conversion units voltage level xeference signals of magnitudes which descend in respective voltage steps, with the ~owest voltage le~el reference signal applied to the lowest level comparator of the preceding paxallel conversion unit being substantially diferent.from the:remaining voltage level ~:
reference signals for each of the other comparators in the pre- :
ceding parallel conversion unit and the range of the voltage level reference signals for said following parallel conversion ~ -8-~.
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unit being larger than, and offset in respect to, said steps of the voltage level reference ~ignals for said preceding par-allel conversion unit; and digital adding means adding the en-coded outputs of all of said parallel conversion units with the least significant bit of the encoded output from said preceding parallel conversion unit and the most significant bit of the encoded output from said following parallel conversion unit being accorded the same weight.

The aboYe, and other vbjects, features and advantages 10 Of the invention, will be apparent in the follo~ing detailed descriptio~ of preferred embodiments thereof which is to be read~ in connection with the acoompanying drawings.
BRI:E:F DESCRIPTIaN OF l'HE DRAWTNGS
~ig~ 1 is a schematic diagram illustrating a parallel-serial analog to digi~al converter according to the :
prior art;
Fig. 2A graphically illustrates various outputs obtained when the con~erter of Fig. 1 is operating accurately i~ response to variations in the incomislg video or other 20 analog signal;
.~ Figo :2B is simiLar to Fig. 2A~ but graphically illustrates the outputs obtained when reference signals de~iate from standard leve:ls in the converter of Fig. l;
Fig. 2C graphically illustrates the analog signal obtained from the outputs of Fig~ 2B~when reconverted to analog form, and to which re~erence will be made in explair~ing a problem associat~d with ehe known analog to digital converter;

8a-Fig. 3 is a schematic diagram si~ilar to that of Fig. 1, but illustrating a parallel-serial analog to digital converter according to one embodiment of this invention;

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Fig. 4A shows graphic illustrations simila~ ~o those of Fig. 2B but for the converter according to this inven~bn as illustrated on Fig~ 3;
Fig. 4B graphically illustrates the analog signal obtained when the digital ou-put of the converter of ~ig. 3 is reconverted to analog form;
Fig. S is a schematic diagrarn ilïustrating a parallel serial a~alog:to ~igital converter accordl~g to another em~odiment of this invention;
Fig. 6 is a schema ic diagram illustra~ing a parallel-ser~al analog to digital converter according to still another embodiment of this invention; ant Fig. 7 graphically illustrates various outputs in the conver~er of Fig. 6 in response to variations in the incoming analog signal.
DESCRIPTION OF
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Referring ~o ~he dr wings in detail, and i~itially ~o Fig. l thexeof, it will be seen that, i~ a parallel-serial analog to digital converter 10 according to the p~ior art, each sampled portion oE an incoming video or other analoO
signal applied to an input terminal ll is converted ~o an 8-bit digital charact~r in two 4-bit~paralle~ ~onversions which occur serially in units 12 and 13, respectively.
In the irst,or coars~ parallel-conversion unit 12 for specifying the four most significant bits of the 8-bit digital . .
: chara~ter, the sampled incoming analoO s ignal is applied ~rom input terminal ll to first inputa of a plurality of~dual input - -. ~ .

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eoarse comparators 141-1415. The other or second inputs of comparators 141-1415 receive respective voltage level reference signals having m~gnitudes which descend in unit increments Es in the direction from comparator 141~ to comparator 141.
Such voltage level reference signals may be provided by a suitable voltage dividing network or, as shown, by a series circuit of voltage sources 151,152,153,---1515 each providing a pote~tial equal to the respective unit increment Es~ Thus, the voltage level reference signals for the comparators 141, 1~,143,- -1415 have the magnitudes Es,2ES,3Es, --15ES, respectively~ so that comparators 141-14L5 provide a first coarse conversion of the sampled incoming analog signal.
The outputs o~ comparators 14~ 5 ~b coupled to a conventional encoder 16 which, for example, provides a binary encoded output at its four output terminals 161S162, 163 and 164 specifying the four.most significant bits of an 8-bit digi~al charac~er representing the sampled incoming analog signal. Such encoded output from encoder 16 i.s reconverted to analog form in a digital to analog converter 17, and the resulting analog signal is subtracted from the sampled incoming analog signal applied to terminal 11 in a subtracte~r 18 so as to provide a difference analog signal which is subjected to a ine conversion in th~ second or ~ine parallel conversion unit 13.
As sho~m7 in fine parallel conversion unit 13, the difference analog signal from subtractor 18 is applied to ~ 10 -first i~puts of dual input fine Comparators 191 19l5, while second inputs of such comparators receive voltage level reference signals having magnitudes which descend in unit increments of ~5516 in the direction from comparator 1915 to comparator 191~ Such voltage level reference gignals may be ~pplied to comparators 191 1915 fxom a suitable Yoltage di~idin8 network or~ as shown, Dl~y be pro-rided by 2 series circu~ o~ voltage sources 201-2015 each providing a voltaOe or potential equal to th~ respective unit increment ES/16 Thus, the voltage leVel reference signals applied to fine comparatoxs l9L,192~193~- 1915 have magnitudes of ES/16, 2ES/16, 3E~;~16 ,---15ES/16, r spectively . As a result of the ~ore2oing, the collverting range of parallel conversion urlit 13 is sub5talltially equal to the steps or i~cres~e~ts E ~n ~che converting range of the preceding parallel co~version unit 12. The output~ of ~ine comparators 191-1915 are coupled to a conventional encodPr 21 which pro~ides, at outputs 211,212,213 and 214~ a respective binaxy encoded output specifying the four least sig~iicant bits o~ the digital character representing th~ sampled incomi~g analog signal. Finally~, the four least significant bits of ; -the digital character are led fro~ outputs 211,212,213 and 214 o~ enc6~der 21 to output terminals 1,2,3 and 4, respectively, . . .
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%~i~s while the four most significant bits of the digital character are led from~outputs 161,162,163 and 164 of encoder 16 to output terminals 5,6,7 and 8, respectively.
It will be apparent that, in the above described analog to digi~al converter 10 according to the prior artl the number of compara~ors in each of the parallel conversion units 12 and 13 is (2~-1), in which K is the number of bits in the digitized output from the respective encoder 16 or 21. Similarly~ the number of voltage sources required for establishing the voltage level reference signals for such comparators in each of the units or stages 12 and 13 is (2KWl). Thus, in the case where ~eu~s.or stages 12 and 13 each have 4-bit outputs, each unit or stage requires. fifteen comparators and fifteen voltage sources, as shown. If a similar 8-bit ou~put was ~o be obtained from merely a parallel-type analog ~o digit~l converter, that is, with a single parallel conve~sion s~ ge, such single stage would require (28~ hat is~ 255, comparators and the same number of voltage sources or estabLlshing the respective voltage level re~erence signals. Thus, the known parallel-serial analog to digital converter does very substantially reduce the numhers of circuit elements required, while being capable of relatively hi8h speed operation.
Referring now to Fig. 2A, it will be seen that, so long as the voltage leveI reference signals applied to the comparators 141-14l5 of coarse conversion unit or stage 12 have the correct values ~nd such comparators ef~ect accurate ~mparisons of the inputs applied thereto, increasing values o~ the incoming video or other analog signal applied to inpu~
terminal 11, as indicated at (I), will e~fect the changes in the logics o the 4-bit digital output from encoder 16, that is, the four most significant bits of ~he digital output , -appearing at output terminals 8,7,6 and 5, respectively, as shown at (II~. In response to such changes in ~he digital output from encoder 16, the analog output from digital to analog converter 17 will vary in a stepwise manner, as indica~ed at (III), with each step in ~he output from converter 17 corresponding to a respective unit incre~ent or step in the voltage level re~erence signals applied to comparators 141~1415.
For variations o the incoming analog signal between the steps of the voltage level reference signals, the difference analog signal applied from subtracter 18 to the comparators 191-1915 of the ine conversion unit or stage 13 will correctly have a range of Es, as indicated at (IV). Therefore, for variations of the incoming analog signal between two successive voltage level reference signals, for example, between 3Es and 4Es, the four least significant bits o~ the digitaL output applied rom encoder 21 to output termi~als 4,3,2 and l, respectively, will have logics ranging from 0000 ~o 1111, as indicated at (V) in which the symbol X indicates the logic O or 1.
However, if the comparators 14L-14l5 of the coarse conversion stage or unit 12 do not accurately compare ~hc . ' signaLs appLied thereto, or if the actual voltage le~elreference signals appLied to such comparators have values E's,2E's,3E's---etc. which deviate from the desired values Es,~Es,3Es---etc., respectively as indicated at (I) on Fig.
2B, then changes in logics of the four most significant bits of the digital output~ as indicated at (II~ on Fîg. ~B, and the steps in the analog ou~put from conver~er 17, as indicated at (III) on ~ig. 2B, will not ac~urateLy correspond o the desired steps in voltage level references signals or the coarse conversion stage 12.. As a result of the foregoing, the difference a~alog signal applied from subtracter 18 to ~he comparators l9L~19L$ o~ the ~ne conversion stage L3 may extend above the value Es or attain negati~e values, as indicated at (IV) on Fig. 2B.
. By reason of the oregoing, the 8 bit digital character:or ou~put from converter LO may not ac~ura~ely correspond to the incoming video or . other analog signaL.
For example, if the incoming analog signal has a ~alue varyir~g between 2ES and 2E's, the 8-bit digitaL character at the output o converter 10 will remain fixed at 00011111, as indicated at (II) and (V) on ~ig. 2B. Similarly, in the illustrated example, if the incoming analog signal has a ~alue varying between 6E's and 6ES, the 8 bit tigital character at the output of co~erter 10 ~will r emaLn fixed at GllOOOOO. Acco~dingly~when the digital outpu~ from converter 10 is subsequently reconver~ed i;
to ~nalog form, the resulting analog signal sh~wn ~n Fig. 2C wiLl not accurately correspvnd`~to ~ e origin~l incoming analog signal shown at ~I) on Fig. 2B.
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~ eferring now to Fig. 3, it will be seen that, in a parallel-serial analog to digital converter 10' according to an embod~ment of ~his inven~ion, the several components corresponding to those included in the above described knor~n converter 10 are identified by the same reference numerals, but with a prime (') appended thereto. Generallyl the conve~ter 10' accordi~g to this invention is s~milar ~ the p~evlously known converter 10 a~d di~fers from the latter in tha~ the range of the voltage level reerence sig~als applied to the comparators 19'1-~9'15 of the fine parallel conversion u~it or stage 13' is lar~er than, and offset in respect t~,the steps or incxements in the voltage level reference signals applied to the:comparators 14'1~14'(2~_1) of the coarse parallel conversion unit or stage 12'~ and in that the digital outputs ... ......
of encoders 16' and 21' of the stages or units 12' and 13', respectively, are digitally added9 as in a digital adder 22, with the least significant bit of t~e encoded outpu~ from the coarse parallel conversion stage 12' being accorded the sama weight as the most significant bit of the encoded ou~put from the next foll~wing or relatively finer parallel conversion stage 13', so as to elimin~ from the 8-bit digital character .
o~:tai~ed at output terminals 1'-8-', that is, the result of the di~ital addition, the previously described de~ects that would ise~ arise -from inaccuracies in the voltage level reference slgnals and/or in ~h~ comparing operations o~ the comparators .. ..
particularly in the coarse conversion s~age 12'. .-.

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In the case where the sampled incoming video or other analog signal applied to input terminal 11' is to be converted to an 8-bit digital character by means of two serially occurrin~ parallel conversions in the converter 10', the first or coarse parallel conversion stage or unit 12' is arranged to provide a 5-bit outpu~, while ~he second or fine paxallel conversion stage or unl~ 13' is arranged to again provide a 4-blt output, as shown, so that the least significant bit of the 5-bit output and the most significant bi~ of the 4-bit output can be accorded the same weight in the digital adder 22 ~or producing the desired 8-bit digital character or output corresponding to the sampled incoming analog signal.
More particularly, it will be seen that, in the first or coarse parallel-conversion unit 12', the sampled incoming anaLog signal is applied from input terminal 11' to first inputs of a plurality of dual input coarse comparators 14'1-14'31. Thus, it will be seen that the number o~ comparators in conversion stage 12' is again (~K-l), but with K now being 5.

The other or second inputs of comparatoEs 14' 1-14'31 receive respecti~e voltage level reerence signals having magnitudes which descend in unit increments Es i~ the direction from comparator 14'31 to compara~or 141. Such voltage level reference signals may be provided by a suitable voltage dividing network or, as shown, by a series circuit of voltage sources 15'1,15'2,15'3,---15'3L, with the voltage source 15'1 . :

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'3 providing a voltage or potential o~, for exam?le, (ltl/2)ES, and with each of the other voltage sources 15'2-15'31 each providing a potential equal to the respective unit increment Es Thus, the voltage level reference si4nals for the comparators 14'lj14'2,14'3--~14'31 have the magnitudes (1~1/2)Es, (2~1/2)ES,(~1/2)Es~--(31~1/2)Es, respectively, so that comparators 14'1-14'31 provide a irst coarse conversion of the sampled incoming analog signal.
The outputs of comparators 14'1-14'31 are coupled to a conventional encoder 16' which, for example, provides a binary encoded output a~ its five output terminals 16'1,16'2, 16'3,16'4.and 16'5 specifying five most significant bits of an 8-bit digital character representing the sampled incoming analog signal. As before, such encoded output from encoder 16' is reconverted to analog form in a digital to analog conver~er 17', and the resulting analog signal is subtracted from the sampled incoming analog signal ap21ied to terminal 11' in a subtracter 18' so as to provide a di~ference analog signal which is subjected to a fine conversion in ~he second or fine parallel conversion unit 13'.
As shown, in fine parallel conversion unit 13', ~he diference analog signal from subtracter 18' is applied to first inputs of fifteen t2K-l) dual input fine comparators 19'1-19'15- In the illustrated embodiment of this invention, the voltage level reference signals applied to ~he second inputs o~ compar~tors 197l--19i}5 have magnitudes which descend in unit ~ :
increments of, for example, 2Es/(2K l), tha~ is 2ES/~

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~ 5 from a max~mum voltage level reference signal of 2E for the comparator 19'15 to a minimum voltage level reference signal of 2ES/15 for the comparator 19'1. Such voltage level reference signals may be applied to comparators 19'l-19'15 from a suitable voltage dividing network or, as shown, may be provided by a series circuit of voltage sources 20'l-20'15 each providing a voltage or potential equal to the respective unit increment 2ES/15. Thus, the voltage level reference signals applied t~
f ine comparators 19'1,19~2,19'3---19' 15 have magnitudes OL
2ES/15~4Es/15~6Eg/15~~~2Es~ respectively. As a result of the foregoing, the range 2ES/15 to 2ES of ~he voltage level re~erence signals applied to fine comparator 19'1-19'15 in parallel conversion UQit 13' is larger than the increments Es of the voltage level reference signals applied to the comparators in the preceding parallel con~ersion stage or unit 12'. Further, the range o the voltage level reerence signals employed in conversion unit or stage 13', that is, the converting range o the la~tex, is ofse~ by about 1/2ES in respect to the steps in the voltage level reference signals employed in the preceding :
stage 12'.
The outputs of fine comparators 19'l-19'15 are coupled to ~ conventional encoder 21l which provides, at outputs 21'1,21'2,21'3 and 21'4, a respective binary encoded output specifying the four least significant bits of the digital character representing the sampled incoming analog signal.

Finally, the four least sLgnificant bits appearing at outputs 21'1,21'2,21'3 and 21'4 of encoder 21' and the ~ive most significan~ bits appearing at outputs 16'1,16'2,16'3,16'4 and .

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, s 16'5 of encoder 16' are appli~d to respective inpu~s of digital adder 22 which, as indicated previously, gives equal weight to the bits appearing a~ outputs 16~1 and 21'4 so as to provide the desired 8-bit digital character at output terminals 1',2',3',4',5',6',7' and ~'.
Referring now to Fig. 4A, it will be seen that the parallel-serial analog to digital converter 10' according to this invention will prov~ e an 8-bit digital character which accurately corresponds to the sampled incoming analog signal even if the comparators 14'1-14'31 of the coarse conversion stage or unit 12' do not accura~ely compare ~he signals applied thereto, or i~ the actual voltage level reference signals applied to such comparators have values (l~l/2)E's,(2~1/2)E's, ~3+1/2)E'S---(31~1/2)E's which may diffe~ from the respective desired values by as much as l/2Es, as sho~ at (I) on Fig. 4A. Increasing values of the incoming video or other analog signal applied to input terminal 11l, as indicated at (I), will effect the changes in the logics of the 5-bit digital output from encoder 16' shown at (II). In response to such changes in the digital output rom encoder 16', the analog output ~rom ~
digital to analog converter 17' will vary in a stepwise manner, . ~:
as indicated at (III), With each step in the output from con-verter 17' corresponding to a respective increment or step in the voltage level reference signals applied to comparators 14ll-14'31. For variations of the incoming analog sîgnal between the steps o$ the volta~e level reference signals actually applied ~.
to the comparators in conversion stage 12', the difference analog .

~ fi~5 signal applied from subtracter 18' to the comparators 19'1-lg'15 of the fine conversion unit or stage 13 will always lie in the range between G and 2ES, as indicated at (IV). Therefore, for variations of the incoming analog signal between two successive actual voltage level reference signals, for ex~mple, between (1+1~2)~'s and (2+1/2)E's, the four bits of digital in~ormation appaaring at ou~puts 21'4,21'3,21'~ and 21'1 of encoder 21' will have logics ranging ~rom 0000 to 1111, as indica~Pd at (V) on Fig. 4A.
When the 5-bit output from encoder 16' is digitally added to the 4 -bit output from encoder 2L' with the least significant bit of the output from encoder 16' (II) being given the same weight as the most signiican~ bit from encoder 21', the xesulting 8-bit digital output from adder 22 has the logi~s indicated at (VI) on Fig. 4A. It will be seen that, even though the actual voltage level reerence signals applied to comparators 14'1 and 14'2 in conversion stage 12' are sh~wn at (I) to have values (l~l/2)E1s and (~tl/2)E' that are respecti~ely greater than the intended values (l~ )Es and (2~1/2)ES, the 8-bit digital character obtained from adder 22 for a sampled incoming analog signal rangingS for example, from Es to 2ES, correctly has logics ranging ~rom 00001000 to 00001111, as shown at VI on Fig. 4A. Accordingly, when the :
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digital output from conv~rter 10' is subsequently reconverted ~o analog ~orm~ ~he resulting analog signal shown on Fig. 4B

will accurately correspond to the original incoming analog : signal shown at (I) on Fig. 4A.

...
- ~ - : . , ~)'7~5 As previously noted9 in the above described converter 10' according to this invention, the ran~e of the voltage level reference signals applied tQ the comparators in the fine conversion stage or unit ~3' is larger than) and offset by s with respect,to,!the steps in ~he voltage level reference signals applied to the comparators in the coarse conversion unit 12 ' so as to ompensate for i~accuxaciPs as large as ~s i~ the voltage level reference signals a~p~ied to comparators 14'1-14'31 or in the comparing operations of such comparators. ~owever, such inaeouracies are not likely to :`
be so large as ~Es 50 that the described offset may be reduced and the number o comparators in the fine conversion stage 13' may be correspondingly lowered. For example, if it is desired to compensate for inaccuracies no greater than about LES the voltage leYel refere~ce sign ls applied to comparators 14'1-14'31 in conversion sta~e 12' may remain as before~ while the conversion stage 13' is provided with only thirteen comparators l9'L 19'l3 which have voltage level reference signals 2ES/15,4Es/15,5Es/15---26Es/L5, respectively, applied thereto. In the latter case9 the range of the voltage level re~erence signals applied to the comparators in stage 13' is still larger than, and offset in respect to,the steps of the voltage level re~erence signals applied to t.he comparators in the preceding convers~ n stagP 12'.

j '.

~ 6~

In the converter 10' according to this inven~ion, only two serially occurring parallel conversions are employed for providing an 8-bit digital character or output corresponding to the incoming sampled analog signal. However~ it will be noted that the present invention may be similarly applied to analog to digital converters in which three or more parallel conversions occur serially to provide, for examplP, a 12-bit digital character or ou~put.
For example, as shown on Fig. 5, an analog to digital converter 110 according to this invention may effect three serially occurring parallel conversions of the sampled incoming analog signal applied to input terminal 111 by means of first, second and thixd parallel conversion stages or units 112,113 a~d 114, respectively. The first or coarsest parallel conversion stage 112 may correspond to the stage or unit 12' of the previously described converter 10' and provide a 5-bi~
~gital output in respon~e to the conversion effec~ed by ~2K-l) or thirty-one coarse comparators which, as in the case o the stage or unit 12', receive voltage level re~erence signals (L~1/2)Es,(2~1/2)Es,~l/2)Es---(31~L/2)~s, respectively.
The 5-bit digital output from stage or unit 112 is applied to a digital to analog converter 115 which provides a corresponding analog signal to a subtractor 116 for subtraction in the latter from the s~mpled încoming analog signal applied to input terminal 111. The resulting analog difference signal from subtractor 116 is applied to the second parallel conversion .. . . . . . . ~

stage or unit 113 which i5 operative to provide a 5~bit digital character or output corresponding to such analog di:f~f erence s ignal .
The second paral lel conversion stage or unit 113 may also be similar to the-previously described stage or unit :
112 in that it include5 (2K 1) or thirty one comparators rec~i~ing the analog difference signal and comparing the same with respective voltage level reerence signals. However, in the case of the stage or unit 113 which effects a iner convexsion than the preceding stage or unit 112, the increments between th~ successive lJolta~e level reference signals are 2Es/(2K-l), that is, 2ES/31, and the lowest voltage level referen~e sign~l is 3/2(~Es/31) or 3Es/31. Accordingly, in the second conversion stage 113, the voltage level reference ~gnals for the thirty-one cor~parators rarlge from a minimurn of 3Es/31 to a maximum o~ 12~1/31)ES~ Thus, the range of the vol~age le~el reference signals iIl the second corlversion stage 113 is larger than, and offset in respect to, ~he steps in the voltage level re:~erence signals in the precedin~
first conversion stage 112.
Alternatively, the first a~d second parallel conver-s ion stages 112 and 113 can be identical, that is, pravided with the same volt~age leYel reference signals, if an amplifier (not sho~n~ with an amplification factor of 31~2 is interpos d between subtracter 116 and the second conversion stage ~13.

..
- 23- ~ :
~', - . . . . . . .. . ..

The 5-bit digital output from the fi~st coarse parallel conversion stage 112 and the 5-bit digital output fr~m the finer second paraLlel conversion stage 113 are applied to a digital adder 117 with the least significant bit of the output from stage 112 and the most significant bit of the output from sta~e 113 being accorded the same weight to provide a 9-bit digital output from adder 117. Such 9-bit digital output fro~ adder 117 is applied to a digital to analog converter 118 which provides a correspon~ing analog signal to a subtracter 119 for subtaction in the latter from t~e sæmpled incoming analog signal applied to input terminal 111.
The resulting analog difference signa~ from subtracter 119 is applied to the third or finest parallel conversion stag,e or unit 114 which is operative to provide a 4-bit digital character or output corresponding to the analog difference signal from subtracter 119/
The thlrd or finest parallel conversion stage 114 having a 4-bit digital output may be similar to the previously described conversion stage 13' in that it incLudes (2K-l) or fiteen comparators receiving the analog diference signal from 5ubtracter 119 and comparing the same wi~
respective voltage level reference signals. However, in the case of:~e stage or unit 114 which effects a still finer con~ar5io~ ~han the preceding stage 113, the increments betwee~ the successi~ voltage level reference si~nals are . .2E
-- or 4E /465 with the smallest voltage level `~
(2 -1) (2 -1) s :
' ~ - ( 85i reference signal in stage 114 being 4Fs/465 and the largest voltage level reference signalin that stage being 15(4ES/465) or 4Es/310 Thus, the range of the voltage level reference signals applied to the comp~rators in the finest or third parallel conversion stage 1~4 is larger than, and ofset in respect to,the steps in the voltage level reference signals applied to ~he comparators in the p~eceding second parallel conversion stage 113.
Finally, as showng the g-bit digital output from digital adder 117 and the 4~bit digital output from the third stage 114 are digitally added in a digital adder 120 with the least significant bit of the o~tput from digital adder 117 being accorded the same weight as the ~ost significant bit of the output from third staOe 114. Thus, the digital addition in adder 120 provides~a l~-bit digital output at its output terminals:l201-12012. In a manner s~milar to that d~scribed above with reference to Figs. 3,4A and 4B9 the 12-bit : digital out~ t of converter 110 according to this invention is made to accurately correspond to the sampled incoming analog signal even when inaccuracies exist in the voltage level reference signals applied to the comp2rators andlor in the comparing:operations of the comparators, particularly in the first and second conversion stages 112:and 113.
: In the above described analog to digital converter 10' according to th~ invention,~the desired offset cf the :
range of the v~ltage level reference signals applied to the :
.~ ~
~ -25 '''~ , .

., 3'J~ 3 comparatorS i~ the fine or second parallel conversion stage or unit 13 ', that is , t~ o:Efset of the converting range of such unit 13', in respect to the steps in the voltage level reference signals applied to the comparators in the coarse or firs~ parallel conversion s,tage or unit 12 ' has been provided by upwardly of~settin~ the voltage level re~erence signals in stage 12' 9 for example, from Es,2Es,3ES- -31ES to (1~1/23ES, (2+1/2)Esg ~3~1/2Eg)~~(31~1/2)Es~ respectl~ely. However, i desired, the advantages of this invention can be similarly realized by dow~wardly offsetting the voltage level xeference :~
signals applied to t~e comparators of the first or coarse parallel con~ersion unit or stageO
For example, as shown on Fig. 6, an anlog to digi~al con~erter 210 acco~ding to this invention for converting an incoming video o~ o~her ana~og si~nal applied to an input terminal Zll into an 8-blt di~ital ~utput may comprise a irst or coarse parallel conversion unit or stage 212 having a 5-bit di$ital output and bein~ generally similar to the conversion stage 12' o~ Fig. 3 in that it has (25-1) or thirty-one comparators which compaxe the incoming analog signal with respective voltage level reference signals having - ;
ma~nitudes that descend i n steps or increments of EsO However, in the conver5ion stage 212, the successive voltage level reference signals are ofset downwardly by, for example, lES
so that the sma~les~ reference signal is (1-1/2)Es or and the remaining voltage level reference signals are {2-1/2~Esg (3-l/23Es~ (3l-l/2)Es~as indicated at ~I~ on Fig. 7.

2 6 -~ 8~

The 5-bit digital output from conversion stage 212 indicated at tII) o~ Fig. 7 is reconverted to an analog signal indicated at (III) on Fig. 7 i~ a digital to analog converter 217, and the resulting analog signal is subtracted from the sampled incoming analog si~nal applied to terminal 211 in a subtracter 218 so as to provide a difference analog signal Lndicated at (IV) on Fi~g. 7. In the converter 210, a bias of, for example, Es is applied by a bias shifter 2L4 to the analog difference signal from subtracter 218 to provide a bias-shi:ted analog differencP signaL as indicated at (~J~ on Fig. 7. Such bias-shifted analog diference signal is then su~j ected to a fine conversion in the secoIld or fine parallel. conversion st~e or unit 213 which may be the same as the stage or unit 13' previously described with reference to Fig. 3, and which provides a corresponding b, bit digital output indicated at (VI) on .
Fig. 7. In~the stage or unit 213, the bias-shi~t~d ana~og differe~ce signa~ is co~pared with voltage level re~erence signals ha~ing magnitudes which descend in unit increments of, for example, 2E~(2K-l), that is 2ES/15, from a maximum voltage leveL reference signal of 2ES to a mini um voltage leve~
reference signal of 2Es/lS. Thus,;the range of the voltage level reference signals employed in conversion stage 213 is again larger than~ and ofset in respect to,the steps of th~ ~:
~olta~e ~evel reference signals employed in the precedino .
conYersion stage 2120 : - ~

'-.

~ ~7;~

The 5-bit digital output froGl coarse conversion stage 212 and the 4-bit digital output from fine conversion stage 213 are applied to respe~:tive inputs of a digital aader 222 which gives equal weight to the least signiricant bit or the output from stage 212 and ~o the most si"nificant bit of ~he output from stage 213 so as to provide a resulting 8-bit digital output, as indicated at (VII) o~ Fig. 7. Finally, as shown, a generator 215 p~ovides a 4-bit digital output 1000 which corresponds to the voltage value Es~ and which ls subtracted dLgitally, in a digital subtracter 216, from the 8-bit digital output c~f adder 222 so as to provide an 8-bit digi al output, indicated at (VIXI~ on Fig. 7, at t~e output terminals 2l6l-2l68 o~ the subtracter 216.
I~ will be seen from Fig. 7 t~at the parallel-serial analog to digital converter 210 according to this in~ention will provide an 8-bit digital character at the output of ~ubtracter 216 which accu~ately corresponds to the sampled inc~ming analog signal even if the comp2rators or the coarse ~ :
0nversion stage or unit 212 do not accurately compa~e the signals applied thereto, or if the actual voltage level reference signals applied to such comparators have values (1^112)E' S~ (2-l/23E' 9, (3-1/23E:' s~~~ (31-112)E' s whic'n mAy differ from the respective desired values by 2s much as 1ES
as shown at (I) on Fig. 7. Increasing values of the inco~ing .
video or other analog signal applied to input terminal 211, as indica~ed at . (I) j will ~effect the changes in the log:ics of the S-bit digital output ~roL~ conversiorl stage 212 shown at (II).

'' ~ 5 In response to such changes in the digital output from stage 212, the analog output from digital to analog converter 217 will vary in a stepwise manner, as indicated at (III), with each step in the output from converter 217 corresponding to a respective ineremen~ or step in the voltage level re~erence signals applied to the comparators in conversion stage 212.
For variations of the incoming analog signal between the steps of the vol~age level reference signals actually applied to ~he comparators in conversion stage 212, the bias-shited diffe~ence analog signal applied ~o ~he fine conversion unit or stage 213 will always lie in the range between O and 2ES, as indicated at (V3. Therefore, for variations o- the inco~ing analog signal between two successive actual voltage level reference signals, for example, between tl~l/2)E's and (2-1/2)E's, the rour bits of digital information appearing at the output of stage 213 will have logics ranging from ~000 to 1111, as indicated at (VI) on Fig. 7.
When the 5 bit output from stage 212 is digitaLly added to the 4-bit output from stage 213 with the least significant bit o the output ~rom stage 212 (II) being given the same weight as the most significant bit fro~ stage 213 and the digital character 1000 is subtracted therefrom, the resulting 8-bit digital output from subtracter 216 has the logics indicated at (VIII) on Fig. 7. It will be seen that, even though the actual voltage level reference signals applied :`
to the first and second comparators in conversion stage 212 are shown at (I3 to have values (1-1/2)E's and (-2-1/23Ets that , -2g-- -~u~

are respectively greater than the intended values (l-l/2)Es and ~2-1/2)Es, the 8-bit di~ital chaxacter obtained from subtracter 216 for a sampled incoming analog signal ranging, for example, from Es to 2ES, correctly has logics rangin~
from 00001000 to OOOOllll,as shown at (VIII) on Fig. 7.
Aocordingly, when the digital output from con~erter 210 is subsequently reconverted to analog form, the resulting analog signal will accurately correspond to the original incoming analog signal~
Although illustxative embodiments of the invention have been described in detail herein with reference to ~he accompanying drawings, it is to be understood that the invention is not limited to those precise embod~ments, and that various changes and modifications may be effec~ed therein by one ~`~
skilled in the art without departing from the scope or spirit . .. ..
of the invention as defined in the appended claims.

. 30

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An analog to digital converter comprising a plural-ity of parallel conversion units in a serial arrangement com-prising a preceding parallel conversion unit and a following parallel conversion unit for specifying respective groups of decreasingly significant bits of a digital character, each of said parallel conversion units including a number of comparators having first inputs for receiving an analog signal and second inputs for receiving respective voltage level reference signals and encoder means receiving the outputs of said comparators for providing an encoded output specifying the most significant group of bits of a digital character corresponding to the analog signal received by said first inputs of the respective compara-tors; an input terminal for receiving a sampled analog input signal said input terminal being connected to said first inputs of the comparators in said preceding parallel conversion unit to supply said sampled analog signal thereto; means interposed in said serial arrangement of parallel conversion units for re-converting the most significant group of bits to an analog signal and subtracting the reconverted analog signal from said sampled analog input signal to produce an analog difference signal and for applying the analog difference signal to said first inputs of the comparators in the following parallel conversion unit;
means for applying to said second inputs of the comparators in each of said parallel conversion units voltage level reference signals of magnitudes which descend in respective voltage steps, with the lowest voltage level reference signal applied to the lowest level comparator of the preceding parallel conversion unit being substantially different from the remaining voltage level reference signals for each of the other comparators in the pre-ceding parallel conversion unit and the range of the voltage level reference signals for said following parallel conversion unit being larger than, and offset in respect to, said steps of the voltage level reference signals for said preceding par-allel conversion unit; and digital adding means adding the en-coded outputs of all of said parallel conversion units with the least significant bit of the encoded output from said preceding parallel conversion unit and the most significant bit of the encoded output from said following parallel conversion unit being accorded the same weight.

2. An analog to digital converter according to claim 1 in which said preceding parallel conversion unit is a coarse parallel conversion unit and said following parallel conversion unit is a fine parallel conversion unit, and said steps between the successive voltage level reference signals applied to the comparators in said coarse conversion unit are substantially equal to each other and are different from the lowest of said voltage level reference signals applied to said lowest level comparator in said coarse conversion unit.

3. An analog to digital converter according to claim 2, in which said lowest voltage level reference signal applied to said lowest level comparator in said coarse conversion unit is substantially larger than each of the rest of said steps between the successive voltage level reference signals applied to the other comparators in said coarse conversion unit.

4. An analog to digital converted according to claim 3, in which said lowest of the voltage level reference signals applied to said lowest level comparator in said coarse conver-sion units has a value of approximately (1+?)Es with Es being approximately the value of the voltage of the remainder of said steps between the successive voltage level reference signals in said coarse conversion unit, and each of said steps of the voltage level reference signals applied to comparators in said fine conversion unit have values of approximately 2Es/(2K-1) with K being the number of bits of said digital character in said encoded output from said fine conversion unit.

5. An analog to digital converter according to claim 4 in which said encoded output from said coarse conversion unit is made up of 5-bits of said digital character, said encoded outputs from said fine conversion unit is made up of 4-bits of said digital character, and the least significant bit from said coarse conversion unit is accorded the same weight as the most significant bit from the fine conversion unit so that the output from said digital adding means is an 8-bit digital character.

6. An analog to digital converter according to claim 2, in which said lowest voltage level reference signal applied to said lowest level comparator in said coarse conversion unit has a value substantially smaller than each of the rest of said steps between the successive voltage level reference signals applied to the other comparators in said coarse conversion unit.

7. An analog to digital converter according to claim 6, in which said smallest voltage level reference signal applied to a comparator in said coarse conversion unit has a value of approximately 1/2Es with Es being approximately the voltage value of said steps between the successive voltage level reference signals in said first conversion unit, said range of the voltage level reference signals in said fine conversion unit is approxi-mately 2Es, and said steps of the voltage level reference signals in said fine conversion unit have values of 2Es/(2K-1) with K
being the number of bits of said digital character in said encoded output from said fine conversion unit.

8. An analog to digital converter according to claim 7 in which said encoded output from said coarse conversion unit is a 5-bit digital output, and said encoded output from said fine conversion unit is a 4-bit digital output so that the output from said digital adding means is an 8-bit digital character.

9. An analog to digital converter according to claim 7, further comprising means for upwardly biasing said analog difference signal by the voltage value Es, and means for digital-ly subtracting said digital voltage representing the voltage value Es from the output obtained from said digital adding means.

10. An analog to digital converter according to claim 1, in which said parallel conversion units comprise first, second and third parallel conversion units for effecting coarse, finer and finest conversions, respectively, of the sampled analog input signal; and said digital adding means includes a first digital adder for adding the encoded outputs from said first and second conversion units, and a second digital adder for adding the digital output of said first digital adder and the encoded output from said third conversion unit.

11. An analog to digital converter according to claim 10, in which said steps between the successive voltage level reference signals above said lowest level reference signal in said first conversion unit are equal to each other and are each smaller than the lowest level said reference signal in said first conversion unit, and steps between said successive voltage level reference signals in said second conversion unit are equal to each other and are each smaller than the smallest of said voltage level reference signals in said first conversion unit.

12. An analog to digital converter according to claim 11, in which said lowest level reference signal in said first conversion unit has a value of approximately (1+?)Es with Es being approximately the value of said steps between the succes-sive voltage level reference signals above said lowest level in said first conversion unit; said lowest level reference signal in said second conversion unit has a value of approximately 3Es/(2K-1) with K being the number of bits in said encoded out-put from said second conversion unit, and said steps between the successive voltage level reference signals in said second conversion unit above said lowest level in said second conver-sion unit each have a value of approximately 2Es/(2K-1); and the lowest of said voltage level reference signals in said third conversion unit has a value of approximately , with K' being the number of bits in the encoded output from said third conversion unit, and the steps between the successive voltage level reference signals in said third conversion unit are each substantially equal to said value of the lowest level reference signal in said third conversion unit.

13. An analog to digital converter according to claim 12, in which the encoded outputs from said first and second conversion units are respective 5-bit characters, the encoded output from said third conversion unit is a 4-bit character, the least significant bit from said first conversion unit being accorded the same weight as the most significant bit from the second conversion unit, and the least significant bit from the second conversion unit accorded the same weight as the most significant bit from the third conversion unit so that the output of said second digital adder is a 12-bit digital character.

14. An analog to digital converter according to claim 12; in which the range of said voltage level reference signals in said second conversion unit is approximately 2Es, and the range of said voltage level reference signals in said third conversion unit is approximately 4Es/(2K-1).