CA1070020A - Method and apparatus for recognizing handwritten characters in an optical character recognition machine - Google Patents

Abstract

METHOD AND APPARATUS FOR RECOGNIZING HANDWRITTEN
CHARACTERS IN AN OPTICAL CHARACTER RECOGNITION MACHINE
ABSTRACT OF THE DISCLOSURE
Handwritten character recognition is facilitated in an optical character recognition machine by electronically scaling-down the size of received characters, both in height and width, to normalized dimensions. The scaling-down factors are rendered adjustable as a function of the dimensions of the received character. Actual recognition is rendered highly reliable by employing a time-shared electronic mask which tests the received characters for the following features, in sequence: Top horizontal line; upper left and/or upper right portion line crossings; mid-portion horizontal lines; lower left and/or lower right portion line crossings; and bottom horizontal line. Recognition of the character is effected by decoding the test results.

Description

CROSS l'~FERENCE TO RELATED PAT _TS
This application discloses a sub-system portion of the optical character recognition machine disclosed in the following U.S. patents: Patent No. 3,812,459, issued to John H. MacNeill and Ronald R. Willey on May 21, 1974 and entitled "Improved Optical Scan ~rrangement for Optical Character Recognition Systems"; Patent No. 3,872,443, issued to Thomas G. Holmes, Harrison B. Lidkea and Kenneth L. Selb on March 18, 1975 and entitled "Optical Character Recognition System"; and Patent No. 3,848~228, issued to John H. MacNeill on November 12, 1974 and entitled "Visual Display of Unrecogniaable Characters In an ~ .
Optical Character Recognition Machine". References to the disclosures in the aforementioned Patents are made herein.
BACKGROUND OF TXE INVENTION
The present invention relates to a method and apparatus for recognizing handwritten characters in an optical character recognition machine.
Recognition of handwritten data in prior art optical character recognition machines has presented substantial problems. Unlike standardiZed machine print which presents characters in a fixed format for relatively straight forward recognition by processing circuitry, handwritten characters can vary substantially from the recommended format in ` accordance with thP care taken by the individual responsible ! for writing the data. Conseqùently, both the height and ~ - 2 ~

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width of handwritten characters can vary siynificantl~ from a pre-specified format, in which case recognition by standard prior art optical character recognition machines is impossible.
Although not expressly described in terms of optical character recognition, U~S.Patent No.2,96~,7;4 issued December 13, 1960 to George P.West describes an electronic handwritten character recognition approach which allows considerable character configura-tion variation without introducing recognition error.The characters to be recognize~;l by the system of the West patent are transcribed with a substance designed to vary an electrical characteristic such as current conductance, flux permeability or capacitive charge. The sensing device includes agroup of sensing elements or electrodes which are arranged to detect predetermined condi-tions or features in a character configuration. In efEect, these electrodes look for line crossings at different locations within the character and decode such line crossings to provide an indication of the character.
The technique described in the aforementioned West patent i5 far more suitable for use in optical type character recognition machines than the techniques presently used in most such machines. However, the West technique of detecting line crossings in various character locations is faced with a number of practical problems when used in optical character recognition machines. Specifically, there is no method described in the West patent which effects compensation for variations in character size. In addition, it has been found that tne Wes-t approach te;^,ds to confuse certain characters which are : .

visibly distinguishable by the presence or absence of horizontal lines at one or more locations in the character. ~rhe reason for this confusion is the fact that the West app~oach tends to look only for line crossings rather than horizontal features in the characters being recognized.
It is therefore an object of the present invention to provide a highly reliable method and apparatus for recognizing handwritten characters in an optical character recognition machine.
It is another object of the present invention to provide a metho-~ and apparatus which automatically compensates for variations in size of handwritten characters to facilitate recognition of such characters in an optical character recognition system.
lS It is still another object of the present invention to provide an optical character recognition system in which the technique d~scribed in the aforementioned ~est patent is expanded to test for character features in addition to line cxossings to thereby render recoc~nition more reliable.
2n SUMMARY OF THE INVENTION ~:
In accordance with one aspect of the present invention, handwritten character recognition in an optical character recognition system is rendered more re~iable by employing an electronic mask which is time shared to test for different 25 features of characters being shifted through the mask. ' Specifically, the tests are performed in sequence for the following char~cter features: ~op horizontal line; upper left :

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1 and/or upper right portion line crossings7 mid-portion horizontal line; lower left and/or lower r~ght portion line crossings; and bottom horizontal line. Primary recognition is effected on the basis of the results of the tests for the top line, mid-portion line, bottom line and upper left line crossing. Ambiguities axe resolved on the basis of results from the tests for line crossings in the upper right, lower left and lower right portions of the character.
In order to facilitate processing of the hanclwritten characters, each character is scaled down to a standarcl size before bring passed to recognition circuitry. Different scaling factors are utilized so that the scale factor for any character may be automatically selected on the basis of the received character size.
In accordance with the present invention there is provided an optical character recognition machine comprising- ;
quantizing means for temporarily storing binary signals in a form to physically represent a received character examined by said machine, each binary signal designating the presence or absence of a character portion in a respective physical location;
scaling means including means for monitoring the size of the represented chaxacter, and means for deleting certain stored binary signals in accordance with a predetermined pattern to reduce the size of the represented character to a normalized size;
means for testing the~binary signals comprising the normalized character for the presence of predetermined character features; and 3~ means for decoding the results o testing said binary signals to identify said represented character;

wherein said quantizing means represents saicl ~ ~ ~ S-" ~7~2~

1 received character in a matrix of binary signals at grid locations comprising m columns and n rows wherein said m columns are arranged along the height dimension of the represented character and said n rows are ,arranged along the width dimension of the represented character, and wherein said means for testing comprises:
mask means including m shift registers of less than n stages each;
means for shifting said represented character through said mask means, parallel by column and serially by row only, each column being shifted through a respective mask shift register; and means for monitoring the shifted character for specific features at predetermined mask locations during each of a plurality of character positions in said mask means.
Also in accordance with the present invention there is provided a method of recognizing handwritten characters in a character recognition machine of the type in which characters to be recognized are converted into quantized characters made up of binary signals such that each binary signal represents a grid location in a two-dimensional matrix and wherein the level of each binary signal designates the presence or absence of a projected character portion at the grid location represented by that binary signal, said method of recognizing handwritten characters comprising the steps o:
positioning the quantized character at a reference location within said matrix;
normalizing the quantized characte~ to a standard siæe by combining the binary signals at pre-detarminecl grid locations in accordance with the size of said quantiæed character;

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1 translating the normali2ed character through a mask of shift registers, said txanslating being effected by shifting the binary levels at said matrix grid location through said mask only in parallel along one entire matrix dimension and only serially along the other matrix dimension;
monitoring plural combinations of prescribed mask locations, for at least one position of said normalized character as it is translated through said mask, to detect predetermined character ~eatures at said prescribed mask locations; and processing detected character features from each normalized character to determine the identity of that character.

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BRIEF DESCRIPTION OF TH~ DRAWINGS ~:
The above and still further objects, features and ::
advantages of the present invention will become apparent upon . -:
consideration of the fo~lowing detailed description of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings, wherein:
FIGURES 1 through 16 are individual schematic diagrams of the circuits which comprise the handwritten scalar unit; ~:
FIGURES 17 through 26 are schematic diagrams of : individual circuits which comprise the handwritten mask - :
logic unit;
: FIGURES 27 through 38 are schematic diagrams of individual circuits which comprise the handwritten decoder unit of the present invention; .: .

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FIGURES 39 throuc3h 48 are graphical representations of the hanclwrittell mask locations utili~ed in testing Eor a line crossing i.n the upper left portion of a character;
FIGURES 49 through 5~ are graphically representations of the handwritten mask locations utilized in testing for a line crossing in the upper right portion of a character;
FIGURES 55 through 59 are graphical representations of the handwritten mask locations utilized in testing for a line crossing in the lower left portion of a character;
FIGURES 60 through 66 are graphical representations of the handwritten mask locations utilized in testing for a line crossing in the lower right portion of a character;
FIGURE 67 is a chart illustrating how various columns are combined in the handwrltten scalar for purposes ~:
of effecting the different width reduction ratios;
:
: FIGURE 68 is a chart il.lustrating how the various rows are combined in the handwritten 5calar for purposes of , .
effectiny the different height reduction ratios;
~ FIGURE 6~ is a functional block diagram of the-~; 20 ~ recognition circuitry of an optical character recognition ;machine employ1ng the handwritten recognition circuitry of :
the present invention; and FIGURE 70 i9 a graphical representation of a normalized handwrltten character matrlx illustratlng the 25~ : posit~ions of the various tests and the locations of the handwritten~mask at dlffèrent test tlmes~ all relative to an overlayed character "3"~

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DESCRIPTION OF THE PREFERRED EMBODIMENTS
I. General The optical character recognition system described herein is part of the same system described in each of the U.S. patents listed in the CROSS REFERENCE TO RELATED
PATENTS section of this application. Al:L of those applications are assigned to the same assignee as the present invention. Those aforementioned patents are concerned with the optical components, the document handling mechanism, system control logic and machine print character recognition circuitry for an optical character recognition system. The present invention relates to cir-cuitry for processing and recognizing handwritten characters ~-in the same system. To this end the circuitry disclosed in ~-Figures 1 through 16 herein is intended to replace the cir-cuitry in Figures 92 and 96 of the aforementioned U.S. patent 3,872,443 whereby the system disclosed in that application -is rendered capable of processing and recognizing both machine print and handwritten print characters. Numerous references are made herein to components of the system illustrated and described in ~he aforesaid U.S. patent 3,872,443.
In order to facilitate signal tracing between the numerous schematic diagrams disclosed herein, and between the schematics herein and those in the aforementioned U.S. patent 3,872,~43, each component illustrated ~)7~Z~
illustrated herein, ~ut not in said a~orementioned patent, bears a five digit reference numeral in which the first digit is "2", the second and third digits correspond to the fiqure number herein in which the element or component is found, and the last two digits identify that component or element in the figure. An input signal received by an element bears a parenthesiz~d numeral designating the element or component from which that signal originated. Likewise an output signal from an element or component bears the reference numeral of the component or element receiving that signal.
Certain signal sources or destinations are located in circuits~ -illustrated in the aforementioned U.S. Patent 3,872,443;
those sources or destinations are designated either by a four~digit number, or a five-digit number having "1" as a first digit. In either case, the source or destination number identifies a figure number and component in the application. In this manner signals and logic operations can be traced from schematic to schematic and, more particular~y, from element to element throughout the entire system. The one exception to this approach relates to timing signals TPA, TPB, TPC, TPD, TPE and TPF which originate in the circuits of Figure 8 of the aforementioned U.S.Patent 3,872,443, and are utilized throl-ghout the system without bearing source or destination reference designation.
Particular voltage levels are not specified herein unless necessary to an understanding of the system operation.

For ease in reference, however, a convention is employed in ' .

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which 1ogic one constitutes a relatively higi or po~itive voltage whereas logic zero constitutes a relatively negative or ground voltage.
The drawings in this application and in the afore-mentioned U.S.Patent 3,872,443 disclose the entire system fo, purposes of the present application, and signal tracing from drawing to drawing will provide those of ordinary sklll in the art with a complete understanding of all functions capable of performance by the system. To facilitate an understanding of the.inventive concepts of the present invention, the approach employed herein in describing the system is to -describe in detail only those portions.of the system which relate to the inventive functions, whereas conventional functions and operations performed ~y the system are not described in detail. Consequently, while substantially all of the illustrated components bear reference numerals, only those components which relate to the inventive functions are described in detail. ~ -It will also be understood by those skilled in the field of optical character recognition systems that the approach to handwritten recognition described herein can be utilized in the recogntion of substantially any handwritten characters. For purp~ses of facilitating the present description, however, only recognition of numbers 0 through 9 is de~,cribed in detail.
Referring initially to Figure 69 of the accompanying drawings, the recognition circuitry of the optical character , _9_ .

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recogni~ion system is illustrated in functional block form.
This ~lock diagram is similar to that in Figure 2 of the aforementioned U.S.Patent 3,872,443 except that handwritten scalar 211 h~s replaced horizontal' S and vertical scalar 203, and handwritten mask logic 212 and handwritten decoder 213 have been added. The basic timing for the recognition circuits is illustrated in the timing Aiagram of Figure 49 o the aforementioned U. S. Patent 3,872,443. The basic timing for the recognition circuits is controlled by the multiplexer counter located in quantizer and multiplexer 202. The multiplexer counter defines one timing interval, designated herein as an MUX interval, for each six successive master timing pulses. There are sixty-four MUX intervals for each recognition circuit cycle. During one ~UX interval in each sixty-four interval cycle, the sixty channels of data detected by photo-diode array 201 are sampled and stored in parallel in a register quantizer and multiplexer unit 202. This data is then transferred in parallel to a shift register rom which it is shifted out serially durinq the remaining sixty-three MUX intervals (i.e. one shlft per interval)~ The serial data is received at handwritten scala 211 where it is placed in thirteen columns for machine print recognition and in fifteen columns for handwritten recognition.
The columns of shift registers effectively serve to reconstitute the samples or vertical slices of data characters to permit recognition of the machine print characters by mask circuitry at unit 204 a~d of handwritten characters in handwritten , .
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mask logic circuitry 212. The machine print mask circuitry is described in detail in the aforementioned U.S. Patent 3~72,4~3.
Handwritten recognition and processing begins at the S handwritten scalar 211 where the serial data from the quantizer multiplexer 202 is first oriented into thirty-two sixty-four-~!it shift register columns in order to accommodate characters of varying width. The scalar 211 then normalizes the character appearing in the thirty-two columns, both in height and width, to provide fifteen columns (i.e. channels), each column being twenty-four bits in length. These fifteen columns of data are examined by the handwritten mask logic 212.
At the handwritten mask logic unit 212 there is provided a fifteen column by eight row mask grid which is time shared to perform different tests on a character progress-ing through the fifteen column by twenty-four row shift register matrix. The tests involve determining whether the character passing through the mast has c~rtain eatures.
Different combinations of these features, if present, identify the character being processed. The features tested for include: A top horizonta~ line; mid-portion horizontal line;
bottom horizontal line; and line crossings in the upper left, upper right, lower left and lower right portions of the character.
25The results of the tests are evaluated at the handwritten decoder 213. Depending on the character features detected, decode~r 213 provides a four bit output signal, ' ' ', ~ ,, -11- '' '' ' .

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coded to identify the reco~rlized character. In addition to decoding the test results, the handwritten decoder provides various timing signals to permit time sharing of the handwritten mask and also compares test results to determine if recognitlon error conditions exists.
The individual circuits represented by blocks 211, 212 and 213 in Figure 69 are illustrated in detail below and the figures noted in parenthesis inside of these blocks.

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II. HANDWRITTEN SCALAR
The handwritten scalar is illustrated in Figure 1 through 16 and performs two main functions. The first of these is to store as much as thirty-two columns of data, each 5 column belng sixty-~our elements high. Thus, an adclitional nineteen columns o;~ storage are required to supplem~nt the thirteen c~lumns o~ machine print mask storage illustrated in Figure 33 of the aforementioned U.S.Patent 3,872,443.
The additional nineteen registers (20115-20125 and 20211-2.0218) are illustrated in Figure 1 and 2 of the accompany-ing drawings. These registers are each sixty-four bits :in length.
The data input to the shift ~egister is MUXSDG (MUX
serial data gated~ which is provided by AND gate 20230. rrhis gate receives the MUXSD signal from the quantizer-multiplexer a~d the BLKS EN 1 signal from the da~-a control circuits. The MUXSDG signal can be controllably inserted at a number of locations along the chain of thirty-two serially connected shift registers which comprise the handwritten mask storage. For example, the MUXSDG data can enter at column thirty-two (shift register 20115) by a gate 20102 for handwritten 4.3 pitch ~-operation. For handwritten 5 pitch operation MUXSDG data enters at column 25 (shift register 20122) via AND gate 20114, OR gate 20113, and NA~D gate 20109. For 7B font operation the MUXSD data enters the mask storate at column 18 (shift register 20214~ via AND gate 20210, OR gate 20209, and NAND
gate 20204. Alternatively, the additional nineteen columns may be by-passed entirely. In other words, for OCR-A font ., ' ~. :
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operation, the ~UXSDG data isprovided -through AND ga~e 20227 and OR gate 20228 as the MUX C~L 13 signal which is applied directly to the thirteen columns comprising the machine print mask storage illustrated in Figure ~3 of the aforementioned U.S.Patent 3,872,443.
As is the case with the thirteen shift registers 9301-9313 in the machine print mask storage, the output stage of each of the additional nineteen shift register columns is fed to the input stage of the next lower column, this feed being effected, however, through NAND gates 20103-20112 and 20201-20208 which are enabled by the RDEN (read enable) signal. The registers are thus cleared within sixty-four MUX count in~ervals after the RDEN signal goes ]ow.
The ability to change the point of insertion of the 15 MUXSDG data effectively permits changing the length of the overall register (i.e. changing the number of active columns~
as a function of the font to be recognized. In other words, the higher numbered columns are blocked from receiving data when the operative font re~uires fewer than thirty-two columns ~ -for recognition. The second main function of the handwritten scalar is to scale down the width of the received handwritten character being processed from a received range of 12-32 columns to a processing range of 12-15 columns. It also scales the height of the received character from a received rangQ of 20-48 elements or rows to a processing range of 20-24 elements or rows. Width scaling is performed by the circuits illustrated in ~igures 3, 4 and 5 of the accompanying drawings~ ;

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The first operation required for width scaling is a determination of -the width of the received character. The width and horizon-tal position oE the recelved character is moni-tored by registers 20301 through 2030~ in Figure 3. These registers are utilized as ones ca-tchers, there being a storage bit ~Wl through W32) for each of columns 1-32 ti.e. shift registers 9301-9313, 20102-20112; 20201-20208; gate 20229).
In other words, all storage bits Wl-W32 are fed in the ones catching or RS mode. In this way any black (i.e. binary 1) appearing for any shift pulse at anytime appears as a low or zero at the corresponding input terminal in registers 20301-20308 and is entered into the respective storage bit at DEW
time. At the end of the DEW pulse a high or binary 1 appears at the output of the storage bito Thus, if a black ~ccurs at the input to the shift register during any of the vertical sixty four shift pulses (i.e. during any MUX count cycle), the corresponding storage bit latch is set. In other words, the storage bit corresponding to that particular column is set. The output of that bit remains high until the end of the vertical shift period at MUX63 time. In this manner the outputs of the various storage bits go high at MUX63 time if the corresponding columns contain one or more black bits during a sixty four count MUX cycle. In essence, the horizontal projection of any image proceeding through the shift register columns is denoted by output signals Wl through W32. For example, if a character of thirty-two columns in width is in the mask, all signals Wl through W32 are high; absence 3f a ~15-~, f~

character portion from any column results in a corresponding low W signal for that column. The horizontal projection moves through the storage bits starting at W32 and moving do~n towards Wl, one position during each ve~tical scan interval (i.e. 64 count MUX cycle).
Characters enter the thirty-two columns o mask storage at the highest numbered acti~e column and proceed serially by bit to the lower numbered columns. By definition, the mask centered condition occurs when Wl goes low and W2, W3, W4, W5 and W6 all go high. At this time stoxage bit signals W14 through W24 are examined for the purpose of determining how many consecutive white-only colum~s follow the last column (or trailing edge) of the centered character.
Thls in effect identifies the right hand edge o~ the character which the centered character has proceeded through the mask.
The logic for performing this scale determination is illustrated in Figure 6 of the accompanying drawings. If any~of signals W14~ W15, W16, or W17 are low, negative OR gate 20601 is activated to provide a high Wl:l signal, Inverter 20602 provides a low Wl:l signal which inhibits gates 20603 and 20605. Under these conditions no reduction in width is required~ If however W14 through W17 are all high but any of W18 through~W21 are low, gate 20606 is enabled and actuate~
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` gate 20603 to provide a~high W5:4 signal. The latter acts , throug~ inverter 20604 to inhibit ~0605. Under these conditions a 5-to 4 (20~) reduction in character width is required. If Wl4 throu~h W21 are all h~igh, but a low occurs in any of W22 . . , ~ .

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through W25, gate 20607 lS enabled and actuates gate 20605 to provide a high W3:2 signal. This indicates that a 3 to-2 (330/O) reduction in character width is required. If none o~ bits W14 through W25 are zero, indicating that each of columns 14 through 25 con~ain black bits, the Wl:l, W5:4, and W3:2 signals are all low. This indicates that a 2-to-1 (50%) character width reduction is necessary. These gates thus have the characteristics of a priority encoder wherein the lowest numbered blank column has control over the width reduction division ratio. Consequently the next character traversing the mask cannot affect the division ratio~ even if it occurs within one or two columns of the centered character.
Gates 20608, 20609 and 20610 are utilized as a four line to two bit encoder. When a l-to-l reduction ratio is required, the Wl:l signal enables both gates 20608 and 20609 to render both the W31 and WB2 signals high. If a 5-to-4 ratio is required, the high W5:4 signal enables gate 20609 and only WB2 is high~ Similarly, when W3:2 is high gate 20608 is enabled and only WBl is high. If all three signals are low, indicatiDg a 2-to-1 width reduction ratio, neither o~ ~Bl and WB2 are high.
The WBl and WB2 signals are utilized to control slgnal selection at data selector multiplexers 20508-20521 illustrated ln Figure 5 of the accompanying drawings. These data selector multiplexers are four line to one line selectors and serve to select between di~erent shi~t register column output signal and output slgnals~from dlfferent gates 20401-~: ~
20421. The latter effectively serve as~ ne~ative OR gates , ~L~71)~

to combine difEerent pairs of adjacent shift register column output signals. Typical of -the operation of these gates is gate 20401 which receives the COL2 and COL3 signals. Its 2 ~ 3 output signal is high only if both input signals are high;
that is, when there is no black element in both columns 2 and 3. In this manner gates 20401-20421 effectively OR the blacks condition of adjacent columns.
Figure 67 indicates graphically how width reduction is effected for the various reduction ratios. For example, for a 5-to-4 width reduction ratio, the received COLl signal is fed to handwritten register 20529 to provide the CHANl signal, the received COL2 signal is fed to handwritten register 20529 to provide the CHAN2 signal, and the recelved COL3 signal is fed to the handwritten 20529 to provide the CHAN3 signal, however, the 4 + 5 signal is fed to handwritten register 20529 to provide the CHAN4 signal~ Then, column 5 is put on channel 4, column 6 on channel 5, column 7 on channel 6 and the 9 + 10 signal is used for the CdAN8 signal. In like manner, every fourth and fifth column signals are OR'd together to provide every fourth handwritten channel signal so that the C~A~15 ; signal comprises the 18 ~ 19 si~nal. This selection is made , possible at data selectors 20508-20521 because WBl is high and WB2 is low for the 5-to-4 width reduction ratio. For the to-1 width reduction, WBl and WB2 are both high, whereby the 25` ~ifteen column slgnals are e~ployed as corresponding channel signals. The 2-to-1 width reduction ratio requires both WBl .
and WB2 to be low, whereby the CO inputs to data selectors 1~7(~
20508-20521 are ~elected. It should be noted that the COLl and COL2 signals are combined only for 2-to-1 width xeduction under the control of gate 20522. Otherwise the COLl signal is always pro~ided at the output oE gate 20523. However, when

2-to-1 width reduction is required, the W2-1 signal is low at gate 20522 and permits the state of the COL2 signal to be applied to gate 20523 where it is effectively OR'd with the COLl ~ignal.
In addition to reducing the image width to between 12 and 15 columns, the handwritten scalar approximately centers the image in the 15 column handwritten mask storage. That is, if the reduced image is 12 or 13 columns ln width, the image is automatically transposed one column to the right, so that channel 1 is blank and channels 14 and/or 15 are blank. When the reduced image is 14 or 15 columns wide, column 1 of the reduced image goes to channel 1 of the handwritten mask, ; leaving either no blanks or one blank at channel 15. This is the reason for the second set of multiplexers 20524-20527 in Figure 5. Th~se are quadruple 2-to-1 multiplexers which are addressed by the SLB signal. The SLB signal is generated in the circuit of Figure 6. SLB is high lf either W14 or W15 is l~w during l-to-L scaling (gates Z0611, 20612, 20614); or if during 5-to-4 reduction W18 is low tgates 20613, 20614); or ; if during 2-to-1 reduction W26, W27 or W28 is low (gates 20615, :: :
25~ 2061~, 20614)o It i5 important to note that the width determination lS perormed during the same vertical shift period in which the .

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~7~)Z~) mask centered condition is reached; in other words, when the leading edge oE the character is in column 2. Thus, during 1-to-1 width reduction, if Wl~ or W15 is low, the image is only 12 or 13 columns wide. Normally, with signal SLB low, the A inpu-ts to the multiplexers 20524-20527 are connected through to the channel outputs; however when the SLB signal is high the B inputs to these multiplexers are connected to the channel outputs. Specifically, with SLB low, the reduced column 1 signal from gate 20523 is connected through to the CHANl output whereas when SLB goes high the signal from gate 20523 is connected through to the CHAN2 output and CHANl is connected to the positive voltage applied to the lB input of multiplexer 20524.
Registers 20529-20532 are utilized as ones catching I5 latches to scale the image vertically in accordance with the requirements of the vertical scaling process. The vertical height of the image whose horizontal projection is indicated by signals Wl-W32 is determined by the circuitry illustrated in Figure 7. All thirty-two column signals are fed in groups of eight to four NOR gates 20701,20703, 20706 and 20708. The outputs of these gates are inverted by respective inverters 20702, 20704, 20707 and 20709 whose outputs are comblned at NOR gate 20705. The VPROJ output signal from gate 20705 is high whenever a low is applied to anyone of the thirty-two ~25 shift register columns. Since all characters are continuous from top to bottom, one or more columns receives a low 5i.e.
corresponding to black bit) pulse during the entire time the ':

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charac-ter image is entering the mask storage shi~t register columns. In other words, the VPROJ signal is high for the full period during which a centered character is entering the shift registers. This VPROJ signal could be used directly to operate the vertical scalar counter, however, dirt or individual voids in the signals could possibly cause an erroneous reading.
It is desirable therefore -to be sure that the VPROJ signal results from a character image before initiating scaling. For this reason the VPRO~ signal is fed to 8-bit shift register 20801 in Figure 8. Individual dirt specks are too small to start the height count process because the height count enable (Hl' CT EN) flip-flop 20807, 20808 cannot be set until blacks have reached the QB, QC, QD, QE and QE outputs (i.e. five black columns) of register 20801 while QG is still low, as determined by gate 20805. If these conditions obtain, gate 20805 is driven low by the TPB pulse if transmission of the character to the logic circuitry is not occurring (XMIT). This low sets the height count enable (HT CT E~) flip-flop 20807, 20808, which remains set until two adjacent white columns appear at 20 ~ the QA and QB outputs of counter 20801. In such case, gate 20806 provides a low signal at TPC time to reset he1ght count enable flip-flop 20807, 20808. In this manner five vertical columns containing blacks must be obtained before the HT CT EN
slgnal goes high and two adjacent blank columns must occur before the HT CT E~ signal goes low.
The HT CT EN signal is applied to divide-by-sixteen counter 20902 wh1ch in turn feeds th~ee additional Johnson counter 3L~70~;~V

stages in -the ~orm of flip-flops 20904, 20905, 20906. These three counter bits are called the state counter. EIeight count and scaling proceeds as follows: If a mask centered condition has not occurred, at M~X63G time the output signal o:E ga-te 20903 goes low and clears counter 20902 clS well as resetting ~ohnson counter flip-flops 20904, 20905 and 20906. Thus the state counter is initially cleared to the count of 000, designated herein as state count 0. The count states defined by the three stage ~ohnson counter are decoded by NAND gates 21101 through 21106 and inverting OR gate 21107 through 21110 in Figure 11.
When the state count zero condition exists, the circuitry is primed and waits for the HT CT EN signal to go high at the EnT terminal of counter 20902. The EnP terminal at that counter is maintained high by the CS5 si~nal which is high because the count state zero condition exists rather than the count state five condition. When HT CT EN goes high, counter 20902 is clocked by TPD pulses which successively increment the count. At the trailing edge of the count of fifteen, the carry output signal (CU) from counter 2~902 is inverted by inverter 20901 and applied to the ~D terminal of the counter whereby it causes the counter to be preset to the binary number appearing at preset terminals DA, DB, DC and D . This binary number is made up of signals derived from count state decoder gates in Figure ll. Since a zero count state i9 assumed for Johnson counter stages 20904-20g06, the preset number is binary 11 at this time and this number is preset into counter 20902. At the same time the CU signal causes :

1(~7~0Z~3 the Johnson counter to advance from count state zero to count state one.
It should be noted that if the HT CT EN signal goes low before the count of fifteen is reached, the Johnson counter remains at the zero count state. This i!3 a character short condition which is reflected through gates 21101 and 21110 as an indication which is monitored at the handwritten decoder circuitry.
The top of the image must reach the QF stage of register 20801 before height count enable flip-flop 20807, 20808 is set, whereas the bottom of the image needs only to reach the QC stage of the counter before the flip-flop is reset. Thus, the duration of the high HT CT E~ signal is four MOS CLOCK periods shorter than would be required to clock the actual vertical projection of the image. This means that the transition from count state zero to count state one occurs when the vertically projected character is actually twenty counts and not sixteen counts in height.
At the beginning of count sta~e one, counter 20902 is preset to a count of eleven as previously described. Four TPD counts later the carry signal CU again goes high. During count state one the preset input signals for counter 20902 are as follows: Since it is count state one, S0~Sl is high; S2+S3 is low; CS4 is high; and 51+54 i9 low. This corresponds to a preset count of ten which is entered duriny. the tim~ the CU
signal is high, The Johnson state counter stages 20904-20906 advance to count state two wherein both signals SC'A and SCB

-~3-~C~7~Z~

are high. I~ must be pointed out once again that if at any time the HT CT EN signal goes low, the counting process stops until af-ter the following MUX63G pulse at which time counter 20902 is reset.
During state count two the preset inputs to counter 20902 are as follows: SO+Sl is low, S2~S3 is high; CS4 is high; and Sl~S4 is high. This corresponds to a preset count of seven. When, after eight additional counts the counter again reaches a count of fifteen, the state counter advances to the count state of three. For count state three the preset inputs to counter 20902 are the same as for count state two; in other words a preset of seven occursO When, after eight more counts counter 20902 again reaches a count of fifteen~ the state counter advances to count state four. At count state four the preset inputs to counter 20902 are all low; however, this is mmaterial since during the advance to count state five the -CS5 signal at the EnP terminal of the counter goes low, inhibiting further count. Thus if the HT CT EN 6ignal is still ~ high at the time count state five is reached, the counting ;20 position of counter 20902 hangs up at count state 5; this is an indication that the image of the character is too high.
The CS0 and CS5 signals are effectively OR'd togeth~r at gate 21110 to provide the CS/L si~nal which indicates that the count is too short or too long~ Th~ ~S~L signal is 25 ~ applied to the handwritten decoder to indicate this error condition. Whatever count state the state counter is in at the time the HT CT E~ signal goes Iow remains in the state ,,.$
~ -24-~37~

counter until cleared at MUX63G time. However, if during this period a mask centered condition occurs, the count rem~ins in the s-tate counter throughout the following vertica:L scan interval, which serves as the transmit time. In other words, during -transmit time the HT CT E~ signal remains low and the state counter count determined during the vertical shift interval immediately before the transmit interval remains stored.
The decoded outputs of the state counter are fed to the variable modulus counter consisting of flip-flops 21001, 21005, and 21008, and gates 21003, 21004, 21006 and 21007 in Figure 10. If the state counter stops at count state one~
during the transmit interval signal CSl is low and causes the output signal from gate 21002 to stay low and mainta~n flip-flops 21001, 21005 and 21006 reset. The CLR SHIFT EN signal is thus high, allowing continuous shift pulses to be fed to the handwritten mask circuitry. If count state two is reached before the HT CT E~ slgnal goes low, the CS4, CS3 and CSl signals are all high. In this condition the three bit counter ln Figure 10 is connected as a divide-by-five counter wheraln the C~R SHIFT EN signal lS hlgh for four shift counts and low for one shift count, deleting every fourth shift ~ulse rom the train applied to shift registers in the handwritten mask ; circuitry (Figs. 17, 18) and also deIeting every fifth ~Iear pulse from the ones~ catching latches 20301-20308 (Fig. 3~
Thls has the effect o com~inin~ the fourth~and flth rows : of the actual image in an OR function to form the fourth row :
`

.
-25- :
' ~ :

~o~

of the handwritten image to be processed~
If count state three is reached in -the state counter, signal CS3 is low, main~aining -the output signal from gate 21007 high; this converts the counter in Figure lO to a divide-by-three counter. Under -thes~ conditions the CLR SHIFT EN
signal is high or two counts and low for one count, resulting in the deletion of every third shift pulse applied to the hand-written mask shift registers and combining every second and third rows of the actual thirty~two column character image to produce every second row of the handwritten image to be processed. This is illustrated graphically in Figure 68.
If the state counter is held at count state four, signal CS4 is low, dri~ing the output signal from gate 21007 continuously high. Stages 21001 and 21005 therefore act as a divide-by-two counter and CLR SHIFT E~ signal alternates states with each shift pulse. Under these conditions every other handwritten pulse is deleted and successive pairs of rows of the thirty-two column mask are combinPd in an OR ~unction at the handwritten mask. In other words, rows one and two of the thirty-two column mask are combined in an OR unction into row one o~
the handwritten mask, rows three and our of the thirty-two column mask are combined in an OR function into row two of ~ ~, the handwritten mask, etc., producing a character height reduction of~two-to-one.~ ~ ~
25 ~ As previously~described, in addition to scaling the image, the outputs of the width-determining 1ip-flops , ~L~7S~
(registers 20301-20308) are utilized to determine i~ a mask centered condition occurs. When a mask centered condition is de-tected the process of transmitting the image from the thirty-two columns of storage to the fifteen columns oE hand-written mask begins. Mask centered detection praceeds as follows If there is no data in column one of the thirty-two column storage registers but data exists in columns two, three, four, five and six, the output signal of AND gate 21501 goes high. This high is transmitted through OR gate 21503 to provide a high HWCENT (handwritten centered) signal. A high HWCENT signal may also be provided if by the time the image has moved to column ten it is determined that the image is less than ten columns wide and fifteen rows high in either of columns ten, eleven or twelve. This is designated a ones centered condition and results in a high 1's CENT signal.
This is accomplished by the use of gate 21506, counter 21507, and gates 21509 and 215100 If the image is less than ten columns wide at the time the image has reached column ten, the signal W9 is high (indicating that column nine is vacant) ~ and one or more of signals W21, W20, Wl9 or W18 is low.
Under ~hese conditions the output signal from gate 21509 is high and, since W9 is high, two inputs of gate 21510 are primed. In addition the~COL10, COLll and COL}2 signals are inverted and combined in an OR function at ga~e 21506. Since 25~ counter 21507 ~as cleared by TPC during the previous MUX63 interval, the carry output signal is not initially high ~o that inverter 21508 i9 high and keep~ the EnP te~ninal 1070~ D
enabled. There~ore, as long as either of signals COL10, COLll or COL12 is high, gate 21506 provides a high output signal.
Both the EnT and EnP terminals of counter 21507 are enabled and the counter is clocked by TPC. Once a count of fifteen is reached, the carry signal goes high, enabling another input to gate 21510 and providing a low at the out:put o~ inverter 21508.
This disables the EnP terminal of counter 21507 and maintains a binary one at the output of gate 21506, thereby providing a high at the EnT terminal. The input at the EnT terminal must remain high to maintain a high at the carry output terminal, however, since the EnP terminal is low, further counting ceases. Thus when fifteen rows of blacks are detected, counter 21507 becomes latched with the carry signal high. If a transmit cycle has not been previously started, the XMIT
signal at gate 21510 is likawise high. The CTR BIT ONE signal, whiçh lS high during handwritten operation, is also high, so that TPB during MUX63 time drives the output signal from gate 21510 low. Flip-flop 21511, 21512 is set thereby, providing a high l's CENT signal which is fed through gate 21503 as a high HW CENT signal. Thls condition is maintained until the second TPC pulse after MWX63 time, at which time the TPC, DELAY and N/2 signals all are high, producing a low output signal from gate 21513 which resets the 1'~ CE~TERED FLIP-FLOP.
~ The high HW CENT signal at gate 21503 is fed to gate 21424 25 ~ ln the transmit control circuit of Figure 14. The uppermost input signal to gate 21424 goes high when flip-flop 21419, 21420 is s t at TPD during the MUX63 interval, and remains -2~-.

~70~
high until the second TPD pulse after MUX63. If there are at least thirty-two blacks counted by the blacks counter (counter 10702 in lig.7 of the aforementioned U.S.Patent 3,&72,443,) the mask Eull input signal to gate 21424 is high.
As assumed, the HW CENT signal is high and, if the mask centered condition occurs one window time after the previous transmit operation, the WIND DEL (window delay) signal is also high.
CTR BIT 2 is high for handwritten operations, and RDEN is also high during read enable. At TPE during the -7~ time which immediately follows MUX63; the output signal from gate 21424 is driven low and sets the transmit flip-flop 21426, 21427.
The XMIT signal remains high for a complete vertical scan interval (i.e. 64 MUX counts), turning off at the TPB time immediately following M~X63.
During transmit the handwritten shift gate 21421 is primed. TPA pulses actuate this gate toprovide the hand-written shift pulses when the CLR SHIFT EN signal is high, which occurs: at every second shift time before two-to-one with reuduction; at two out of each three shift intervals for the three-to two width reduction; at four of every five shift intervals for the five-to-four width reduction; and at every interval for the one-to one width reduction. Thus, depending upon the clear shift enable pulse, handwritten shift pulses may occur at one half, two thirds, four fifths, or the same rate as TPA. The clear shift enable (CLR SHIFT EN~ pulses also prime gate ~1413, thws allowing TPB to be passed as the CLR CONT (clear continuous) pulses whenever CLR SHIFT EN is ' ' :
.. .. . . . . - . - .

-~7~
high. As with the handwritten shift pulses, this can occur with every TPB pulse, every second TPB pulse, with two out o every three TPB pulses, with four out of every five TPB pulses.
This CLR CONT signal is fed to the master reset inputs of registers 20529-20532 (Figure 5), which also receive the DE
pulses. Since these DE pulses coincide with TPF and are repetitive throughout the vertlcal shift interval (i.e. MUX
count cycle),for each step of image through the thirty-two column register a black (zero or low), if it is detected, is presented to the set inputs of the respective 1atches in registers 20529-2~532. However, dependlng upon the CLR SHIFT EN, every second, third, fourth, or fifth CLR CO~T pulse may be missing. This has the effect, as stated before, of combining in an OR function the r~quisite ~umber of rows of the image to reduce the vertical size of the image by the required indicated - ratio. The outputs of registers 20529-20532 are inverted by inverters 20533-20547 to provide the inverted channel output signals CHANl - CHAN15 whlch are utilized at the handwritten mask circuitry in Figure 18.
~; The straight line detector, illustrated in Figure 14,utiliæes the output~ signals Wl through W31 of the width :~ :
detector circuItry. All~thirty-two columns mu~t be interrogated during handwritten operation to determine whether or not a stxaight line~xists across the mask. However, if the OCR-A
machine print fonk is being read, ~TR ~I~ 2 is high, producing ~; a low at the output of inverter 21407 which maintaills the output of gate 21408 continuously high, thereby blocking of~

_30 1~317~ZO
the effect of W14 through W31 rom gates 21401-21406. Similarly, ~or 7B font operation, CTR BIT 1 is high and th~ output signal from gate 21405 is maintained high, nullifying the efect of Wl9 to W31. During handwritten operation~ neither CTR BIT 1 nor CTR BIT 2 is high and W14 through W25 are effective, unless 4.3 pitch is selec~ed, in which case CTR BIT 3 goes high and enables W26 through ~31. If all selected lines are high a straight horizontal line is present across the mask. Under such conditions, with Wl through W31 all high simultaneously, the SL (straight line) signal goes low.
The width detecting flip-flops in registers 20301-20308, as previously stated, are cleared shortly after every MUX63 interval by the CLRW pulse. This pulse is produced by gate 21415 J When a transmit function is not in process, gate 21414 lS primed by the ~MIT signal. The delay pulse from gate 21419 lS high from the TPD pulse during the MUX63 : interval until the second TPD pulse after MUX63. Another priming signal for gate 21414 is N/2 whlch occurs dur~ng the second MUX~ahift intervaL after MWX63. Thus g~te 21414 : ~ is enabled by the TPB pulse during the second MUX interval ater MUX63,~to provide~the~C~RW sign~l. During the transmit interval the XMIT signal primes gate 21422 ~o that the CLRW
: ~ :
~ :pulse is generated by gate 21415 at MUX~3G time instead o~
:: ~
at the~second TPB~pulse after MUX63 as in~non~transmit 25~ ccndition~c.
Due tc the~helght:reduction process the verti~cal height (time-wlse) of the reduced image may not correspond preci3ely : :

: : -31-.~

~L~7~G12~
to that of the image in the thirty-two column shift register;
therefore the C~IANl through CHAN15 signals proceed not only to the handwritten mask circuit but also to gates 20501 and 20502 of E`igure 5. These channel outputs are combined in an 5 OR function so that the ACD signal from gate 20501 is high for any shift interval in which any of the channels 1 through 15 are high. The ACD signal is used in the circuit of Figure 35 to keep track of the position of the reduced character image being shifted through the handwritten mask.
Due to the random width and spacing of the handwritten characters it is necessary to compensate the data stream applied to the blacks counter 10702 illustrated in Figure 107 of the aforementioned U.S.Patent 3,872,443.
In other words, for machine print, the characters are uniform 15 and each character can be referenced from the center of the previous ~ounter. For handwritten recognition, it is necessary to reference each character from a point which immediately follows the trailing edge of the previously centered character~ -For the purpose the width bit signals, WBI, WB2 and the SLB
20 signal are stored in register 21301 illustrated in Figure 13.
The WB1, WB2 and SLB signals are entered in register 21301 at the leading edge of the transmit cycle and are held until the leading edge of the following transmit cycle. The output signals from register 21301 are the stored width bit 1 (SWB1), 25 stored width bit 2 (SWB2~, and the stored SLB signals. These are fed as select signals to the dual four-to-one data multi-plexers 20506, 2G5U7 in Figure 5. The data inputs to these ~-"'.

' ':. ' ' , , ~7~Z~
data slector multiplexers come from var.ious points in ~.he shit register columns which correspond to the point slightly after the trailing edge of the dif~erent images for.each of the three width reduction ratios. In other words, either 5 14 or 16 is ~elected or the one-to-one width reduction ratio, depending upon whether the image is twelve to thirteen columns or fourteen to fifteen columns wide. Similarly, for the five-to-four width reduction ratio, 17 or 20 .is selected, and for the three-to-two ratio, 20 or 24 is selected, depending 10 upon whether the image is in the wider or narrower portion of the scale for these reduction ratios. For handwritten 4.3 pitch operation, either 27 or the MUXSDG` signal is selected.
For handwritten 5 pitch, MUXSDG is combined in an OR function with 27 at gate 20504. Since for handwritten 5 pitch no data 15 is present in column 27, the selected MUXSDG or MUXSDG output is fed from multiplexers 20506, 20507 to multiplexer 20527 where, depending upon whether the character is wide or narrow relative to the reduction ratio .in force, the DATA SEL (data select) signal is applied to gate 20232 in Figure 2. When 20 CTR BIT 1 is low ~i.e~ OCR font 7B or handwritten operation is selected) the selected output channel data is fed through gates 20232 and 20233 as the BLKS CTR SD (blacks serial counter --data) signal, which replaces the MUXSD signal applied to the D input to CGUnter 10702 in U.S.Patent 3,872,443.
25 With CT~ BIT 1 high, gate 20232 is disabled and gate 20231 is enabled, passinc3 the MUXSD signal clirectly through gate 20233 as the BLKS CTR SD signal , ' ... . .. . .. . . .

:1 ~7~
Generation of the MUX CLOCK and MOS CLOCK si~nals is effected by the circuitry in Figure 12 in accordance with the same logic descr.ibed in relation to the circuit of Figure 92 of the aforementioned U.S.Patent 3,872,443.

~ ':

1~7~
III. HANDWRITTEN MASK LOGIC
The handwritten mask logic is illustrated in Figures 17 through 26 oE the accompanying drawings. The main functions of the handwritten mask logic are the recognition of certain charac-teristics and features in th~ characters being processed and the proper orientation of the data streams in each channel to optimize recognition of those characteristics and features.
In order to properly orient the da-ta streams, the CHANl through CHAN15 outputs from the handwritten scalar are fed to registers 21809, 21811, 21813 (Fig. 18) where they are delayed for one E~SHIFT pulse and then passed to registers 21810, 21812, 21814 where they are delayed for a second HWSHIFT pùlse. Registers 21809-21814 are parallel in - parallel out shift registers.
Thus the output signals from registers 21810, 21~12, 21814 are designated CHANlD - CHAN15D and are the same as CHANl - CHAN15 but delayed in time by two handwritten shift pulses. The purpose for this delay is discussed subsequently~
The CHANlD - CH~N15D signals are applied to serial in -parallel out 8-bit registers 21701-21710, 21801-21805. These are the shift registers which drive the handwritten mask logic. Since the shift registers are only eight rows high, whereas the image of the character passing through the mask can vary up to twenty-six rows in height, the registers must be time-shared in order to lnterrogate full image height.
In other words, the image in the mask must be interrogated several times during lts progress through the mask. The timing pulses utilized to interrogate the image as it passed through : .

~ -35-`

~7~

the mask are generated in the handwri-tten decoder circuits described subsequently.
The output signals Erom shift registers 21701~21710 and 21801-21805 are designated in -the form CXRY, where X
represents the ver-tical column or channel number and Y represents the horizontal row or register shift position. The different columns and rows define the handwritten mask in the form of a grid or matrix which is fifteen columns wide and nominally eight rows high. Combina-tions of bits from different grid locations are employed to test ~or certain identiEying features in characters being shifted through the mask. Some of these tests, as described subsequently, require three additional bits for columns one through six and ten through fifteen, and for this purpose, parallel in - parallel out shift registers 21711, 21712, 21807, 21808, 21815 and 21816 are provided. In addition, parallel in - parallel out shift register 21806 is provided to extend columns seven and nine by one bit. Thus, mask column one includes the elght bits ClR0 through ClR7 provided by shift register 21701, and bits ClR00, ClR01 and ClR02 provided ~ by registers 21711, 21712 and 21815, respectively. Columns seven and nine on the other hand include the eight bits C7R0 and C9R0 thro~gh C7R7 and C9R7 provided by registers 21707 and 21709, plus .
bits C7R00 and C9R00 provided by register 21806. The character features tested for by the mask logic are as follo~s~
~aj horizontal line (HL);
(b3 line crossing in upper left portion of character (MlT41;

` .7= ' _~

f~7~

~c) line crosslng in upper xigh-t portion oE character (M5Tl), (d) line crossing in lower left portion of character (MST2); and (e) line crossing in lower right portion of character (M2Tl).
In addition, a detected horizontal line is tested as to whether it is located at the top middle or lower portion of the character.
Briefly, -the mask is able to make use of only eight (or in some cases eleven) rows of data to recognize features in characters which are nineteen to twenty-six bits high in the following manner. When the top o~ a character reaches the upper portion o~ the eight bit high mask, the character is checked for a lS top line. Four shift counts later (after the character has shifted four positions higher in the mask) a test is made for the presence of lines at the top right and top left sides of the mask. Two more shift pulses later a search is made for a mid portion line, which search continues until the line is found or the bottom of the character reaches the bottom of the eigh-t bit high maskO When the bottom of the character reahes the bottom of the mask, the search for a bottom line is initiated and the bottom left and bottom right line ~ tests are perEormed.
The circuitry for detecting the presence of a horizontal line in th~ mask is illustrated in Figu~es 24~ 25, and 26. The criterion for a horizontal line is as Eollows:

:~ :
` -37-~7~
If an image occ~lrs in any one or more of Eour rows across a span of eight adjacellt coLurnns, a horizontal line is deemed present. Four rows are examined to permit a sloping or curved line to be detected as a horizontal line. The inpu-t pulse trains(i.e. CHANlV through C~AN15L)~ to the eight stage mask shift registers, along wi-th the signals from rows five, six and seven of those registers, are monitored by gates 22401-22415. For example, if either the CHANlD, ClR7, ClR6 or ClR5 signals are zero, gate 22401 provides the ClOR signal in its binary 1 state. Thus, anytime a black occurs in any one of the first four rows of the shift register of any channel, the output of the respective gate 22401-22415 for that channel goes high. The output signals from these gates are combined eight at a time at NA~D gates 22416-22420 and 22501-22503. In other words, ClOR through C80R are combined at gate 22416 to provide a binary O LTl signal if all eight input signals are high, signifying that an image is present somewhere in the top four rows of each of columns (channels) one through elght. Likewise, gate 22417 provides a binary O
LT2 signal if an image is present somewhere in the top four rows of each of channels two through nine, etc., so that all combinatlons of eight adjacent columns are examined by a respective gate. If any of the LT (line test) signals go low n other words, an image appears in one or more of the top fo~r rows of eight adjacent columns~, the HL signal provided by negative OR gat~ 22504 is dxiven high~ Signal HL, ndicatlng that a horizontal line has been detected, is fed ,: ~
: :

`:

z~
to shift register 22603. Since the first detected ho.rizontal line in a character is not necessarily located at the top of that character, shift register 22603 serves to locate the detected line relative to the character. Specifically, the state of HL is shifted to ~our successive shift register bits during four successive HWSHIE'T pulsesO If HL is high, gate 22604 provides a high output signal to gate 22601 dur.ing each of t.hese four shift intervals. Gate 22601 also receives timing pulse TPl which, as described subsequently in relation to Figure 37, is binary 1 when the top portion of the character is passing through the top portion of the mask. Thus, i~
gate 22604 provides a binary 1 signal in time coincidence with TPl, the detected horizontal line is a top line and the TOP LINE
signal from gate 22601 goes low. Similarly, gate 22605 is connected to shlft register 22603 50 that a horizontal line detected within two rows of the bottom of the character cause .
the BOTT LI~E signal from gate 22606 to go low. That ist timing pulse TP4 is synchronized to be binary 1 when the bottom o~ the character reaches the bottom of the handwritten mask;
consequently, gate 2260~6 is actuated at TP4 if a bottom line is ; ~ detected in the character being shifted through the mask.
Timing~pulse T2D becomes binary 1 six shift counts after the top of the character enters the top of the mask.
An additional shift delay is incorporated at ~lip-flop 22610, 2~ ~the set output signal from which is thereoxe driven hl~h ; at a time seven shlft pulses after TPlo At TPl time the top of the character was at the top output pin of shift 7~V

register 22603: therefore,by the -time flip-flop 22610 is set, the top of the character should have been shifted out of the mask by seven rows. In other words, the search for a mid-line begins seven rows below the top oE the character. Since the bottom o~ the character (at TP4) o~curs a-t the same time that HL would be provided at the output of inverter 22602, the fact that the mid-line pick-up point is seven shift counts prior to the bottom of the character means that the search for the mid-, line is terminated seven shift counts before the bottom of the image reaches the interrogation location at the lowest two output terminals of shift register 22603. In other words, the search for a horizontal line at the mid-portion of the character occurs from a point seven rows below the top of the image to a point seven rows above the bottom of the image. I~ a mid-line occurs during T2D time, as delayed by flip-flop 22610, gates 22613, 22614, connected as a cross-coupled latch, are ::
set~, producing a low MID-LINE signa~.
Latch 22613, 22614 is reset by the ERASE signal : :
which lS generated by flip-flop 22612. Normally, with XMI~
low, the J input o flip flop 22612 is high and the K input is low. With MUX63G used as a clock signal for the flip-flop, the set outpu~ is normaIly high; however~ when XMIT goes high (after~MUX63G of the vertical scan period)~ the set output of 1ip-flop 226~12 goes~low and~stays low until the following 2~ ; MUX63G pulse. After the read enable interval, the~subsequent DLRST slgnal insures``that flip-flop 22612 is~reset.

.: : :

`~::: : :
: :
~:~

~7~C~2~
The test for a character having a line crossing in its upper left hand portion is designated herein as test MlT4~
Logic circuitry for this test is illustrated in Figures 19 and 20, diagrammatic or graphical representations of the MlT4 test and its various sub-tests are illustrated in Figures 39 through 48. Sub-tests comprising MlT4 are performed during timing pulse TP3 which occurs four handwritten ~hift pulses after the top of a character is supposed to have been shifted to the top of the mask~ To this end, TP3 is applied to ~AND
gate 21906.
There are nine sub-tests in the MlT4 test, each performed at a different one of inverted OR gates 21901-21905 and 22001-22004. Each sub-test examines a different series of adjacent grid locations in the mask to determine if'a black bit is present in any one or more of those locations. If at least one black bit is detected in all nine sub-tests, the ; logic determines that an upper left line cro5sing existsc : : More particularly, sub-test one of the MlT4 test : : :
;~ ~ is performed at gate 2190I. As illustrated, this gate looks at the following locations in the mask. Column 9ix, row one;
column five, row two; column six, row two; column five, row three~; column three, row four; column four, row four; column ive,~row~four; column:one, row;five; column two, row five;
and~ column three~:~ row ~ive. This suh-test is illustrated 5~ graphlcally ln F'gu~re 40~wherein the mask locations coxres-ponding to those viewed`~or MlT4 sub-test one are shaded.
The overall grid~contains fifteen vertical columns (corresponding) . .
.
,, ' .

~ Ot7~

to the fif~een channels) and anywhere from nineteen to twenty-six horizontal rows (corresponding to the height of each character), these rows being numbered along the left hand side o~ the grid. The mask, as mentioned above, is only eight (or in some cases, eleven~ rows high so that it must in effect be translated up and down relative to the twenty-~our element character grid. This translation is effected by the timing pulses associated with the various mask tests. Specifically, since gate 21906 can be activated to show a positive test result only during timing pulse TP3, and since TP3 occurs a specified time after the top of the character passes through the top of the mask, the mask rows are effectively re-positioned by TP3 relative to the twenty-four element high character in the manner 1llustrated in Figure 39. As a consequence, the mask rows Rl through R5 which are used in MlT4 sub-test one are positioned in correspondence w1th grid rows six through - ten; respectively.
In a similar manner, the MlT4 sub-tests two through nine are performed at gates 21902 through 21904, 22001 through 22004, and 21905, respectively, and are graphically depicted ; ~ in F1gures 41 through 48 respectively. A compos1te of all ;~ nine MlT4 sub-tests is graphically illustrated in Figure 39 for ease of reference.
If all nine MlT4 sub-tests are positive during the ~25 ~ TP3 interval, all ten input signals to N~N~ gate 21906 are :
at logic one and the MlT4 output signal from that gate becomes logic æero. This indicates that a line crossing exists in the upper left portion of the character being processed. The MlT4 signal is utilized in the handwritten decoder circuitry of Figure 27 in a manner described subsequently.
In a similar manner test MSTl examines the character being processed for a line crossing in the upper right hand portion o the character. The logic circuitry for test M5Tl is illustrated in Figure 22 of the accompanying drawings.
Test M5Tl is subdivided into five sub-tests one through five, performed by respective inverted OR gates 22201, 22202, 22204, 22205 and 22206. The sub-tests are illustrated graphically in Figures 50 through 54 respectively, with a composite graphical representation ~f test M5Tl being presented in Figure 49.
The output signals from each of gates 22201, 2~202, 22204, 22205 and 22206 are applied to NAND gate 22207 along with timing pulse TP3. The M5Tl test is thus performed during the TP3 interval at the same time as test MlT4 described above.
, If the results of all M5Tl sub-tests are positive during the ; TP3 interval, the M5Tl output signal from gate 22207 becomes logic zero to indicate that a line crossing exists in the upper right hand portion of the character being processedO
.
The M5Tl signal is utilized in the handwritten decoder circuitry of Figure 27 as described subsequently.
The test ~or a line crossing in the lower left hand portion of the character is desiynated M5T2. The logic -; :
circuitry for this test is illustrated in Figure 23, and the various sub-tests for M5T2 are illustrated in Figures 56 ~, .

~7~
through 59 . The our sub tests performed for tes t M5T2 are effected at gate~ 22301, 22302, 22304 and 223050 respectively.
If the re~ults of all four sub-te~ts ~re po~itive during the interval of timing pulse TP4, the output ~ignal M5T2 from NAND gate 22306 is rendered binary. zero to indicate that a line crossing exists in khe ~ower left hand corner oiE the character being procesa~d~ Xt should b~ noted in Fi~ures 56 through 59 that the mask rows R02, R01, R00, R0, ancl ~1 are transposed ~in this case by timing pulse q~P4) to row~l thirteen through seventee~, respectively, on the t:wenty-:Eour row character matrix. The difference in mask row locations on the matrix, relative to those locations ~or tests M5Tl and MlT4, illu~trates the time sharing f~ature of the ma~k. A
composite representation of all four M5T2 ~ub-te~ts is illu~tra ed in Figure 55.
The te~t for ~etermining whe~her a line cro~sing exists in the lower right hand portion of a character being .
p~ocessed is designated M2Tl, The logic-circuitry or J performing test~ M~Tl i~ ustrated in Figure 21 of the `I 20 accompanying drawingQ . Graphical repres~ntation of the s ix :~ sub~ te~ts which comprlse M2Tl are presented in Figure~ 61 }
through 66; a composite of these six ~ub-te~ts i~ graphically rapresented in Figure 60. If at least~one grid location tested by eaoh o gates 22101-22106 is black during timing .l -puïse TP~ il) gate 22107 provides the M2Tl Signall ill itS

blnary ro state. This indicates that the charact~r being processed has a line crosqing in its lower right hand portion~

-~4 ~,..

~L~7~

-The M2Tl signal is processed in the circuitry oE Fiyures 28, 30 and 32 of the handwri_ten decoder.
Indications of the results of all seven mask tests (top line, mid line, bo-ttom line, MlT4, M5Tl, M5T2, and M2Tl) are transmitted to the handwritten decoder circuitry.

: ' ~ ' :

~ ' ~ ~ , :

, . .

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IV. HANDWRITTEN DECODER
The handwritten decoder logic is illus-trated in Figures 27 through 38. As was mentioned during the discussion of the handwritten mask logic, the -top line test occurs during timing pulse TPl, whereas the top left and top right tests (MlT4 and M5Tl) occur at TP3 time. Since these times are considerably in advance of TP4 time when the remainder of the tests are conducted, the results of the early tests must be stored until all test results have been accumulated. Register 22703 in Figure 27 is utilized for this function. OR gate 22702 is enabled at TPl and TP3 times and, along with a coincident HWSHIFT pulse, enables NAND gate 22701. Gate 22701 thus pulses the enter input terminal of register 22703 once during TPl and once during TP3. This permits the result of the top line test to be stored in register 22703 at TPl and the result of the top right ~M5Tl) and top left (MlT4~ tests to be stored therein at TP3 time~ These results are stored until the ERASE signal goes low at the end of the transmit period. The mid line test has its own latch ~22613, 22614), as discussed prevlously. The thusly stored top line test result signal is designated SMlTl, the stored MlT4 ~top left) result signal is designated SMlT4, and the mid line test result signal ~is designated SMlT2. The SMlTl, SMlT4, SMlT2 and~BOTT~hINE slgnals;are ~applied to a four line-to-sixteen -~ 2~5 ~ ~ line decoder 22802 in~;Figure 28. The sixteen output lines of thls decoder are labeled~O~O through OC15 (or outcome O
~ through~outcome 15). The Fignificance of these outcome Q

:: ~ :
~ E~ R~`i 1~7~V
signals is indicated in the followin~ truth table for which logic is embodied in the circuits of Figures 28, 29 and 30:
SMlTl SMlT2 SMlT4RECOGNIZED
OC~ (TOP) _(MID~BOTT (TCIP LF.FT) CHARACThR

2 0 0 1 0 ?

3 0 0 1 1 ?

4 0 1 0 0 4 7 0 1 1 1M~SK S

9 1 0 0 1 ?

A question mark in the right hand column of the foregoing truth table indicates that a character has not been recognized.
It is noted from the truth table that two conditions ~produce a mask 2 character; these are when there is no upper 25~ left line crossing and either a top and bottom line (OC10) or top, bottom and mid line (OC14) are present. Under these conditions if a lower right line crossing is present, as determined at yate 23004, the result is called a character three. If, however, a lower right line crossing is not present, 3~0 ~ ~as determlned at gate 23002, tlle character ` lS called a two~
Mask 2 decoding is performed by gates 23003, 23002 and 23004 llustrated ln Figure~3. Signals OC10 and OC14 are combined n invertlng O~ga~te 2300~3, which produces~a h~igh output s~ignal if either input signal is low. If M2Tl is high at ~7-, ~::: :
, 3~ J
':

~7~
this time -the 3 signal Erom gate 230Q4 goes Low, indicating that the character 3 is recognized. If M2Tl is high, the 2 signal from ga-te 23002 goes low indicating that the character 2 is recognized.
The mask 5 character is considered if there is a mid-line, bottom line, and upper le~t crossing, whether or not there is a top line (OC7, OC15). The truth table for the mask 5 character is as follows:
Tl T2CHARACTER
__ o 0 5 Mask 5 is decoded by gates 22805 through 22814 in Figure 28.
This decoder is primed by the M5EN signal appearing at one input of gates 22806, 22808, 22811 and 22813. A high M5EN
signal is provided by gate 23008 (Fis. 30) when either OC7 or OC15 is low. If SM5Tl (upper right) and M5T2 (lower left~ are both high (i.e. no upper right or lower left line crossing), gate 22805 is enabled. Since gate 22806 has been primed by the M5EN signal, this gate provides a low 5 signal, indicating that the character 5 has been recognized. If SM5Tl is high and M5T2 is high (i.e. upper right line crossing but no lower left line crossing)igate 22807 is enabled and in turn enables gate 22808. `The latter provides a low output signal which n turn provldes a low 9 signal from ga~te 22809 to indicate that the character 9 has been recognized~ Since OC13 also .
~: :
i indicates recognition o~ character 9, OC13 is also employed : : :
.! ~ ' :

:
~ ~48-.

7~

to enable gate 22809 to provide the low 9 signal.
If both SM5Tl and M5T2 are high, gate 22810 provides a high output signal which in turn enabLes the primed NAND
gate 22811 to generate a low 8 signal. This indicates recognition of the character 8. If SM5rrl is high and M5T2 is high, gate 22812 is enabled and in turn enables primed NAND gate 22813. The latter enables gate 22814 to provide a low 6 signal. Since OC6 also indicates recognition of character 6, OC6 is also employed to enable gate 228l4.
The truth table for the OC signals indicates that OCO or OCl corresponds to recognition of character 1. The OCO and OCl signals are combined in inv~rting OR gate 22902.
The high output signal from gate 22902 primes NAND gate 22905.
If the ones centered condition has not occurred, both inputs to gate 22905 are high and a low 1 (WIDE) signal is produced.
This signal actuates gate 22906 to provide a low 1 signal, indicating recognition of character 1. `If, however~ a processed character is suf~icient]y narrow to operate the ones centered detector (as discussed in relation to the handwritten scalar, Fig. 15) the l'CENT signal goes high. With the XMIT signal also high, the flip-flop comprising gates 22903, 22904 is set, producing a low INH4 signal. This signal is applied to gate 22906 to provide the low 1 signal, indicating recognition of character 1~
~ The INH4 s~gnal is also employed at gate 23005 to inhibit spurious recognition of character 4. Spec1fically, if OC4 or OC5 is lowi gate 23006 provides a high output signal.

i :
. , _49_ .: - . ~ - ~ . , -,: . . , ,:

~(~7~
When INH~ is high, th~ 4 si~nal is rendered low at gate 23005.
If INII4 is low, however, a character sufficiently narrow to be considered a one has been centered and gate 23005 is inhibited from pro~Jiding a low 4 signal.~
The character 7 is recognized at gate 23007 if OC8 or OC12 is low.
In addition to recognizing the ten numerals, the system as disclosed is also capable of recognizing the Letter C~
Lettær C is recognized by gates 23211, 23212 if OCll is low and both SM5Tl (upper right) and M2Tl (lower right) are low, indicating the absence of a line crossing on the right hand side of the character. For this condition gate 23211 provides a low input signal to combine with the Low 0 signal at gate 23212 to provide a low C signal from the latter gate. This indicates recognition of the let~er C.
~he encoding of the characters into a four bit code is performed in the circuitry of Figure 31. Data converter 23102 converts the characters 0 through 7 into a three bit code. Since the character codes for 6 and C have the same first three bits, the 6 and C signals are combined in an 9R
function at gaté 23213 and then fed to data convert~r 23102 as common signal 6 - C.~ Signals 8 and 9 are combined in an OR function with signal C to provide the fourth bit of the character code~ Since the code for character 9 also requires bit 1 to ~e high, the 9 si~nal is combined in an OR function , with the blt l output of converter 231020 The our code bits are then applied in positive-true ormat, to registar `~ : :
b~
,~
~ 50~
,~ .

- . .
.~ , ....

23106 where they are stored at hand print recogniæed time (i.e. when the HPREC signal goes high) for use in the data con~rol circuitry (Fig.-l9 of the aforementionecl U.S.Patent 3,872,443~
In addition to the particular tests required to identify the characters, tests are conducted to assure that an errolleous character substitution does not occur. For example, iE the zero character code is to be transmitted to the data control circuits, M2Tl and SM5Tl must both be high;
10 that is, there must be both upper and lower right line crossings in the character to be transmitted. If both M2Tl and SM5Tl are low, the character is a C. If only one of these is high and the other is low, exclusive OR gate 23001 provides a low HRS output signal. This low is passed through gate 15 23202 and combined in a negative AND function with O at gate 23201 to provide the ERROR O signal.
If a wide 1 is detected and M2Tl is low at gate 23204 (i.e. a lower right line crossing exists), a low ERROR 1 signal is pro~ided by gate 23205. If a 2 is detected when M5T2 is low ~0 (i.e. the character image does not intersect the lower left portion of the mask~, an ERROR 2 signal is generated. If a 3 ls de~ected and there is either a lower left intersection, or absence of an upper right intersection, or absence of a mid-line, an ~RROR 3 signal is generated. If a 4 is detected 25 and the upper left is missed, a low ERROR 4 signal is generated. If a 5 is detected and a top line is missed, a low ERROR 5 sign~l is generated. If a 6 is detected and a .
:, :
, , ,~ ' - .: : - . -~L~7~
and a lower right in-tersection is missed, or the lower le~t intersection is missed, or a top line is detected, a low -ERROR 6 signal is generated. If a 7 is detected and a mid-line is also detected~ a low ~RROR 7 signal is generated. If an 8 is de-tected and a top line or lower right intersection is not identified, a low ERROR 8 signal is generated. If a 9 is detected and an upper right intersection is missed~ ox a bottom line is detected, or a top line is missed, a low ERROR 9 signal is generated.
All of the ERROR signals are combined in a negative OR function at gates 23401, 23402 to produce a positive going signal which is inverted by inverter 23403 to provide a negative ERROR signal. This signal is applied to inverting OR gate 23404 along with the OC9 and SPER signals. The SPER signal is provided by the circuit of Figure 35 wherein OC2 and OC3 are combined at inverting OR gate 23510 and passed as a low SPER signal by gate 23513 if CTR BIT 1 is low. If .
any of the OC2, OC3 or OC9 signals are low there has been no character recognition, as indicated in the OC truth ~able above.
Henc these signals are combined with the ERROR signal provided by inverter 23403.
If no ~RROR signal is generated, the HPREC (hand print recognlze) is permitted to go low, assuminy that the CS/~ signal remains high ~i~e. character~is not too short nor too long)~
:
Specifieally, gate 23405 primes one input to gate 23406 at TPF time. At TP4 tim~ during the T2 interval gate ?3405 is therefore enabled to provide the low ~IPREC signal and cause ~ , 7~
inverter 23407 to provide the high ~IPREC signal. If any error is detected, gate 23406 is inhibited, inhibitiny the inc]ication of any recognition of a handwritten character, and causing the HPER (hand print error) signal to go low).
The remaininy circuitry ln the handwri-tten decoder is used -to generate timing signals required to lceep track of the progress of the character image through the mask. The ACD
signal, as described in relation to Fiyure 5, represents the vertical projection of the combined image of all fift~een channels proceeding through the mask. This ACD signal is fed to the data input terminal of flip-flop 23503 (Fig. 35).
Assuming the system to be in the transmit mode, the ERASE
signal is high and inhibits TPA pulses from passing through gates 23501 and 23502 to clock the flip-flop 23503. However the output of gate 23501 is combined in a negative OR function with the HWSHIFT pulses at gate 23503, so that the handwritten shift pulses serve to clock flip-flops 23503, 23504 and the 8-bit shift register 23505. Thus, at the first shift pulse after ACD goes high, the Q output signal of flip-flop 23503 goes high. The trailing edge of the following shift pulse causes flip-flop 23504 to be likewise set, and this high is passed progressively through shift register 23505 as long as the handwritten shift pulses occur and as long as ACD is high.
Normally, ACD goes low before the handwritten shift pulses are stoppedO In such case, the Q output signal of flip-flop 23503 goes low at the first handwritten shift pulse after ACD
goes low. One shift pulse af-ter that the Q output signal of ~L~7~13if,Z(~

flip-flop 23504 goes low and this low is passed progressively throu~h shift register 23505 as the vertlcal projection oE
the handwritten character image. When the top of the character image has reached the top of the handwritten mask, the shifted ACD signal is low at the top output terminal of shift register 23505 but hi~h a-t the second from top output terminal. If there is enough of the image such that the second throuyh fifth terminals from the top are high, the STPl output signal from gate 23507 goes low. Importantly, in order for STPl to go low, the system must be in T0 time. T0 remains high until a received character image, of sufficient height to keep the second through fifth output terminals from the top of shift register 23507 high, has risen up through the shift register to enable gate 23507 and drive STPl low.
The low STPl signal is fed to OR gate 23601. The following ~SHIFY' pulse causes the output of 23507 (STPl) to go hlgh (since the output of 23506 goes low). STPl going high advances FF23602 from the count o~ O to the count of 1. Since flip-flops 23602, 23603 are no longer both reset, gate 23606 is inhibited and the T0 signal becomes logic 0. This disables gate 23507 and the STPl signal remalns high. The count of one at flip-flops 23602,23603 enables gate 23605 to provide the Tl timing signal.
When Tl is high the counter comprising flip-flops 23701, 23702, 2~3704 (Fig. 37) starts countiny HWSHIFT pulses~ From the time ~ Tl goes high until thé end of the first HWSHIFT pulse, TPl ; is low, because all Input signals to NAND gate 23707 are high during this intervaI. Following the first shift pulse, however, the Q output signal from flip-flop 23701 goes low, ~ `

1~7~

turning off the TPl signal at gate 23707. TP2 goes hiyh when the count oE three is reached (i.e. at the third ~ shiEt pulse) and STP3 goes low when coun-t five is reached. STP3, in addition to being the signal which is inverted by inverter 23804 (Fig.
38) to provide TP3, is also fed to gate 23607 where it advances the count in flip~flop 23602, 23603 to two. This drives T1 low at gate 23605 and T2 high at gate 23604. With Tl low, further counting by the counter of Figure 38 is inhibited.
When in timing interval T2, the system waits for the bottom of the character to enter the mask. When the bottom of the character reaches the lower most input terminal of shift register 23505, the STP4 signal from gate 23508 goes low.
This signal is inverted by inverter 23509 to provide the TP4 signal which interrogates the handwritten mask for the conditions to be determined at the lower portion of the character. The STP4 signal also advances the count at flip-flops 23602, 23603 from count two to count three in which condition both counters (Fig. 35, Fig. 36) await the end of transmission before being reset to zero.
Flip-flops 23805, 23806 in Figure 38 are utilized to delay the T2 signal by two shift pulses to provide the T2D siynal~
T2D is used~at the mid line detector so that the search for a mid-line begins no sooner than seven rows below the top of the character. The clock for flip-flops 23805, 23806 is the hand~
2~ written shift pulse train. The two flip-flops are operated as a shift register so that the first handwritten shift pulse after T2 sets flip-flop 23805, and the second shift pulse ' ~0713~

after T2 sets flip-flop 23806~ When T2 goes Low both flip-flops are reset immediately.
V. CONCLUSION
In order to facilitate understanding of the handwritten character recognition process there is provided in Figure 70 a graphical representation of the 15 colurnn x 24 row normalized character matrix in which the positions of the composite of six of the seven major tests are shown by cross-hatched lines.
The mid-line test region is illustrated to the left of the matrix. Overlaying the matrix and the tests is an idealized handwritten character "3"~
The position of the 8 or 11 row handwritten mask at each of times TPl, TP3 and TP4 is illustrated to the right of the matrlx. Speciflcally, at TPl the mask rows R0 through R7 correspond to matrix row O through 7. At TP2 the mask rows R0 through R7 correspond to matrix rows R5 through R12. At TP4 time the mask rows R02 through R7 correspond to matrix rows 13 through 23.
The character "3" extends continuously across at least eight columns in the top-line test region MlTl so that a top line is detected for this character. The same holds true for both the mid-line and bottom llne tests since there are elght continuous~columns contained present in each of these~test reglons.~ All~of the top right and bottom right sub-tests are cros6ed so that crossings ar~ detectled in theise regions. The upper left region is touched by the "3" in two ~: :
places~ but this test reglon lS not crossed therefore ::
~ : ~
; : ~ :
: :
-56- ~
. ~-~7~

no upper left crossing is detected. Likewise no lower left crosslng is detected.
From the foregoing description it should now be apparent that the present invention provides a method and S apparatus for sensing handwritten characters to provide input signals for a data processing machine.
The method taught herein is the essence of simplicity and yet allows a considerable variation in character size and shape.
~he description herein has been particularly directed to the sensing and ~ranslation of decimal digits. However, it will be apparent to those skilled in the art that the technique is applicable as well to the translation of letters, or any other symbol which may be written or printed within predetermined guide line sets.
A particular arrangement for translating the sensed signals has been shown. It will be recognized, however, that the variations which are possible are almost ininite in ~erms of the type of character configurations involved as well as the particular rules which are specified as to how the various characters must fall within sub-tests.
While we have described and illustrated specific embodiments of our invention, it will be clear that variations of the details of construction which are specifically illustrated ~5 and described may be resorted to without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
   OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
   
   l. An optical character recognition machine comprising:
   quantizing means for temporarily storing binary signals in a form to physically represent a received character examined by said machine, each binary signal designating the presence or absence of a character portion in a respective physical location;
   scaling means including means for monitoring the size of the represented character, and means for deleting certain stored binary signals in accordance with a predetermined pattern to reduce the size of the represented character to a normalized size;
   means for testing the binary signals comprising the normalized character for the presence of predetermined character features, and means for decoding the results of testing said binary signals to identify said represented character;
   wherein said quantizing means represents said received character in a matrix of binary signals at grid locations comprising m columns and n rows wherein said m columns are arranged along the height dimension of the represented character and said n rows are arranged along the width dimension of the represented character, and wherein said means for testing comprises:
   mask means including m shift registers of less than n stages each;
   means for shifting said represented character through said mask means, parallel by column and serially by row only, each column being shifted through a respective mask shift register; and .
   
   means for monitoring the shifted character for specific features at predetermined mask locations during each of a plurality of character positions in said mask means.
2. 2. The machine according to claim 1 wherein said means for monitoring comprises:
   first logic circuit means operable at one position of each character shifted through said mask means for detecting binary signals at predetermined mask locations to determine if the character shifted through said mask means includes a top line extending widthwise; and second logic circuit means operable at a specified position of each character shifted through said mask means for detecting binary signals at mask locations to determine if the character shifted through said mask means includes portions of at least a specified minimum height in the upper left and upper right areas of the character.
3. 3. The machine according to claim 2 wherein said means for monitoring further includes:
   third logic circuit means operable at a further position of each character shifted through said mask means for detecting binary signals at predetermined mask locations to determine if the character shifted through said mask means includes a bottom line extending widthwise and portions of at least specified minimum heights in the lower left and lower right areas of the character.
4. 4. A character recognition machine of the type in which characters to be recognized are converted into quantized characters made up of binary signals such that each binary signal represents a grid location in a two-dimensional matrix and wherein the level of each binary signal designates the presence or absence of a projected character portion at the grid location represented by that binary signal, said machine including apparatus for recognizing handwritten characters comprising:
   means for positioning the quantized character at a reference location within said matrix;
   scaler means for normalizing the quantized character to a standard size, said scaler means including means for combining the binary signals at predetermined grid locations in accordance with the size of said quantized character;
   means for translating the normalized character through a mask of shift registers, said means for translating including means for shifting the binary levels at said matrix grid locations through said mask only in parallel along one matrix dimension and only serially along the other matrix dimension;
   logic circuit means for monitoring plural combinations of prescribed mask locations, for at least one position of said normalized character as it is translated through said mask, to detect predetermined character features at said prescribed mask locations; and processing means responsive to detected character features by said logic circuit means for determining the identity of each normalized character.
5. 5. The apparatus according to claim 4 wherein said matrix includes n grid locations in its first dimension and m grid locations in its second dimension, wherein said mask is defined by n shift registers having m - x stages each, where x is a positive integer less than m, and wherein said logic circuit means includes a plurality of logic gates operatively connected to a plurality of locations in said mask for each of plural different positions of said normalized character in said mask.
6. 6. The apparatus according to claim 5 wherein said first matrix dimension corresponds to width and said second matrix dimension corresponds to height, wherefore said means for translating shifts said normalized character heightwise through said mask, said logic circuit means further comprising:
   a plurality of logic gates operative for one position of said normalized character in said mask to sense the binary levels at predetermined mask locations for a character line extending widthwise; and a further plurality of logic gates operative for another position of said normalized character in said mask to sense the binary levels at predetermined mask locations on each side of said mask for character lines of a minimum predetermined height.
7. 7. An optical character recognition machine of the type wherein a document is transported along a transport path containing a read station, wherein an optical scanner is actuable to scan transversely of the transport direction across a line of said document located at said read station, wherein a photo-sensitive detector receives images of hand-written characters viewed by said optical scanner and converts said images into electronic signals, said photo-sensitive detector comprising an array of photo-sensitive elements arranged in a straight line to receive vertical slice images of characters viewed by said optical scanner, wherein recognition circuitry processes said signals for the purpose of identifying handwritten characters viewed by said optical scanner, wherein said system includes means operative at regular intervals for quantizing slice images received at said array into respective binary signals indicating the reception and non-reception of handwritten character images at the individual array elements, and a plurality of shift registers, operative between quantizing intervals, for serially shifting said binary signals through all of said shift registers in turn to accumulate a received character in the form of vertical columns and horizontal rows of binary signals, said system being characterized by means for reducing the size of the accumulated character to a normalized size suitable for processing, said recognition circuitry comprising:
   means for counting the number of columns and rows occupied by a received character;
   
   means for determining the number of columns and rows by which the size of said received character exceeds said normalized size;
   means for combining predetermined pairs of columns and predetermined pairs of rows to achieve said normalized size, each combined pair of columns resulting in a single column in which each row location represents the presence of a character portion only if such row location in either of the combined columns contains a character portion, each combined pair of rows resulting in a single row in which each column location represents the presence of a character portion only if such column location in either of the combined rows contains a character portion; and means for shifting said character through a mask means, parallel by column and serially by row only, where each column is shifted through a respective mask shift register.
8. 8. A method of recognizing handwritten characters in a character recognition machine of the type in which characters to be recognized are converted into quantized characters made up of binary signals such that each binary signal represents a grid location in a two dimensional matrix and wherein the level of each binary signal designates the presence or absence of a projected character portion at the grid location represented by that binary signal, said method of recognizing handwritten characters comprising the steps of:
   positioning the quantized character at a reference location within said matrix;
   normalizing the quantized character to a standard size by combining the binary signals at pre-determined grid locations in accordance with the size of said quantized character;
   translating the normalized character through a mask of shift registers, said translating being effected by shifting the binary levels at said matrix grid location through said mask only in parallel along one entire matrix dimension and only serially along the other matrix dimension;
   monitoring plural combinations of prescribed mask locations, for at least one position of said normalized character as it is translated through said mask, to detect predetermined character features at said prescribed mask locations: and processing detected character features from each normalized character to determine the identity of that character.
9. 9. The method according to claim wherein said matrix includes n grid locations in its first dimen-sion and m grid locations in its second dimension, wherein said mask is defined by n shift registers having m - x stages each, where x is a positive integer less than m, and wherein said step of monitoring includes monitoring a plurality of combinations of mask locations for each of plural different positions of said normalized character in said mask.
10. 10. The method according to claim 8 wherein said first matrix dimension corresponds to width and said second matrix dimension corresponds to height, wherefore said normalized character is shifted heightwise through said mask during said step of translating, said step of monitoring further comprising: , at one position of said normalized character in said mask, testing the binary signals at predetermined mask locations for a character line extending widthwise; and at another position of said normalized character in said mask, testing the binary signals at predetermined mask locations on each side of said mask for character lines of a minimum predetermined height.
11. 11. The method according to claim 8 wherein said first matrix dimension corresponds to width and said second matrix dimension corresponds to height, wherefore said normalized character is shifted heightwise through said mask during said step of translating, and wherein said step of monitoring includes:
    testing binary signals in said mask for a widthwise-extending top line in said normalized character at one character position in said mask;
    testing the binary signals in said mask for lines of a minimum predetermined height in the upper left and upper right portions in said normalized character at a second character position in said mask;
    testing the binary signals in said mask for a widthwise-extending line proximate the heightwise center of said normalized character at a third character position in said mask; and testing the binary signals in said mask for a widthwise-extending bottom line and for lines of minimum predetermined height in the lower left and lower right portions in said normalized character at a fourth character position in said mask.
12. 12. The method according to claim, wherein said step of monitoring includes the steps of:
    testing the binary signals comprising the normalized character in said mask for the presence of a widthwise-extending line at the top of the normalized character;
    testing the binary signals comprising the normalized character in said mask for the presence of a widthwise-extending line at the mid-portion of the normalized character; and testing the binary signals comprising the normalized character in said mask for the presence of a widthwise-extending line at the bottom of the reduced character.
13. 13. The method according to claim 11 wherein the step of monitoring further includes the step of testing the binary signals in said normalized character for the presence of character lines crossing the upper left, upper right, lower left and lower right portions, respectively, of the character.
14. 14. The method according to claim wherein said binary signals are successively shifted through serially-connected shift registers arranged to define columns and rows of said matrix, wherein each serially-connected shift register constitutes a column and corres-ponding stages in each shift register constitute said rows, wherein the normalized width of a character constitutes a predetermined number of columns, and wherein the step of normalizing comprises the step of reducing the number of columns in the represented received character as necessary to provide a character having only said pre-determined number of columns.
15. 15. The method according to claim 14 wherein said step of reducing comprises the step of combining specified pairs of adjacent columns on a row by row basis such that each combined pair of columns results in one new column containing binary signals representing character portions at each row location at which a character portion is present in either of the combined pair of columns, the specified pairs of adjacent columns being determined in accordance with the number of columns present in the quantized character before.