BRPI0920782A2 - técnica para promover a fusão eficientes de instruções - Google Patents
técnica para promover a fusão eficientes de instruçõesInfo
- Publication number
- BRPI0920782A2 BRPI0920782A2 BRPI0920782A BRPI0920782A BRPI0920782A2 BR PI0920782 A2 BRPI0920782 A2 BR PI0920782A2 BR PI0920782 A BRPI0920782 A BR PI0920782A BR PI0920782 A BRPI0920782 A BR PI0920782A BR PI0920782 A2 BRPI0920782 A2 BR PI0920782A2
- Authority
- BR
- Brazil
- Prior art keywords
- instructions
- technique
- promoting efficient
- efficient fusion
- fusion
- Prior art date
Links
- 230000004927 fusion Effects 0.000 title 1
- 230000001737 promoting effect Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/452—Instruction code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/290,395 US9690591B2 (en) | 2008-10-30 | 2008-10-30 | System and method for fusing instructions queued during a time window defined by a delay counter |
PCT/US2009/062219 WO2010056511A2 (en) | 2008-10-30 | 2009-10-27 | Technique for promoting efficient instruction fusion |
Publications (2)
Publication Number | Publication Date |
---|---|
BRPI0920782A2 true BRPI0920782A2 (pt) | 2015-12-22 |
BRPI0920782B1 BRPI0920782B1 (pt) | 2020-04-22 |
Family
ID=42063260
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI0920782A BRPI0920782B1 (pt) | 2008-10-30 | 2009-10-27 | aparelho, método e sistema para executar fusão eficiente de instruções |
BRPI0904287-3A BRPI0904287A2 (pt) | 2008-10-30 | 2009-10-30 | técnica para promover a fusão de instrução eficiente |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI0904287-3A BRPI0904287A2 (pt) | 2008-10-30 | 2009-10-30 | técnica para promover a fusão de instrução eficiente |
Country Status (8)
Country | Link |
---|---|
US (4) | US9690591B2 (pt) |
JP (2) | JP2012507794A (pt) |
KR (1) | KR101258762B1 (pt) |
CN (2) | CN101901128B (pt) |
BR (2) | BRPI0920782B1 (pt) |
DE (1) | DE102009051388A1 (pt) |
TW (1) | TWI455023B (pt) |
WO (1) | WO2010056511A2 (pt) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8090931B2 (en) * | 2008-09-18 | 2012-01-03 | Via Technologies, Inc. | Microprocessor with fused store address/store data microinstruction |
US9690591B2 (en) * | 2008-10-30 | 2017-06-27 | Intel Corporation | System and method for fusing instructions queued during a time window defined by a delay counter |
JP5491071B2 (ja) * | 2009-05-20 | 2014-05-14 | エヌイーシーコンピュータテクノ株式会社 | 命令融合演算装置および命令融合演算方法 |
US9223578B2 (en) * | 2009-09-25 | 2015-12-29 | Nvidia Corporation | Coalescing memory barrier operations across multiple parallel threads |
US8856496B2 (en) | 2010-04-27 | 2014-10-07 | Via Technologies, Inc. | Microprocessor that fuses load-alu-store and JCC macroinstructions |
US8850164B2 (en) | 2010-04-27 | 2014-09-30 | Via Technologies, Inc. | Microprocessor that fuses MOV/ALU/JCC instructions |
US20130081001A1 (en) * | 2011-09-23 | 2013-03-28 | Microsoft Corporation | Immediate delay tracker tool |
US9672037B2 (en) * | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
US9483266B2 (en) | 2013-03-15 | 2016-11-01 | Intel Corporation | Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources |
US9886277B2 (en) * | 2013-03-15 | 2018-02-06 | Intel Corporation | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
US9329848B2 (en) * | 2013-03-27 | 2016-05-03 | Intel Corporation | Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs |
US9792121B2 (en) | 2013-05-21 | 2017-10-17 | Via Technologies, Inc. | Microprocessor that fuses if-then instructions |
US9348596B2 (en) | 2013-06-28 | 2016-05-24 | International Business Machines Corporation | Forming instruction groups based on decode time instruction optimization |
US9372695B2 (en) * | 2013-06-28 | 2016-06-21 | Globalfoundries Inc. | Optimization of instruction groups across group boundaries |
US10503513B2 (en) * | 2013-10-23 | 2019-12-10 | Nvidia Corporation | Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type |
WO2016042353A1 (en) * | 2014-09-18 | 2016-03-24 | Via Alliance Semiconductor Co., Ltd. | Cache management request fusing |
US20160179542A1 (en) * | 2014-12-23 | 2016-06-23 | Patrick P. Lai | Instruction and logic to perform a fused single cycle increment-compare-jump |
US10579389B2 (en) * | 2015-11-02 | 2020-03-03 | Arm Limited | Fusion of instructions by delaying handling of a partial subset of a fusible group of instructions |
US10387988B2 (en) | 2016-02-26 | 2019-08-20 | Google Llc | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
US10387147B2 (en) * | 2017-08-02 | 2019-08-20 | International Business Machines Corporation | Managing an issue queue for fused instructions and paired instructions in a microprocessor |
US11157280B2 (en) | 2017-12-07 | 2021-10-26 | International Business Machines Corporation | Dynamic fusion based on operand size |
US11256509B2 (en) | 2017-12-07 | 2022-02-22 | International Business Machines Corporation | Instruction fusion after register rename |
US11416252B2 (en) * | 2017-12-27 | 2022-08-16 | Arm Limited | Program instruction fusion |
US11194722B2 (en) * | 2018-03-15 | 2021-12-07 | Intel Corporation | Apparatus and method for improved cache utilization and efficiency on a many core processor |
US10929136B2 (en) | 2018-04-11 | 2021-02-23 | Futurewei Technologies, Inc. | Accurate early branch prediction using multiple predictors having different accuracy and latency in high-performance microprocessors |
US20200042322A1 (en) * | 2018-08-03 | 2020-02-06 | Futurewei Technologies, Inc. | System and method for store instruction fusion in a microprocessor |
US10831480B2 (en) * | 2019-02-25 | 2020-11-10 | International Business Machines Corporation | Move data and set storage key instruction |
US10831496B2 (en) | 2019-02-28 | 2020-11-10 | International Business Machines Corporation | Method to execute successive dependent instructions from an instruction stream in a processor |
US11216278B2 (en) * | 2019-08-12 | 2022-01-04 | Advanced New Technologies Co., Ltd. | Multi-thread processing |
KR102339882B1 (ko) | 2020-01-24 | 2021-12-14 | 정종범 | 역압대응이 가능한 티 모션 진자식 게이트밸브 |
US11249757B1 (en) | 2020-08-14 | 2022-02-15 | International Business Machines Corporation | Handling and fusing load instructions in a processor |
CN112363762B (zh) * | 2020-11-13 | 2023-01-06 | 苏州浪潮智能科技有限公司 | 一种融合命令处理方法、***、设备以及介质 |
US12008369B1 (en) | 2021-08-31 | 2024-06-11 | Apple Inc. | Load instruction fusion |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2834171B2 (ja) | 1989-02-06 | 1998-12-09 | 株式会社日立製作所 | コンパイル方法 |
US5392228A (en) | 1993-12-06 | 1995-02-21 | Motorola, Inc. | Result normalizer and method of operation |
US5860154A (en) | 1994-08-02 | 1999-01-12 | Intel Corporation | Method and apparatus for calculating effective memory addresses |
US6006324A (en) | 1995-01-25 | 1999-12-21 | Advanced Micro Devices, Inc. | High performance superscalar alignment unit |
JP3113792B2 (ja) | 1995-04-27 | 2000-12-04 | 松下電器産業株式会社 | 最適化装置 |
US6151618A (en) | 1995-12-04 | 2000-11-21 | Microsoft Corporation | Safe general purpose virtual machine computing system |
US6041403A (en) | 1996-09-27 | 2000-03-21 | Intel Corporation | Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction |
US5860107A (en) | 1996-10-07 | 1999-01-12 | International Business Machines Corporation | Processor and method for store gathering through merged store operations |
US5957997A (en) | 1997-04-25 | 1999-09-28 | International Business Machines Corporation | Efficient floating point normalization mechanism |
US5903761A (en) | 1997-10-31 | 1999-05-11 | Preemptive Solutions, Inc. | Method of reducing the number of instructions in a program code sequence |
US6112293A (en) | 1997-11-17 | 2000-08-29 | Advanced Micro Devices, Inc. | Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result |
US6282634B1 (en) | 1998-05-27 | 2001-08-28 | Arm Limited | Apparatus and method for processing data having a mixed vector/scalar register file |
US6247113B1 (en) | 1998-05-27 | 2001-06-12 | Arm Limited | Coprocessor opcode division by data type |
US6018799A (en) | 1998-07-22 | 2000-01-25 | Sun Microsystems, Inc. | Method, apparatus and computer program product for optimizing registers in a stack using a register allocator |
US6742110B2 (en) | 1998-10-06 | 2004-05-25 | Texas Instruments Incorporated | Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution |
TW477936B (en) * | 1998-12-29 | 2002-03-01 | Ind Tech Res Inst | Instruction folding method and device used in a stack machine |
US6338136B1 (en) * | 1999-05-18 | 2002-01-08 | Ip-First, Llc | Pairing of load-ALU-store with conditional branch |
US6647489B1 (en) | 2000-06-08 | 2003-11-11 | Ip-First, Llc | Compare branch instruction pairing within a single integer pipeline |
US20030023960A1 (en) | 2001-07-25 | 2003-01-30 | Shoab Khan | Microprocessor instruction format using combination opcodes and destination prefixes |
US6675376B2 (en) | 2000-12-29 | 2004-01-06 | Intel Corporation | System and method for fusing instructions |
US6832307B2 (en) | 2001-07-19 | 2004-12-14 | Stmicroelectronics, Inc. | Instruction fetch buffer stack fold decoder for generating foldable instruction status information |
US6587929B2 (en) * | 2001-07-31 | 2003-07-01 | Ip-First, L.L.C. | Apparatus and method for performing write-combining in a pipelined microprocessor using tags |
US6889318B1 (en) | 2001-08-07 | 2005-05-03 | Lsi Logic Corporation | Instruction fusion for digital signal processor |
US6718440B2 (en) | 2001-09-28 | 2004-04-06 | Intel Corporation | Memory access latency hiding with hint buffer |
US7051190B2 (en) | 2002-06-25 | 2006-05-23 | Intel Corporation | Intra-instruction fusion |
US6920546B2 (en) | 2002-08-13 | 2005-07-19 | Intel Corporation | Fusion of processor micro-operations |
US7653906B2 (en) * | 2002-10-23 | 2010-01-26 | Intel Corporation | Apparatus and method for reducing power consumption on simultaneous multi-threading systems |
US20040128485A1 (en) | 2002-12-27 | 2004-07-01 | Nelson Scott R. | Method for fusing instructions in a vector processor |
US7024544B2 (en) | 2003-06-24 | 2006-04-04 | Via-Cyrix, Inc. | Apparatus and method for accessing registers in a processor |
US7355601B2 (en) | 2003-06-30 | 2008-04-08 | International Business Machines Corporation | System and method for transfer of data between processors using a locked set, head and tail pointers |
KR101076815B1 (ko) | 2004-05-29 | 2011-10-25 | 삼성전자주식회사 | 분기 타겟 어드레스 캐쉬를 포함하는 캐쉬 시스템 |
US8082430B2 (en) * | 2005-08-09 | 2011-12-20 | Intel Corporation | Representing a plurality of instructions with a fewer number of micro-operations |
US7937564B1 (en) | 2005-09-28 | 2011-05-03 | Oracle America, Inc. | Emit vector optimization of a trace |
US7676513B2 (en) | 2006-01-06 | 2010-03-09 | Microsoft Corporation | Scheduling of index merges |
US7958181B2 (en) * | 2006-09-21 | 2011-06-07 | Intel Corporation | Method and apparatus for performing logical compare operations |
US7917568B2 (en) | 2007-04-10 | 2011-03-29 | Via Technologies, Inc. | X87 fused multiply-add instruction |
US9690591B2 (en) * | 2008-10-30 | 2017-06-27 | Intel Corporation | System and method for fusing instructions queued during a time window defined by a delay counter |
-
2008
- 2008-10-30 US US12/290,395 patent/US9690591B2/en active Active
-
2009
- 2009-10-27 WO PCT/US2009/062219 patent/WO2010056511A2/en active Application Filing
- 2009-10-27 BR BRPI0920782A patent/BRPI0920782B1/pt active IP Right Grant
- 2009-10-27 KR KR1020117007623A patent/KR101258762B1/ko active IP Right Grant
- 2009-10-27 JP JP2011534680A patent/JP2012507794A/ja active Pending
- 2009-10-29 TW TW098136712A patent/TWI455023B/zh active
- 2009-10-30 CN CN200910253081.5A patent/CN101901128B/zh active Active
- 2009-10-30 DE DE102009051388A patent/DE102009051388A1/de not_active Ceased
- 2009-10-30 BR BRPI0904287-3A patent/BRPI0904287A2/pt not_active Application Discontinuation
- 2009-10-30 CN CN201410054184.XA patent/CN103870243B/zh active Active
-
2014
- 2014-11-28 JP JP2014241108A patent/JP5902285B2/ja active Active
-
2016
- 2016-04-30 US US15/143,518 patent/US20160378487A1/en not_active Abandoned
- 2016-04-30 US US15/143,522 patent/US20160246600A1/en not_active Abandoned
- 2016-04-30 US US15/143,520 patent/US10649783B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR20110050715A (ko) | 2011-05-16 |
JP5902285B2 (ja) | 2016-04-13 |
CN103870243B (zh) | 2018-02-02 |
CN101901128B (zh) | 2016-04-27 |
KR101258762B1 (ko) | 2013-04-29 |
US20160378487A1 (en) | 2016-12-29 |
US20160246600A1 (en) | 2016-08-25 |
CN101901128A (zh) | 2010-12-01 |
WO2010056511A2 (en) | 2010-05-20 |
TWI455023B (zh) | 2014-10-01 |
TW201032129A (en) | 2010-09-01 |
WO2010056511A3 (en) | 2010-07-08 |
DE102009051388A1 (de) | 2010-05-06 |
CN103870243A (zh) | 2014-06-18 |
US9690591B2 (en) | 2017-06-27 |
US20100115248A1 (en) | 2010-05-06 |
JP2012507794A (ja) | 2012-03-29 |
BRPI0904287A2 (pt) | 2011-02-01 |
JP2015072707A (ja) | 2015-04-16 |
US10649783B2 (en) | 2020-05-12 |
BRPI0920782B1 (pt) | 2020-04-22 |
US20170003965A1 (en) | 2017-01-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
BRPI0920782A2 (pt) | técnica para promover a fusão eficientes de instruções | |
BRPI0919250A2 (pt) | métodos para a purificação de vírus | |
BRPI0923748A2 (pt) | Método para a preparação de dióis | |
BRPI1011809A2 (pt) | método para aprimoramento de uma rota de cache | |
BR112012014490A2 (pt) | processo para a preparação substituída de 1-o-acil-2-desóxi-2-fluoro-4-tio-beta-d-arabinofuranoses | |
BRPI1007160A2 (pt) | Método para esterilizar um material | |
BRPI0922490A2 (pt) | Método para produção de beta-santaleno | |
BRPI1014262A2 (pt) | anticorpos específicos para caderina-17 | |
BRPI1013482A2 (pt) | método para produzir um composto | |
BRPI1007459A2 (pt) | método para produção de manômeros olefínicos | |
BRPI1014267A2 (pt) | processo para a carbonitrificação | |
BRPI1015446A2 (pt) | material colorido para junção de pedras | |
BRPI1007529A2 (pt) | métodos para regeneração de tecido pancreático | |
BRPI0921739A2 (pt) | junção em t para estruturas em grelha | |
BR112012001731A2 (pt) | Processo para a preparação de 1-benzil-3-hidroximetil-1h-indazol | |
BRPI1010841A2 (pt) | método para a fabricação de fluoroalquilnitrilas | |
BRPI0923370A2 (pt) | Método para produção de titanossilicato | |
BRPI0911391A2 (pt) | método para controlar um soldador | |
BR112013012094A2 (pt) | método para a purifação de misturas | |
BR112013012096A2 (pt) | método para a purifação de misturas | |
FR2949371B3 (fr) | Agrafeuse | |
ES1071796Y (es) | Aparcamiento para bicicletas | |
BRPI1009145A2 (pt) | método para a fabricação de derivado de benzodiazepina | |
BRPI1008438A2 (pt) | Processo para a preparacao de colil-l-lisina | |
BRPI0811533A2 (pt) | Método para a produção de um vírus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] |
Free format text: REFERENTE AS 5A E 6A ANUIDADES. |
|
B08H | Application fees: decision cancelled [chapter 8.8 patent gazette] |
Free format text: REFERENTE AO DESPACHO 8.6 NA RPI 2376 DE 19/07/2016 |
|
B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
B06A | Patent application procedure suspended [chapter 6.1 patent gazette] | ||
B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 22/04/2020, OBSERVADAS AS CONDICOES LEGAIS. |