BR8401795A - Celulas e dispositivo de memoria com linhas de acesso compartilhadas - Google Patents

Celulas e dispositivo de memoria com linhas de acesso compartilhadas

Info

Publication number
BR8401795A
BR8401795A BR8401795A BR8401795A BR8401795A BR 8401795 A BR8401795 A BR 8401795A BR 8401795 A BR8401795 A BR 8401795A BR 8401795 A BR8401795 A BR 8401795A BR 8401795 A BR8401795 A BR 8401795A
Authority
BR
Brazil
Prior art keywords
cells
memory device
access lines
shared access
shared
Prior art date
Application number
BR8401795A
Other languages
English (en)
Inventor
Roy Edwin Scheurlein
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8401795A publication Critical patent/BR8401795A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
BR8401795A 1983-04-18 1984-04-17 Celulas e dispositivo de memoria com linhas de acesso compartilhadas BR8401795A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/485,808 US4574365A (en) 1983-04-18 1983-04-18 Shared access lines memory cells

Publications (1)

Publication Number Publication Date
BR8401795A true BR8401795A (pt) 1984-12-04

Family

ID=23929516

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8401795A BR8401795A (pt) 1983-04-18 1984-04-17 Celulas e dispositivo de memoria com linhas de acesso compartilhadas

Country Status (8)

Country Link
US (1) US4574365A (pt)
EP (1) EP0128273B1 (pt)
JP (1) JPS59195397A (pt)
AU (1) AU560391B2 (pt)
BR (1) BR8401795A (pt)
CA (1) CA1213981A (pt)
DE (1) DE3478882D1 (pt)
ES (1) ES8501558A1 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648073A (en) * 1984-12-31 1987-03-03 International Business Machines Corporation Sequential shared access lines memory cells
US4907283A (en) * 1987-03-13 1990-03-06 Canon Kabushiki Kaisha Image processing apparatus
DE69621870T2 (de) * 1995-03-31 2003-01-02 Infineon Technologies Ag Nieder-Leistungs-Leseverstärker des Typs Gain Speicherzelle
US6282115B1 (en) 1999-12-22 2001-08-28 International Business Machines Corporation Multi-level DRAM trench store utilizing two capacitors and two plates
US6580650B2 (en) 2001-03-16 2003-06-17 International Business Machines Corporation DRAM word line voltage control to insure full cell writeback level
US7764549B2 (en) * 2005-06-20 2010-07-27 Sandisk 3D Llc Floating body memory cell system and method of manufacture
US7317641B2 (en) * 2005-06-20 2008-01-08 Sandisk Corporation Volatile memory cell two-pass writing method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US419095A (en) * 1890-01-07 Corn-planter
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
US3893087A (en) * 1974-02-08 1975-07-01 Gen Instrument Corp Random access memory with shared column conductors
US3979734A (en) * 1975-06-16 1976-09-07 International Business Machines Corporation Multiple element charge storage memory cell
US4086662A (en) * 1975-11-07 1978-04-25 Hitachi, Ltd. Memory system with read/write control lines
US4040016A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Twin nodes capacitance memory
US4040017A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Injected charge capacitor memory
US4080590A (en) * 1976-03-31 1978-03-21 International Business Machines Corporation Capacitor storage memory
JPS5951074B2 (ja) * 1980-03-28 1984-12-12 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPH0355911B2 (pt) 1991-08-26
AU560391B2 (en) 1987-04-02
EP0128273A2 (en) 1984-12-19
ES529781A0 (es) 1984-11-16
EP0128273A3 (en) 1986-12-17
CA1213981A (en) 1986-11-12
US4574365A (en) 1986-03-04
ES8501558A1 (es) 1984-11-16
JPS59195397A (ja) 1984-11-06
EP0128273B1 (en) 1989-07-05
AU2706984A (en) 1984-10-25
DE3478882D1 (en) 1989-08-10

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)