BR112015019392A2 - gerenciamento de latência de memória - Google Patents

gerenciamento de latência de memória

Info

Publication number
BR112015019392A2
BR112015019392A2 BR112015019392A BR112015019392A BR112015019392A2 BR 112015019392 A2 BR112015019392 A2 BR 112015019392A2 BR 112015019392 A BR112015019392 A BR 112015019392A BR 112015019392 A BR112015019392 A BR 112015019392A BR 112015019392 A2 BR112015019392 A2 BR 112015019392A2
Authority
BR
Brazil
Prior art keywords
memory
data
memory latency
correction code
latency management
Prior art date
Application number
BR112015019392A
Other languages
English (en)
Other versions
BR112015019392B1 (pt
Inventor
Fanning Blaise
Hun Ooi Eng
J Royer Robert Jr
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015019392A2 publication Critical patent/BR112015019392A2/pt
Publication of BR112015019392B1 publication Critical patent/BR112015019392B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/313—In storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

resumo patente de invenção: "gerenciamento de latência de memória". a presente invenção refere-se a aparelhos, sistemas, e métodos para gerenciar operações de latência de memória. em uma (1) modalidade, um dispositivo eletrônico compreende um processador e uma lógica de controle de memória para receber os dados a partir de um dispositivo de memória remota, armazenar os dados em uma memória cache local, receber um indicador de código de correção de erro associado aos dados e implantar uma política de gerenciamento de dados em resposta ao indicador de código de correção de erro. outras modalidades também são reveladas e reivindicadas.
BR112015019392-7A 2013-03-13 2014-02-26 Aparelho de memória remota, controlador de memória e dispositivo eletrônico para gerenciamento de latência de memória. BR112015019392B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
MYPI2013000863 2013-03-13
MYPI2013000863A MY180992A (en) 2013-03-13 2013-03-13 Memory latency management
PCT/US2014/018513 WO2014163880A1 (en) 2013-03-13 2014-02-26 Memory latency management

Publications (2)

Publication Number Publication Date
BR112015019392A2 true BR112015019392A2 (pt) 2017-07-18
BR112015019392B1 BR112015019392B1 (pt) 2022-10-11

Family

ID=51658789

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015019392-7A BR112015019392B1 (pt) 2013-03-13 2014-02-26 Aparelho de memória remota, controlador de memória e dispositivo eletrônico para gerenciamento de latência de memória.

Country Status (9)

Country Link
US (2) US9904592B2 (pt)
EP (1) EP2972916B1 (pt)
JP (1) JP6137582B2 (pt)
KR (1) KR101669784B1 (pt)
CN (1) CN105210046B (pt)
BR (1) BR112015019392B1 (pt)
MY (1) MY180992A (pt)
RU (1) RU2618938C2 (pt)
WO (1) WO2014163880A1 (pt)

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MY180992A (en) 2013-03-13 2020-12-15 Intel Corp Memory latency management
US10055164B2 (en) * 2016-09-07 2018-08-21 Sandisk Technologies Llc Data storage at an access device
US10069597B2 (en) * 2016-09-07 2018-09-04 Western Digital Technologies, Inc. Aggregated metadata transfer at a data storage device
US10282251B2 (en) * 2016-09-07 2019-05-07 Sandisk Technologies Llc System and method for protecting firmware integrity in a multi-processor non-volatile memory system
US10127184B2 (en) 2016-09-27 2018-11-13 Intel Corporation Low overheard high throughput solution for point-to-point link
CN108363544B (zh) * 2017-01-26 2021-05-07 建兴储存科技(广州)有限公司 固态储存装置及其读取重试方法
US10621091B2 (en) * 2018-05-04 2020-04-14 Micron Technology, Inc. Apparatuses and methods to perform continuous read operations
CN113050874A (zh) * 2019-12-26 2021-06-29 华为技术有限公司 一种内存设置方法以及装置

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Also Published As

Publication number Publication date
JP2016510927A (ja) 2016-04-11
US10572339B2 (en) 2020-02-25
CN105210046A (zh) 2015-12-30
US9904592B2 (en) 2018-02-27
KR20150104165A (ko) 2015-09-14
EP2972916A4 (en) 2017-04-12
MY180992A (en) 2020-12-15
RU2618938C2 (ru) 2017-05-11
EP2972916A1 (en) 2016-01-20
RU2015133910A (ru) 2017-02-17
WO2014163880A1 (en) 2014-10-09
KR101669784B1 (ko) 2016-10-27
CN105210046B (zh) 2021-10-19
BR112015019392B1 (pt) 2022-10-11
EP2972916B1 (en) 2020-12-30
US20160034345A1 (en) 2016-02-04
JP6137582B2 (ja) 2017-05-31
US20190129792A1 (en) 2019-05-02

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 26/02/2014, OBSERVADAS AS CONDICOES LEGAIS