BR112013018294A2 - sistema e método para suportar jit em um sistema seguro com faixas de memórias alocadas randomicamente - Google Patents

sistema e método para suportar jit em um sistema seguro com faixas de memórias alocadas randomicamente

Info

Publication number
BR112013018294A2
BR112013018294A2 BR112013018294A BR112013018294A BR112013018294A2 BR 112013018294 A2 BR112013018294 A2 BR 112013018294A2 BR 112013018294 A BR112013018294 A BR 112013018294A BR 112013018294 A BR112013018294 A BR 112013018294A BR 112013018294 A2 BR112013018294 A2 BR 112013018294A2
Authority
BR
Brazil
Prior art keywords
code
time
unsigned
jit
supporting
Prior art date
Application number
BR112013018294A
Other languages
English (en)
Inventor
Jacques Anthony Vidrine
Lionel Divyang Desai
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of BR112013018294A2 publication Critical patent/BR112013018294A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Stored Programmes (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

sistema e método para suportar jit em um sistema seguro com faixas de memórias alocadas randomicamente a presente invenição refere-se a sistemas, métodos e meios de armazenamento não transitórios, legíveis em computador, para processamento de código just-in-time em um dispositivo que impõe uma exigência de assinatura de código. a descrição inclui recebimento de código de computador, em que uma porção do código just-in-time executável, em um dispositivo que impõe uma exigência de assinatura de código; identificação da porção executável de código just-in-time não assinado; alocação de uma região de memória selecionada randomicamente no dispositivo para pelo menos alguma da porção executável just-in-time não assinada; e execução da porção de código executável just-in-time não assinada na região da memória selecionada randomicamente, como se a porção de código executável just-in-time não assinada fosse código de computador assinado.
BR112013018294A 2011-01-18 2012-01-18 sistema e método para suportar jit em um sistema seguro com faixas de memórias alocadas randomicamente BR112013018294A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/008,880 US8646050B2 (en) 2011-01-18 2011-01-18 System and method for supporting JIT in a secure system with randomly allocated memory ranges
PCT/US2012/021696 WO2012099945A1 (en) 2011-01-18 2012-01-18 System and method for supporting jit in a secure system with randomly allocated memory ranges

Publications (1)

Publication Number Publication Date
BR112013018294A2 true BR112013018294A2 (pt) 2016-11-16

Family

ID=45615051

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112013018294A BR112013018294A2 (pt) 2011-01-18 2012-01-18 sistema e método para suportar jit em um sistema seguro com faixas de memórias alocadas randomicamente

Country Status (11)

Country Link
US (1) US8646050B2 (pt)
EP (1) EP2666116B1 (pt)
JP (1) JP5647360B2 (pt)
KR (1) KR101504857B1 (pt)
CN (1) CN103329139B (pt)
AU (1) AU2012200181B2 (pt)
BR (1) BR112013018294A2 (pt)
DE (1) DE102012200613A1 (pt)
GB (1) GB2487645B (pt)
MX (1) MX2013008218A (pt)
WO (1) WO2012099945A1 (pt)

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Also Published As

Publication number Publication date
EP2666116A1 (en) 2013-11-27
EP2666116B1 (en) 2018-01-10
CN103329139B (zh) 2016-08-10
KR20130114733A (ko) 2013-10-17
JP2014504764A (ja) 2014-02-24
AU2012200181B2 (en) 2014-04-17
KR101504857B1 (ko) 2015-03-20
DE102012200613A1 (de) 2012-12-06
MX2013008218A (es) 2013-08-09
GB201200836D0 (en) 2012-02-29
GB2487645B (en) 2014-03-19
US20120185700A1 (en) 2012-07-19
JP5647360B2 (ja) 2014-12-24
AU2012200181A1 (en) 2012-08-02
CN103329139A (zh) 2013-09-25
WO2012099945A1 (en) 2012-07-26
US8646050B2 (en) 2014-02-04
GB2487645A (en) 2012-08-01

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]