BR0114169A - Método e equipamento para codificação de códigos de blocos lineares - Google Patents

Método e equipamento para codificação de códigos de blocos lineares

Info

Publication number
BR0114169A
BR0114169A BR0114169-4A BR0114169A BR0114169A BR 0114169 A BR0114169 A BR 0114169A BR 0114169 A BR0114169 A BR 0114169A BR 0114169 A BR0114169 A BR 0114169A
Authority
BR
Brazil
Prior art keywords
equipment
linear block
block codes
coding
coding linear
Prior art date
Application number
BR0114169-4A
Other languages
English (en)
Inventor
James Y Hurt
Jeffrey A Levin
Nikolai Schlegel
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR0114169A publication Critical patent/BR0114169A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Algebra (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

MéTODO E EQUIPAMENTO PARA CODIFICAçãO DE CóDIGOS DE BLOCOS LINEARES". Um método e um equipamento para codificação eficiente de códigos de bloco linear usa uma tabela de consulta incluindo um conjunto de respostas ao impulso para dar suporte a desempenho mais rápido por codificação em paralelo. As vantagens incluem uma capacidade de escalonamento ausente nos esquemas existentes.
BR0114169-4A 2000-09-26 2001-09-14 Método e equipamento para codificação de códigos de blocos lineares BR0114169A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/671,372 US6763492B1 (en) 2000-09-26 2000-09-26 Method and apparatus for encoding of linear block codes
PCT/US2001/028496 WO2002027939A2 (en) 2000-09-26 2001-09-14 Method and apparatus for encoding of linear block codes

Publications (1)

Publication Number Publication Date
BR0114169A true BR0114169A (pt) 2003-12-09

Family

ID=24694257

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0114169-4A BR0114169A (pt) 2000-09-26 2001-09-14 Método e equipamento para codificação de códigos de blocos lineares

Country Status (15)

Country Link
US (1) US6763492B1 (pt)
EP (2) EP1323235A2 (pt)
JP (1) JP2004510380A (pt)
KR (1) KR100894234B1 (pt)
CN (2) CN1333530C (pt)
AU (1) AU2001289032A1 (pt)
BR (1) BR0114169A (pt)
CA (1) CA2423425A1 (pt)
HK (1) HK1061121A1 (pt)
IL (1) IL154898A0 (pt)
MX (1) MXPA03002622A (pt)
NO (1) NO20031352L (pt)
RU (1) RU2003112223A (pt)
TW (1) TW531973B (pt)
WO (1) WO2002027939A2 (pt)

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US6904558B2 (en) * 2002-02-22 2005-06-07 Agilent Technologies, Inc. Methods for computing the CRC of a message from the incremental CRCs of composite sub-messages
US7458006B2 (en) * 2002-02-22 2008-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for computing the CRC of a message from the incremental CRCs of composite sub-messages
DE60236896D1 (de) * 2002-04-22 2010-08-12 Fujitsu Ltd Fehlerdetektionscodierer und -decodierer
JP4125718B2 (ja) * 2002-06-28 2008-07-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 識別データブロックの生成方法及び装置
US7434150B1 (en) 2004-03-03 2008-10-07 Marvell Israel (M.I.S.L.) Ltd. Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations
US7360142B1 (en) 2004-03-03 2008-04-15 Marvell Semiconductor Israel Ltd. Methods, architectures, circuits, software and systems for CRC determination
JP2006060663A (ja) * 2004-08-23 2006-03-02 Oki Electric Ind Co Ltd 巡回符号回路
SE0403218D0 (sv) * 2004-12-30 2004-12-30 Ericsson Telefon Ab L M Method and apparatus relating to communication-
DE102005018248B4 (de) * 2005-04-19 2014-06-12 Deutsche Gesetzliche Unfallversicherung E.V. (Dguv) Prüfverfahren zur sicheren, beschleunigten Erkennung von Datenfehlern und Vorrichtung zur Durchführung des Prüfverfahrens
US7500174B2 (en) 2005-05-23 2009-03-03 Microsoft Corporation Encoding and application of extended hamming checksum
KR100850787B1 (ko) * 2006-12-08 2008-08-06 한국전자통신연구원 상위 인터페이스 메모리를 이용한 시공간 블록 코드 방식의인코딩 장치 및 그 방법
US8103934B2 (en) 2007-12-21 2012-01-24 Honeywell International Inc. High speed memory error detection and correction using interleaved (8,4) LBCs
US9003259B2 (en) * 2008-11-26 2015-04-07 Red Hat, Inc. Interleaved parallel redundancy check calculation for memory devices
RU2585992C2 (ru) * 2012-01-11 2016-06-10 Шэньчжэнь Хэк Телеком Текнолоджи Ко., Лтд. Система и способ для беспроводной связи
CN107302420B (zh) * 2017-06-20 2019-11-08 北京科技大学 一种线性网络编码方法
CN111146986B (zh) * 2019-12-30 2022-08-12 深圳市越疆科技有限公司 磁编码器的位置定位方法、装置、电子设备及计算机可读存储介质

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US4623999A (en) * 1984-06-04 1986-11-18 E-Systems, Inc. Look-up table encoder for linear block codes
JPH03272224A (ja) * 1990-03-20 1991-12-03 Canon Inc 情報信号処理方法
EP0470451A3 (en) 1990-08-07 1993-01-20 National Semiconductor Corporation Implementation of the high-level data link control cyclic redundancy check (hdlc crc) calculation
EP0631703A4 (en) 1992-12-29 1996-03-20 Codex Corp DEVICE AND METHOD FOR THE POWERFUL GENERATION AND TESTING OF CRC REMAINS.
DE69320321T2 (de) 1993-02-05 1998-12-24 Hewlett-Packard Co., Palo Alto, Calif. Verfahren und Gerät zum Nachprüfen von CRC-Koden, wobei CRC Teilkode kombiniert werden
US5491700A (en) * 1993-10-01 1996-02-13 Pacific Communication Sciences, Inc. Method and apparatus for code error correction using an ordered syndrome and error correction lookup table
JPH07264078A (ja) * 1994-03-23 1995-10-13 Kokusai Electric Co Ltd Ｂｃｈ符号化装置及びｂｃｈ符号化方法
US5703887A (en) * 1994-12-23 1997-12-30 General Instrument Corporation Of Delaware Synchronization and error detection in a packetized data stream
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Also Published As

Publication number Publication date
HK1061121A1 (en) 2004-09-03
RU2003112223A (ru) 2004-08-27
CN1333530C (zh) 2007-08-22
US6763492B1 (en) 2004-07-13
WO2002027939A2 (en) 2002-04-04
TW531973B (en) 2003-05-11
AU2001289032A1 (en) 2002-04-08
EP1323235A2 (en) 2003-07-02
EP2209215A1 (en) 2010-07-21
CA2423425A1 (en) 2002-04-04
WO2002027939A3 (en) 2002-05-30
NO20031352L (no) 2003-05-08
NO20031352D0 (no) 2003-03-25
CN1476675A (zh) 2004-02-18
KR20030036826A (ko) 2003-05-09
KR100894234B1 (ko) 2009-04-20
JP2004510380A (ja) 2004-04-02
MXPA03002622A (es) 2004-05-24
IL154898A0 (en) 2003-10-31
CN101083468A (zh) 2007-12-05

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 11A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2167 DE 17/07/2012.